AU2001261395A1 - Phase locked loop having dc bias circuitry - Google Patents

Phase locked loop having dc bias circuitry

Info

Publication number
AU2001261395A1
AU2001261395A1 AU2001261395A AU6139501A AU2001261395A1 AU 2001261395 A1 AU2001261395 A1 AU 2001261395A1 AU 2001261395 A AU2001261395 A AU 2001261395A AU 6139501 A AU6139501 A AU 6139501A AU 2001261395 A1 AU2001261395 A1 AU 2001261395A1
Authority
AU
Australia
Prior art keywords
locked loop
phase locked
bias circuitry
circuitry
bias
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001261395A
Inventor
Rejean Beaulieu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Marconi Communications Inc
Original Assignee
Marconi Communications Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marconi Communications Inc filed Critical Marconi Communications Inc
Publication of AU2001261395A1 publication Critical patent/AU2001261395A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/191—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using at least two different signals from the frequency divider or the counter for determining the time difference
AU2001261395A 2000-07-19 2001-05-10 Phase locked loop having dc bias circuitry Abandoned AU2001261395A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/618,882 US6304115B1 (en) 2000-07-19 2000-07-19 Phase locked loop having DC bias circuitry
US09/618,882 2000-07-19
PCT/US2001/015144 WO2002009289A2 (en) 2000-07-19 2001-05-10 Phase locked loop having dc bias circuitry

Publications (1)

Publication Number Publication Date
AU2001261395A1 true AU2001261395A1 (en) 2002-02-05

Family

ID=24479516

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001261395A Abandoned AU2001261395A1 (en) 2000-07-19 2001-05-10 Phase locked loop having dc bias circuitry

Country Status (3)

Country Link
US (2) US6304115B1 (en)
AU (1) AU2001261395A1 (en)
WO (1) WO2002009289A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6929771B1 (en) * 2000-07-31 2005-08-16 High Voltage Graphics, Inc. Method of decorating a molded article
US7688928B2 (en) * 2006-09-05 2010-03-30 Lsi Corporation Duty cycle counting phase calibration scheme of an input/output (I/O) interface
US9629110B2 (en) * 2013-04-03 2017-04-18 Keysight Technologies Singapore (Holdings) Pte. Ltd. Wireless communication apparatus and method performing signal scanning to determine the strongest signal useable for stabilizing a local oscillator
US9831766B2 (en) * 2015-11-19 2017-11-28 Mediatek Inc. Charge pump and associated phase-locked loop and clock and data recovery
CN108011620B (en) * 2016-10-31 2023-08-08 深圳市研祥智慧科技股份有限公司 Fast clock recovery circuit based on FPGA

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5254955A (en) 1989-08-25 1993-10-19 Anritsu Corporation Advanced phase locked loop circuit
JPH04262618A (en) * 1991-02-18 1992-09-18 Advantest Corp Phase detector
US5699387A (en) * 1993-06-23 1997-12-16 Ati Technologies Inc. Phase offset cancellation technique for reducing low frequency jitters
US5663685A (en) * 1996-03-29 1997-09-02 Bull Hn Information Systems Inc. Dual flip-flop detector type phase locked loop incorporating dynamic phase offset correction
US5754598A (en) * 1996-05-23 1998-05-19 Motorola, Inc. Method and apparatus for controlling a phase lock loop
US5920233A (en) * 1996-11-18 1999-07-06 Peregrine Semiconductor Corp. Phase locked loop including a sampling circuit for reducing spurious side bands
JP3055607B2 (en) * 1997-05-29 2000-06-26 日本電気株式会社 Phase locked loop circuit using Schmitt trigger circuit

Also Published As

Publication number Publication date
US6304115B1 (en) 2001-10-16
US20020030519A1 (en) 2002-03-14
WO2002009289A3 (en) 2002-08-29
WO2002009289A2 (en) 2002-01-31
US6466068B2 (en) 2002-10-15

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