AU2001257238A1 - Speed cache having separate arbitration for second-level tag and data cache rams - Google Patents

Speed cache having separate arbitration for second-level tag and data cache rams

Info

Publication number
AU2001257238A1
AU2001257238A1 AU2001257238A AU5723801A AU2001257238A1 AU 2001257238 A1 AU2001257238 A1 AU 2001257238A1 AU 2001257238 A AU2001257238 A AU 2001257238A AU 5723801 A AU5723801 A AU 5723801A AU 2001257238 A1 AU2001257238 A1 AU 2001257238A1
Authority
AU
Australia
Prior art keywords
cache
rams
level tag
separate arbitration
data cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001257238A
Inventor
Rajasekhar Cherabuddi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of AU2001257238A1 publication Critical patent/AU2001257238A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0857—Overlapped cache accessing, e.g. pipeline by multiple requestors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU2001257238A 2000-05-17 2001-04-24 Speed cache having separate arbitration for second-level tag and data cache rams Abandoned AU2001257238A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US57261100A 2000-05-17 2000-05-17
US09572611 2000-05-17
PCT/US2001/013269 WO2001088719A2 (en) 2000-05-17 2001-04-24 Speed cache having separate arbitration for second-level tag and data cache rams

Publications (1)

Publication Number Publication Date
AU2001257238A1 true AU2001257238A1 (en) 2001-11-26

Family

ID=24288605

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001257238A Abandoned AU2001257238A1 (en) 2000-05-17 2001-04-24 Speed cache having separate arbitration for second-level tag and data cache rams

Country Status (2)

Country Link
AU (1) AU2001257238A1 (en)
WO (1) WO2001088719A2 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5692152A (en) * 1994-06-29 1997-11-25 Exponential Technology, Inc. Master-slave cache system with de-coupled data and tag pipelines and loop-back
US5809537A (en) * 1995-12-08 1998-09-15 International Business Machines Corp. Method and system for simultaneous processing of snoop and cache operations

Also Published As

Publication number Publication date
WO2001088719A3 (en) 2002-03-07
WO2001088719A2 (en) 2001-11-22

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