AU2001255351A1 - Fault-tolerant computer system with voter delay buffer - Google Patents

Fault-tolerant computer system with voter delay buffer

Info

Publication number
AU2001255351A1
AU2001255351A1 AU2001255351A AU5535101A AU2001255351A1 AU 2001255351 A1 AU2001255351 A1 AU 2001255351A1 AU 2001255351 A AU2001255351 A AU 2001255351A AU 5535101 A AU5535101 A AU 5535101A AU 2001255351 A1 AU2001255351 A1 AU 2001255351A1
Authority
AU
Australia
Prior art keywords
fault
computer system
delay buffer
tolerant computer
voter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001255351A
Inventor
Wen-Yin Huang
Jeffrey S. Somers
Mark Tetreault
Timothy M. Wegener
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Stratus Technologies Bermuda Ltd
Original Assignee
R L STRATUS TECHNOLOGIES INTER
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by R L STRATUS TECHNOLOGIES INTER filed Critical R L STRATUS TECHNOLOGIES INTER
Publication of AU2001255351A1 publication Critical patent/AU2001255351A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/165—Error detection by comparing the output of redundant processing systems with continued operation after detection of the error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
AU2001255351A 2000-04-13 2001-04-12 Fault-tolerant computer system with voter delay buffer Abandoned AU2001255351A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/548,528 US6820213B1 (en) 2000-04-13 2000-04-13 Fault-tolerant computer system with voter delay buffer
US09548528 2000-04-13
PCT/US2001/012063 WO2001080009A2 (en) 2000-04-13 2001-04-12 Fault-tolerant computer system with voter delay buffer

Publications (1)

Publication Number Publication Date
AU2001255351A1 true AU2001255351A1 (en) 2001-10-30

Family

ID=24189225

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001255351A Abandoned AU2001255351A1 (en) 2000-04-13 2001-04-12 Fault-tolerant computer system with voter delay buffer

Country Status (3)

Country Link
US (1) US6820213B1 (en)
AU (1) AU2001255351A1 (en)
WO (1) WO2001080009A2 (en)

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US9734006B2 (en) * 2015-09-18 2017-08-15 Nxp Usa, Inc. System and method for error detection in a critical system
JP6083480B1 (en) * 2016-02-18 2017-02-22 日本電気株式会社 Monitoring device, fault tolerant system and method
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DE102017210955A1 (en) * 2017-06-28 2019-01-17 Volkswagen Aktiengesellschaft METHOD, DEVICE AND COMPUTER READABLE STORAGE MEDIUM WITH INSTRUCTIONS FOR RESOLVING REDUNDANCY OF TWO OR MORE REDUNDANT MODULES
EP3428748B1 (en) * 2017-07-13 2020-08-26 Siemens Aktiengesellschaft Method and assembly for operating two redundant systems
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