AU2001251071A1 - Protection for input buffers of flash memories - Google Patents

Protection for input buffers of flash memories

Info

Publication number
AU2001251071A1
AU2001251071A1 AU2001251071A AU5107101A AU2001251071A1 AU 2001251071 A1 AU2001251071 A1 AU 2001251071A1 AU 2001251071 A AU2001251071 A AU 2001251071A AU 5107101 A AU5107101 A AU 5107101A AU 2001251071 A1 AU2001251071 A1 AU 2001251071A1
Authority
AU
Australia
Prior art keywords
input signal
node
protection
flash memories
input buffers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001251071A
Inventor
Elio D'ambrosio
Giulio-Giuseppe Marotta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of AU2001251071A1 publication Critical patent/AU2001251071A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes

Abstract

A method for operating a buffering system and a system for enhancing buffering of a low-voltage integrated circuit are disclosed. The method comprises monitoring an input signal (S104); allowing a transfer of the input signal from a first node to a second node if the input signal is below a predetermined triggering voltage; inhibiting the transfer of the input signal from the first node to the second node if the input signal reaches the predetermined triggering voltage; and outputting the transferred input signal (S114).
AU2001251071A 2000-08-30 2001-03-28 Protection for input buffers of flash memories Abandoned AU2001251071A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09651478 2000-08-30
US09/651,478 US6628142B1 (en) 2000-08-30 2000-08-30 Enhanced protection for input buffers of low-voltage flash memories
PCT/US2001/010001 WO2002019525A1 (en) 2000-08-30 2001-03-28 Protection for input buffers of flash memories

Publications (1)

Publication Number Publication Date
AU2001251071A1 true AU2001251071A1 (en) 2002-03-13

Family

ID=24612993

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001251071A Abandoned AU2001251071A1 (en) 2000-08-30 2001-03-28 Protection for input buffers of flash memories

Country Status (8)

Country Link
US (3) US6628142B1 (en)
EP (2) EP1612799A3 (en)
JP (1) JP3973097B2 (en)
KR (1) KR100599889B1 (en)
AT (1) ATE296498T1 (en)
AU (1) AU2001251071A1 (en)
DE (1) DE60111060T2 (en)
WO (1) WO2002019525A1 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6628142B1 (en) * 2000-08-30 2003-09-30 Micron Technology, Inc. Enhanced protection for input buffers of low-voltage flash memories
ITRM20010556A1 (en) * 2001-09-12 2003-03-12 Micron Technology Inc DECODER TO DECODE SWITCHING COMMANDS IN INTEGRATED CIRCUIT TEST MODE.
US20050035806A1 (en) * 2003-07-24 2005-02-17 El-Sherif Alaa Y. Circuit and method to protect EEPROM data during ESD events
KR101548242B1 (en) * 2008-07-21 2015-09-04 삼성전자주식회사 Output driving device in semiconductor device method thereof and electronic processing device having the same
JP5675464B2 (en) * 2011-03-30 2015-02-25 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit
KR101857529B1 (en) 2011-11-08 2018-05-15 삼성전자주식회사 Nonvolatile memory device and driving method thereof
US11099774B2 (en) 2017-08-30 2021-08-24 Micron Technology, Inc. Command address input buffer bias current reduction
KR20220021638A (en) * 2020-08-14 2022-02-22 주식회사 엘엑스세미콘 High speed level shifter

Family Cites Families (23)

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JPS59224162A (en) 1983-06-03 1984-12-17 Ricoh Co Ltd Semiconductor protecting device
US5197033A (en) * 1986-07-18 1993-03-23 Hitachi, Ltd. Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions
US5300835A (en) * 1993-02-10 1994-04-05 Cirrus Logic, Inc. CMOS low power mixed voltage bidirectional I/O buffer
US5589783A (en) * 1994-07-29 1996-12-31 Sgs-Thomson Microelectronics, Inc. Variable input threshold adjustment
US5543734A (en) * 1994-08-30 1996-08-06 Intel Corporation Voltage supply isolation buffer
US5589790A (en) * 1995-06-30 1996-12-31 Intel Corporation Input structure for receiving high voltage signals on a low voltage integrated circuit device
US5594694A (en) * 1995-07-28 1997-01-14 Micron Quantum Devices, Inc. Memory circuit with switch for selectively connecting an input/output pad directly to a nonvolatile memory cell
JP3986578B2 (en) * 1996-01-17 2007-10-03 三菱電機株式会社 Synchronous semiconductor memory device
US6025737A (en) * 1996-11-27 2000-02-15 Altera Corporation Circuitry for a low internal voltage integrated circuit
JP2978783B2 (en) 1996-09-18 1999-11-15 静岡日本電気株式会社 Radio selective call receiver
US5933026A (en) * 1997-04-11 1999-08-03 Intel Corporation Self-configuring interface architecture on flash memories
KR100282708B1 (en) 1997-12-04 2001-02-15 윤종용 An input circuit of a semiconductor device (INPUT CIRCUIT OF SEMICONDUCTOR DEVICE)
US5875142A (en) * 1997-06-17 1999-02-23 Micron Technology, Inc. Integrated circuit with temperature detector
US5852540A (en) * 1997-09-24 1998-12-22 Intel Corporation Circuit for protecting the input/output stage of a low voltage integrated circuit device from a failure of the internal voltage supply or a difference in the power-up sequencing of supply voltage levels
US5973900A (en) 1997-10-31 1999-10-26 Micron Technology, Inc. High voltage protection for an integrated circuit input buffer
KR100269313B1 (en) * 1997-11-07 2000-12-01 윤종용 Semiconductor memory device for consuming small current at stand-by state
US6084430A (en) * 1997-12-31 2000-07-04 Intel Corporation Input buffer for a mixed voltage environment
US6031393A (en) * 1997-12-31 2000-02-29 Intel Corporation Pass gate input buffer for a mixed voltage environment
US6013932A (en) 1998-01-07 2000-01-11 Micron Technology, Inc. Supply voltage reduction circuit for integrated circuit
US6121795A (en) * 1998-02-26 2000-09-19 Xilinx, Inc. Low-voltage input/output circuit with high voltage tolerance
US6282145B1 (en) * 1999-01-14 2001-08-28 Silicon Storage Technology, Inc. Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system
KR100292408B1 (en) * 1999-03-04 2001-06-01 윤종용 High voltage tolerant interface circuit
US6628142B1 (en) * 2000-08-30 2003-09-30 Micron Technology, Inc. Enhanced protection for input buffers of low-voltage flash memories

Also Published As

Publication number Publication date
KR20030064392A (en) 2003-07-31
JP2004507961A (en) 2004-03-11
US20040071033A1 (en) 2004-04-15
US20050077920A1 (en) 2005-04-14
US7057416B2 (en) 2006-06-06
US6628142B1 (en) 2003-09-30
US6940310B2 (en) 2005-09-06
EP1314250B1 (en) 2005-05-25
KR100599889B1 (en) 2006-07-13
DE60111060D1 (en) 2005-06-30
EP1314250A1 (en) 2003-05-28
EP1612799A3 (en) 2007-01-10
DE60111060T2 (en) 2006-01-26
ATE296498T1 (en) 2005-06-15
WO2002019525A1 (en) 2002-03-07
EP1612799A2 (en) 2006-01-04
JP3973097B2 (en) 2007-09-05

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