AU2001249188A1 - Method and apparatus for writing instructions into a buffer queue including overwriting invalid entries - Google Patents

Method and apparatus for writing instructions into a buffer queue including overwriting invalid entries

Info

Publication number
AU2001249188A1
AU2001249188A1 AU2001249188A AU4918801A AU2001249188A1 AU 2001249188 A1 AU2001249188 A1 AU 2001249188A1 AU 2001249188 A AU2001249188 A AU 2001249188A AU 4918801 A AU4918801 A AU 4918801A AU 2001249188 A1 AU2001249188 A1 AU 2001249188A1
Authority
AU
Australia
Prior art keywords
buffer queue
queue including
writing instructions
invalid entries
including overwriting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001249188A
Inventor
Per Hammarlund
Robert F Krick
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2001249188A1 publication Critical patent/AU2001249188A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
AU2001249188A 2000-03-30 2001-03-13 Method and apparatus for writing instructions into a buffer queue including overwriting invalid entries Abandoned AU2001249188A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09539734 2000-03-30
US09/539,734 US7149883B1 (en) 2000-03-30 2000-03-30 Method and apparatus selectively to advance a write pointer for a queue based on the indicated validity or invalidity of an instruction stored within the queue
PCT/US2001/008104 WO2001077821A1 (en) 2000-03-30 2001-03-13 Method and apparatus for writing instructions into a buffer queue including overwriting invalid entries

Publications (1)

Publication Number Publication Date
AU2001249188A1 true AU2001249188A1 (en) 2001-10-23

Family

ID=24152437

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001249188A Abandoned AU2001249188A1 (en) 2000-03-30 2001-03-13 Method and apparatus for writing instructions into a buffer queue including overwriting invalid entries

Country Status (4)

Country Link
US (1) US7149883B1 (en)
AU (1) AU2001249188A1 (en)
TW (1) TW522339B (en)
WO (1) WO2001077821A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7310722B2 (en) 2003-12-18 2007-12-18 Nvidia Corporation Across-thread out of order instruction dispatch in a multithreaded graphics processor
US20080072019A1 (en) * 2006-09-19 2008-03-20 Avinash Sodani Technique to clear bogus instructions from a processor pipeline
US8769207B2 (en) * 2008-01-16 2014-07-01 Via Technologies, Inc. Caching method and apparatus for a vertex shader and geometry shader
US11726783B2 (en) * 2020-04-23 2023-08-15 Advanced Micro Devices, Inc. Filtering micro-operations for a micro-operation cache in a processor
CN112579170B (en) * 2020-12-10 2022-11-08 海光信息技术股份有限公司 Processor and method for reducing virtual address calculation

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4682284A (en) 1984-12-06 1987-07-21 American Telephone & Telegraph Co., At&T Bell Lab. Queue administration method and apparatus
US4841476A (en) * 1986-10-06 1989-06-20 International Business Machines Corporation Extended floating point operations supporting emulation of source instruction execution
JP2560889B2 (en) 1990-05-22 1996-12-04 日本電気株式会社 Microprocessor
US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
WO1993017385A1 (en) 1992-02-27 1993-09-02 Intel Corporation Dynamic flow instruction cache memory
US5604909A (en) 1993-12-15 1997-02-18 Silicon Graphics Computer Systems, Inc. Apparatus for processing instructions in a computing system
US5680564A (en) 1995-05-26 1997-10-21 National Semiconductor Corporation Pipelined processor with two tier prefetch buffer structure and method with bypass
US6237074B1 (en) * 1995-05-26 2001-05-22 National Semiconductor Corp. Tagged prefetch and instruction decoder for variable length instruction set and method of operation
US6094729A (en) 1997-04-08 2000-07-25 Advanced Micro Devices, Inc. Debug interface including a compact trace record storage
US6014742A (en) 1997-12-31 2000-01-11 Intel Corporation Trace branch prediction unit
US6477562B2 (en) * 1998-12-16 2002-11-05 Clearwater Networks, Inc. Prioritized instruction scheduling for multi-streaming processors
US6704856B1 (en) * 1999-02-01 2004-03-09 Hewlett-Packard Development Company, L.P. Method for compacting an instruction queue

Also Published As

Publication number Publication date
TW522339B (en) 2003-03-01
WO2001077821A1 (en) 2001-10-18
US7149883B1 (en) 2006-12-12

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