AU2001247537A1 - Method for improving uniformity and reducing etch rate variation of etching polysilicon - Google Patents

Method for improving uniformity and reducing etch rate variation of etching polysilicon

Info

Publication number
AU2001247537A1
AU2001247537A1 AU2001247537A AU4753701A AU2001247537A1 AU 2001247537 A1 AU2001247537 A1 AU 2001247537A1 AU 2001247537 A AU2001247537 A AU 2001247537A AU 4753701 A AU4753701 A AU 4753701A AU 2001247537 A1 AU2001247537 A1 AU 2001247537A1
Authority
AU
Australia
Prior art keywords
chamber
substrate
etching
rate
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001247537A
Inventor
Tom Choi
Wenli Collison
Frank Y. Lin
Tuqiang Ni
Kenji Takeshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lam Research Corp
Original Assignee
Lam Research Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Research Corp filed Critical Lam Research Corp
Publication of AU2001247537A1 publication Critical patent/AU2001247537A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32623—Mechanical discharge control means
    • H01J37/32642—Focus rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • General Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Analytical Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

An apparatus and method for consecutively processing a series of semiconductor substrates with minimal plasma etch rate variation following cleaning with fluorine-containing gas and/or seasoning of the plasma etch chamber. The method includes steps of (a) placing a semiconductor substrate on a substrate support in a plasma etching chamber, (b) maintaining a vacuum in the chamber, (c) etching an exposed surface of the substrate by supplying an etching gas to the chamber and energizing the etching gas to form a plasma in the chamber, (d) removing the substrate from the chamber; and (e) consecutively etching additional substrates in the chamber by repeating steps (a-d), the etching step being carried out by minimizing a recombination rate of H and Br on a silicon carbide edge ring surrounding the substrate at a rate sufficient to offset a rate at which Br is consumed across the substrate. The method can be carried out using pure HBr or combination of HBr with other gases.
AU2001247537A 2000-03-31 2001-03-16 Method for improving uniformity and reducing etch rate variation of etching polysilicon Abandoned AU2001247537A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09540549 2000-03-31
US09/540,549 US6514378B1 (en) 2000-03-31 2000-03-31 Method for improving uniformity and reducing etch rate variation of etching polysilicon
PCT/US2001/008618 WO2001075958A2 (en) 2000-03-31 2001-03-16 Method for improving uniformity and reducing etch rate variation of etching polysilicon

Publications (1)

Publication Number Publication Date
AU2001247537A1 true AU2001247537A1 (en) 2001-10-15

Family

ID=24155925

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001247537A Abandoned AU2001247537A1 (en) 2000-03-31 2001-03-16 Method for improving uniformity and reducing etch rate variation of etching polysilicon

Country Status (9)

Country Link
US (1) US6514378B1 (en)
EP (1) EP1269529B1 (en)
JP (1) JP4907827B2 (en)
CN (1) CN1230879C (en)
AT (1) ATE475985T1 (en)
AU (1) AU2001247537A1 (en)
DE (1) DE60142685D1 (en)
TW (1) TWI249205B (en)
WO (1) WO2001075958A2 (en)

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CN102315112B (en) * 2011-09-28 2016-03-09 上海华虹宏力半导体制造有限公司 The lithographic method of stacked metal gate
CN102355792B (en) * 2011-10-19 2016-04-06 中微半导体设备(上海)有限公司 Improve the inductively coupled plasma device of plasma uniformity and efficiency
KR102068186B1 (en) 2012-02-29 2020-02-11 어플라이드 머티어리얼스, 인코포레이티드 Abatement and strip process chamber in a load lock configuration
US20160056059A1 (en) * 2014-08-22 2016-02-25 Applied Materials, Inc. Component for semiconductor process chamber having surface treatment to reduce particle emission
CN105676588A (en) * 2014-11-18 2016-06-15 北京北方微电子基地设备工艺研究中心有限责任公司 Substrate etching method
CN109119373A (en) * 2017-06-23 2019-01-01 北京北方华创微电子装备有限公司 pressure ring assembly and reaction chamber
CN108998834A (en) * 2018-07-26 2018-12-14 芜湖凯兴汽车电子有限公司 A kind of sensor monocrystalline silicon etching device
WO2023076078A1 (en) * 2021-10-29 2023-05-04 Lam Research Corporation Phased array antennas and methods for controlling uniformity in processing a substrate
CN118099922A (en) * 2024-04-28 2024-05-28 南京镭芯光电有限公司 Method for etching compound semiconductor multilayer structure by inductively coupled plasma

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Also Published As

Publication number Publication date
ATE475985T1 (en) 2010-08-15
CN1426597A (en) 2003-06-25
EP1269529B1 (en) 2010-07-28
TWI249205B (en) 2006-02-11
EP1269529A2 (en) 2003-01-02
JP2003529931A (en) 2003-10-07
US6514378B1 (en) 2003-02-04
WO2001075958A2 (en) 2001-10-11
DE60142685D1 (en) 2010-09-09
WO2001075958A3 (en) 2002-01-03
CN1230879C (en) 2005-12-07
JP4907827B2 (en) 2012-04-04

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