AU2001247428A1 - Process to minimize and/or eliminate conductive material coating over the top surface of a patterned substrate and layer structure made thereby - Google Patents

Process to minimize and/or eliminate conductive material coating over the top surface of a patterned substrate and layer structure made thereby

Info

Publication number
AU2001247428A1
AU2001247428A1 AU2001247428A AU4742801A AU2001247428A1 AU 2001247428 A1 AU2001247428 A1 AU 2001247428A1 AU 2001247428 A AU2001247428 A AU 2001247428A AU 4742801 A AU4742801 A AU 4742801A AU 2001247428 A1 AU2001247428 A1 AU 2001247428A1
Authority
AU
Australia
Prior art keywords
minimize
top surface
conductive material
layer structure
structure made
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001247428A
Inventor
Bulent M. Basol
Homayoun Talieh
Cyprian E. Uzoh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ASM Nutool Inc
Original Assignee
ASM Nutool Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ASM Nutool Inc filed Critical ASM Nutool Inc
Publication of AU2001247428A1 publication Critical patent/AU2001247428A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/04Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/042Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/04Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/046Lapping machines or devices; Accessories designed for working plane surfaces using electric current
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/22Electroplating combined with mechanical treatment during the deposition
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60Electroplating characterised by the structure or texture of the layers
    • C25D5/605Surface topography of the layers, e.g. rough, dendritic or nodular layers
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • C25D7/123Semiconductors first coated with a seed layer or a conductive layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684Smoothing; Planarisation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/423Plated through-holes or plated via connections characterised by electroplating method
AU2001247428A 2000-04-19 2001-03-05 Process to minimize and/or eliminate conductive material coating over the top surface of a patterned substrate and layer structure made thereby Abandoned AU2001247428A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US19837100P 2000-04-19 2000-04-19
US60198371 2000-04-19
US67180000A 2000-09-28 2000-09-28
US09671800 2000-09-28
PCT/US2001/008199 WO2001081043A1 (en) 2000-04-19 2001-03-15 Process to minimize and/or eliminate conductive material coating over the top surface of a patterned substrate and layer structure made thereby

Publications (1)

Publication Number Publication Date
AU2001247428A1 true AU2001247428A1 (en) 2001-11-07

Family

ID=26893718

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001247428A Abandoned AU2001247428A1 (en) 2000-04-19 2001-03-05 Process to minimize and/or eliminate conductive material coating over the top surface of a patterned substrate and layer structure made thereby

Country Status (3)

Country Link
AU (1) AU2001247428A1 (en)
TW (1) TW521338B (en)
WO (1) WO2001081043A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10154500B4 (en) * 2001-11-07 2004-09-23 Infineon Technologies Ag Process for the production of thin, structured, metal-containing layers with low electrical resistance
TWI587766B (en) * 2015-05-21 2017-06-11 健鼎科技股份有限公司 Electroplating method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69512971T2 (en) * 1994-08-09 2000-05-18 Ontrak Systems Inc Linear polisher and wafer planarization process
US5593344A (en) * 1994-10-11 1997-01-14 Ontrak Systems, Inc. Wafer polishing machine with fluid bearings and drive systems
US6176992B1 (en) * 1998-11-03 2001-01-23 Nutool, Inc. Method and apparatus for electro-chemical mechanical deposition
US6168704B1 (en) * 1999-02-04 2001-01-02 Advanced Micro Device, Inc. Site-selective electrochemical deposition of copper

Also Published As

Publication number Publication date
TW521338B (en) 2003-02-21
WO2001081043A1 (en) 2001-11-01

Similar Documents

Publication Publication Date Title
CA2326244A1 (en) Electrical connecting element and method of producing the same
EP0658930A3 (en) Varying the thickness of the surface silicon layer in a silicon-on-insulator substrate.
CA2186080A1 (en) Recoatable decorative sheet and recoatable decorative material
WO2001039288A8 (en) Method for patterning devices
AU2001228705A1 (en) Powder material for electrostatic application to a substrate and electrostatic application of the powder material to substrate
AU3862599A (en) Method of applying hard-facing material to a substrate
AU2002335842A1 (en) Method and materials for transferring a material onto a plasma treated surface according to a pattern
AU2001289826A1 (en) Process for surface modifying substrates and modified substrates resulting therefrom
CA2399614A1 (en) Flexible reflective insulating structures
AU1539900A (en) Method of fabrication of a ferro-electric capacitor and method of growing a pzt layer on a substrate
HK1048971A1 (en) Tableware, process for surface treatment thereof, substrate having hard decorative coating film, process for producing the substrate, and cutlery
AU2049801A (en) Fabrication of periodic surface structures with nanometer-scale spacings
GB0304305D0 (en) Coating for various types of substrate and method for the production thereof
AU4235196A (en) Forming a planar surface over a substrate by modifying the topography of the substrate
AU2002225682A1 (en) Methods and materials for the manufacture of a solid surface article
MY137728A (en) Corrugated diaphragm
GB2332650B (en) Etching substrate material,etching process,and article obtained by etching
WO2001034313A3 (en) Layer with a selectively functionalised surface
WO2004072374A3 (en) Sheet material and method of manufacture thereof
AU2001289007A1 (en) A method of applying a coating to a substrate
AU2001247428A1 (en) Process to minimize and/or eliminate conductive material coating over the top surface of a patterned substrate and layer structure made thereby
AU7344600A (en) Method of forming a conductive silicide layer on a silicon comprising substrate and method of forming a conductive silicide contact
AU2881900A (en) Decorative sheet material including mask layer
AU7389800A (en) Method of etching a wafer layer using multiple layers of the same photoresistantmaterial and structure formed thereby
AU2003224378A1 (en) Method of providing a substrate surface with a patterned layer