AU2001243402A1 - A method and apparatus for providing highly programmable memory mapping and improved interleaving - Google Patents

A method and apparatus for providing highly programmable memory mapping and improved interleaving

Info

Publication number
AU2001243402A1
AU2001243402A1 AU2001243402A AU4340201A AU2001243402A1 AU 2001243402 A1 AU2001243402 A1 AU 2001243402A1 AU 2001243402 A AU2001243402 A AU 2001243402A AU 4340201 A AU4340201 A AU 4340201A AU 2001243402 A1 AU2001243402 A1 AU 2001243402A1
Authority
AU
Australia
Prior art keywords
programmable memory
memory mapping
providing highly
highly programmable
improved interleaving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001243402A
Inventor
Daniel A. Manseau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2001243402A1 publication Critical patent/AU2001243402A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU2001243402A 2000-03-31 2001-02-28 A method and apparatus for providing highly programmable memory mapping and improved interleaving Abandoned AU2001243402A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/541,448 US6629219B1 (en) 2000-03-31 2000-03-31 Method and apparatus for providing highly programmable memory mapping and improved interleaving
US09541448 2000-03-31
PCT/US2001/006871 WO2001075606A2 (en) 2000-03-31 2001-02-28 A method and apparatus for providing highly programmable memory mapping and improved interleaving

Publications (1)

Publication Number Publication Date
AU2001243402A1 true AU2001243402A1 (en) 2001-10-15

Family

ID=24159637

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001243402A Abandoned AU2001243402A1 (en) 2000-03-31 2001-02-28 A method and apparatus for providing highly programmable memory mapping and improved interleaving

Country Status (3)

Country Link
US (1) US6629219B1 (en)
AU (1) AU2001243402A1 (en)
WO (1) WO2001075606A2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6834334B2 (en) * 2001-08-28 2004-12-21 International Business Machines Corporation Method and apparatus for address decoding of embedded DRAM devices
EP1388947A1 (en) * 2002-08-05 2004-02-11 Alcatel System with interleaver and deinterleaver
US20060164907A1 (en) * 2003-07-22 2006-07-27 Micron Technology, Inc. Multiple flash memory device management
US8806103B2 (en) * 2004-04-28 2014-08-12 Hewlett-Packard Development Company, L.P. System and method for interleaving memory
EP1607879A1 (en) * 2004-06-14 2005-12-21 Dialog Semiconductor GmbH Memory interleaving in a computer system
WO2006032103A1 (en) * 2004-09-24 2006-03-30 Synaptic Laboratories Limited METHOD OF AND APPARATUS FOR MAPPING n-BIT IDENTIFIERS OF FEWER THAN 2n RESOURCES
US8325768B2 (en) * 2005-08-24 2012-12-04 Intel Corporation Interleaving data packets in a packet-based communication system

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0823843B2 (en) 1991-10-11 1996-03-06 インターナショナル・ビジネス・マシーンズ・コーポレイション Memory controller and data processing system
US5530837A (en) 1994-03-28 1996-06-25 Hewlett-Packard Co. Methods and apparatus for interleaving memory transactions into an arbitrary number of banks
US5848258A (en) 1994-06-30 1998-12-08 Digital Equipment Corporation Memory bank addressing scheme
JPH10301842A (en) 1997-04-25 1998-11-13 Nec Corp Memory controller
US6185654B1 (en) 1998-07-17 2001-02-06 Compaq Computer Corporation Phantom resource memory address mapping system

Also Published As

Publication number Publication date
US6629219B1 (en) 2003-09-30
WO2001075606A3 (en) 2002-01-31
WO2001075606A2 (en) 2001-10-11

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