WO2006032103A1 - METHOD OF AND APPARATUS FOR MAPPING n-BIT IDENTIFIERS OF FEWER THAN 2n RESOURCES - Google Patents

METHOD OF AND APPARATUS FOR MAPPING n-BIT IDENTIFIERS OF FEWER THAN 2n RESOURCES Download PDF

Info

Publication number
WO2006032103A1
WO2006032103A1 PCT/AU2005/001460 AU2005001460W WO2006032103A1 WO 2006032103 A1 WO2006032103 A1 WO 2006032103A1 AU 2005001460 W AU2005001460 W AU 2005001460W WO 2006032103 A1 WO2006032103 A1 WO 2006032103A1
Authority
WO
WIPO (PCT)
Prior art keywords
identifier
range
values
value falling
value
Prior art date
Application number
PCT/AU2005/001460
Other languages
French (fr)
Inventor
Benjamin Aaron Gittins
Original Assignee
Synaptic Laboratories Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from AU2004905506A external-priority patent/AU2004905506A0/en
Application filed by Synaptic Laboratories Limited filed Critical Synaptic Laboratories Limited
Publication of WO2006032103A1 publication Critical patent/WO2006032103A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation

Definitions

  • the present invention relates to a method of and apparatus for mapping tags which identify resources and is particularly applicable to memory mapping and to resource load balancing.
  • identifiers such as logical addresses randomly into a physical address space.
  • identifiers are generally referred to as 'tags', and throughout this specification (including the claims) we use the terms 'tag' and 'identifier' as being synonymous.
  • the present application teaches methodologies for mapping a set of numerical identifiers of fewer than 2" physical resources, although the numerical identifiers are n bits long. That is, the present invention caters for a situation where, for example, physical hardware does not include all of the physical 2" address locations which could be addressed by n mapped address bits.
  • the number of memory locations in 128Mbytes of physical memory is a number which is represented by base 2 raised to an integral exponent.
  • a combined memory pool of three modules of 128MByte memory contains a number of memory locations which is not representable by base 2 raised to an integral exponent, but as a practical matter an integral number of address bits must be used to address such a pool of memory.
  • the present invention accordingly provides a method of mapping identifiers comprising the steps of: mapping an identifier which has a value falling in a range of m contiguous values and which is represented in n bits, m being less than 2", into an identifier which has a value falling in a range of 2" values, followed by; mapping the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values.
  • the range of m contiguous values is 0 to (m - 1).
  • mapping of the identifier which has a value falling in a range of m contiguous values into the identifier which is in the range of 2" values comprises a step of keyed mixing of the identifier which has a value falling in the range of m contiguous values.
  • the step of keyed mixing of the identifier which has a value falling in the range of m contiguous values with a key comprises applying a key against at least one of (a) the identifier, and (b) the identifier which has been mapped into the range of 2" values.
  • mapping of the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values comprises the steps of: ascertaining a number which must be subtracted from an identifier which has a value falling in the range of 2" values in order to map that identifier into an identifier which has a value falling in the range of m contiguous values; and subtracting the number so ascertained from the identifier which has a value falling in the range of 2".
  • mapping of the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values comprises the steps of: ascertaining a number which must be subtracted from (m - 1) in order to map an identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values; and subtracting the number so ascertained from (m - 1).
  • circuitry which circuitry comprises at least one component which is disabled depending on whether a number is to be subtracted from (m-1) or subtracted from a mapped identifier which has a value falling in the range of 2 n values.
  • the present invention provides a method of mapping an input identifier onto an output identifier comprising the steps of: a first mapping of an input identifier which has a value falling in a range of m contiguous values and which is represented in n bits, m being less than 2", into an identifier which has a value falling in a range of 2" values, followed by; a second mapping of the identifier which has a value falling in the range of 2" values into an output identifier which has a value falling in the range of m contiguous values, in which the first mapping and the second mapping are performed by ascertaining from a look-up table the value in the range of m contiguous values onto which the input identifier is to be mapped in order to map it onto the output identifier; and assigning the value so ascertained to the output identifier.
  • the method further comprises the step of adding an offset to the identifier which has a value falling in the range of m contiguous values, which identifier has been mapped from a value falling in the range of 2" values.
  • the method further comprises the step of subtracting an offset from the identifier which has a value falling in the range of m contiguous values, which identifier has been mapped from a value falling in the range of 2" values.
  • the present invention provides apparatus for mapping identifiers comprising: a mapper for mapping an identifier which has a value falling in a range of m contiguous values and which is represented in n bits, m being less than 2", into an identifier which has a value falling in a range of 2" values; and a mapper for mapping the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values.
  • the range of m contiguous values is 0 to (m - 1).
  • the range of T values is 0 to (2" - 1).
  • the mapper for mapping an identifier which has a value falling in a range of m contiguous values into the identifier which has a value in the range of 2" values includes a keyed mixer.
  • the keyed mixer applies a key against at least one of (a) the identifier, and (b) the identifier which has been mapped into the range of 2" values with a key.
  • the mapper for mapping the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values comprises: a summer which ascertains a number which must be subtracted from an identifier which has a mapped value falling in the range of 2" values in order to map that identifier into an identifier which has a value falling in the range of m contiguous values; and a subtracter for subtracting the number so ascertained from the identifier which has a mapped value falling in the range of 2" values.
  • the summer which ascertains a number which must be subtracted from an identifier which has a value falling in the range of 2" values in order to map that identifier into an identifier which has a value falling in the range of m contiguous values comprises:
  • (2" - 1) mappers each of said (2" - 1) mappers being adapted to receive as an input one of the values 'zero' to (2" - 2) and for mapping said input value into the range of 2" numbers as an output;
  • (2" - 1) comparators each connected to the output of one of the (2" - 1) mappers, for ascertaining whether the number so mapped is greater than m, and outputting the value T when true and '0' when false; an output which is the output of the comparator which has as its input the mapped value of Oh;
  • each summing element having a different number k of inputs varying from 2 to (2" - 1); taking as its inputs the outputs from the number of comparators corresponding to its number of inputs such that an adder which has k inputs takes as its inputs the outputs of the comparators which map the k lowest values from the range of 2" values; and generating as its output the sum of the number of its ' 1 ' inputs.
  • the summer which ascertains a number which must be subtracted from an identifier which has a value falling in the range of 2" values in order to map that identifier into an identifier which has a value falling in the range of m contiguous values further comprises: a multiplexer having:
  • the mapper for mapping the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values comprises: a summer which ascertains a number which must be subtracted from (m - 1) in order to map an identifier which has a mapped value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values; and a subtracter for subtracting the number so ascertained from (m - 1).
  • the summer which ascertains a number which must be subtracted from (m - 1) in order to map that identifier into an identifier which has a value falling in the range of m contiguous values comprises:
  • (2" - 1) mappers each of said (2" - 1) mappers being adapted to receive as an input one of the values 'zero' to (2" -1) and for mapping said input value into the range of 2" numbers as an output;
  • (2" - 1) comparators each connected to the output of one of the (2" - 1) mappers, for ascertaining whether the number so mapped is less than or equal to m, and outputting the value '1' when true and '0' when false; an output which is the output of the comparator which has as its input the mapped value of (2 n -l);
  • each summing element having a different number k of inputs varying from 2 to (2" - 1); taking as its inputs the outputs from the number of comparators corresponding to its number of inputs such that a summing element which has k inputs takes as its inputs the mapped values of the k highest values from the range of m values; and generating as its output the sum of the number of its ' 1 ' inputs.
  • the counter which ascertains a number which must be subtracted from (m - 1) in order to map that identifier into an identifier which has a value falling in the range of m contiguous values further comprises: a multiplexer having:
  • 2" data inputs comprising: the value '0' (zero); and the output of the comparator which has its input the mapped value of the input (2 n -l); and the outputs from each of the (2" - 2) summing elements; and n control inputs comprising the n bits of the identifier which has a mapped value falling in the range of 2" values; and a subtracter for subtracting the output of the multiplexer from (m - 1).
  • the mapper for mapping the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values comprises: a summer which ascertains a number which must be subtracted from an identifier which has a mapped value falling in the range of 2" values in order to map that identifier into an identifier which has a value falling in the range of m contiguous values, together with a subtracter for subtracting the number so ascertained from the identifier which has a mapped value falling in the range of 2" values; and a summer which ascertains a number which must be subtracted from the (m - 1) in order to map an identifier which has a mapped value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values, together with a subtracter for subtracting the number so ascertained from
  • the summer which ascertains a number which must be subtracted from an identifier which has a value falling in the range of 2" values in order to map that identifier into an identifier which has a value falling in the range of m contiguous values comprises: p mappers, each of saidp mappers being adapted to receive as an input one of the values 'zero' to (p - 1) and for mapping said input value into the range of T numbers as an output; p comparators, each connected to the output of one of the p mappers, for ascertaining whether the number so mapped is greater than m, and outputting the value '1' when true and '0' when false; the output which is the output of the comparator which has as its input the mapped value of Oh;
  • each summing element having a different number k of inputs varying from 2 top; taking as its inputs the outputs from the number of comparators corresponding to its number of inputs such that a summing element which has k inputs takes as its inputs the mapped values of the k lowest numbers from the range of T values; and generating as its output the sum of the number of its ' 1 ' inputs; and that: the summer which ascertains a number which must be subtracted from (m -1) in order to map identifier which is in the range of 2" into an identifier which has a value falling in the range of m contiguous values comprises: q mappers, each of said q mappers being adapted to receive as an input one of the values (p + 2) to (2" - 1) and for mapping said input value into the range of 2" numbers as an output; q comparators, each connected to the output of one of the q mappers, for ascertaining whether the number so mapped is less than or
  • the summer which ascertains a number which must be subtracted from an identifier which has a mapped value falling in the range of 2" values in order to map that identifier into an identifier which has a value falling in the range of m contiguous values further comprises: a first multiplexer having:
  • (p + 1) data inputs comprising: the value '0'; and the outputs from each of the (p-1) summing elements; and the output of the comparator which has its input the mapped value of the input Oh; and
  • control inputs comprising the least significant of the n bits of the identifier which has a mapped value falling in the range of 2" values; and a subtracter for subtracting the output of the multiplexer from the identifier which has a mapped value falling in the range of 2" values; and that: the summer which ascertains a number which must be subtracted from (m -1) in order to map that identifier into an identifier which has a value falling in the range of m contiguous values further comprises: a second multiplexer having:
  • (q + 1) data inputs comprising: the output of the comparator which has its input the mapped value of the input (2 n -l); and the outputs from each of the (q-1) summing elements; and the value '0' (zero); and(n - 1) control inputs comprising the least significant of the n bits of the identifier which has a mapped value falling in the range of 2" values; and a subtracter for subtracting the output of the multiplexer from (m ⁇ 1).
  • the apparatus further comprises a third multiplexer which takes as its data inputs the outputs from the first and second multiplexers and which takes as its control input the most significant of the n bits of the identifier which has a mapped value falling in the range of 2" values.
  • the apparatus further comprises circuit-enable logic, which logic takes as its decision input the most significant of the n bits of the identifier which has a mapped value falling in the range of 2" values, and which disables circuitry given that its output was not chosen from the third multiplexer which takes as its data inputs the outputs from the first and second multiplexers.
  • the apparatus further comprises a look-up table which contains each value in the range of m contiguous values onto which the identifiers in the range of 2" values is to be mapped.
  • the apparatus further comprises a key to select from a plurality of look ⁇ up-tables which each contain values in the range of m contiguous values onto which the identifiers in the range of 2" values is to be mapped.
  • the present invention provides apparatus for mapping an input identifier which has a value falling in a range of m contiguous values into an output identifier which has a value falling in a range of m contiguous values, the apparatus comprising a look-up table, the contents of which look-up table have been generated according to a process comprising the steps of: mapping an identifier which has a value falling in a range of m contiguous values and which is represented in n bits, m being less than 2", into an identifier which has a value falling in a range of 2" values, followed by; mapping the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values.
  • the apparatus further comprises an adder which adds an offset to the identifier which has a value falling in the range of m contiguous values, which identifier has been mapped from a value falling in the range of 2" values.
  • the apparatus further comprises a subtracter which subtracts an offset from the identifier which has a value falling in the range of m contiguous values, which identifier has been mapped from a value falling in the range of 2" values.
  • figures 1, 2 and 3 illustrate aspects of the operation of preferred embodiments of the present invention
  • figures 4 and 5 are block schematic diagrams illustrating the operation preferred embodiments of the present invention
  • figures 6 and 7 are block schematic diagrams illustrating the operation of further preferred embodiments of the present invention.
  • the numbers which can be represented by four bits are the numbers which are represented by '0' (zero) to '15' (fifteen) in decimal notation or by 'Oh' to 'Fh' in hexadecimal notation. (These numbers may also equivalently be represented by 'OxO' to 'OxF' in an alternative form of hexadecimal notation.)
  • an n-bit memory address bus is wide enough to address 2" address locations, the physical hardware may not include all of the physical 2" address locations.
  • a microcomputer which has a 4-bit wide address bus would be able to address the sixteen address locations which are identified as Oh to Fh. However the microcomputer may not actually have all sixteen memory locations installed. For the sake of illustration of embodiments of the present invention, it is assumed that the microcomputer has eleven physical address locations installed, numbered Oh to Ah (zero to ten in decimal notation), eleven being a number which cannot be represented by an integral exponent of base 2 as it falls between the values 'eight' (2 3 ) and 'sixteen' (2 4 ).
  • Figure 1 illustrates the mapping of a set of input states 2 (such as memory addresses) through a mapping operation 3 to produce a set of output states 4.
  • a mapping operation 3 to produce a set of output states 4.
  • the full set of hexadecimal numbers Oh to Fh are shown as potential input states 2, the numbers Bh to Fh are struck through to show that the potential input states represented by these latter numbers are not valid as they do not map to any available physical resource..
  • the input state 4h maps to the output Oh
  • the input state Oh maps to the output state 2h
  • the input state 9h maps to the output state 3h
  • the input state 2h maps to the output state 5h
  • the input state 7h maps to the output state 6h
  • the input state 6h maps to the output state 9h
  • the input state 5h maps to the output state Ah
  • the input state Ih maps to the output state Bh
  • the input state 8h maps to the output state Ch
  • the input state Ah maps to the output state Eh
  • the input state 3h maps to the output state Fh.
  • the mapping operation distributes the input across the entire range of the potential output states.
  • the set of possible output states 4 produced by the mapping operation 3 on the full set of sixteen potential input states represented by Oh to Fh is itself the states Oh to Fh.
  • the five input states represented by Bh to Fh are not valid, only eleven out of the sixteen potential output states which could have been utilized in the range Oh to Fh will be valid.
  • the six invalid input states Bh to Fh are represented as if they would map to the output states Ih, Dh, 4h, 8h, and 7h respectively.
  • the valid input states Ih, 8h, Ah and 3h map to the invalid output states Bh, Ch, Eh and Fh respectively.
  • FIG. 2 illustrates a methodology for addressing these issues according to embodiments of the present invention. Again, figure 2 illustrates the mapping of a set of input states 2 through a mapping operation 3 to produce a set of output states 4 as is illustrated in figure 1.
  • a compression operation is then applied as illustrated at 6 in figure 2 to eliminate the wastage of output space which would otherwise result from the mapping of invalid inputs Bh, Ch, Dh, Eh, and Fh into output states Ih, Dh, 4h, 8h and 7h respectively which are illustrated at 7 in figure 2.
  • the output states which are to the right of locations Ih, 4h, 7h, 8h and Dh are moved leftwards (that is, decreased in numerical value) to the extent that is necessary in order to fill those otherwise wasted output states. (These output states are 'wasted' in the sense that they will never be filled with valid data.)
  • the input state Oh shown at 2 in figure 1 maps to the intermediate state 2h shown at
  • the input state Ih shown at 2 in figure 2 maps to the intermediate state Bh and compresses to the output state 7h
  • the input state 2h shown at 2 in figure 2 maps to the intermediate state 5h and compresses to the output state 3h
  • the input state 3h shown at 2 in figure 2 maps to the intermediate state Fh and compresses to the output state Ah
  • the input state 4h shown at 2 in figure 2 maps to the intermediate state Oh and cannot undergo compression
  • the input state 5h shown at 2 in figure 2 maps to the intermediate state Ah and compresses to the output state 6h
  • the input state 6h shown at 2 in figure 2 maps to the intermediate state 9h and compresses to the output state 5h
  • the input state 7h shown at 2 in figure 2 maps to the intermediate state 6h and compresses to the output state 4h
  • the input state 8h shown at 2 in figure 2 maps to the intermediate state Ch and compresses to the output state 8h
  • the input state 9h shown at 2 in figure 2 maps to the intermediate state Ch and compresses to the output state
  • Figure 3 further illustrates the mapping and compressing operations which take place according to embodiments of the present invention.
  • input states are referenced by reference numeral 2
  • mapped states by reference numeral 4 and compressed states by reference numeral 7.
  • the line of arrows which is referenced by the reference numeral 9 in figure 3 represents the number of positions by which a mapped, valid input state 4 needs to be moved 'leftwise' (that is, decreased in numerical value) in order to compress it into the appropriate compressed state.
  • the input state 4h has been mapped to the state Oh and does not undergo compression because the value Oh is the lowest value.
  • An arrow labelled '0' (zero) accordingly appears adjacent the state Oh to indicate that nothing need be subtracted from it in order to convert it into a valid compressed state.
  • FIGS. 4 and 5 illustrate hardware which performs compression according to a presently preferred embodiment of the invention.
  • Reference numeral 10 in figure 4 indicates a four-bit input value which is mapped by the mapping operation 3 to produce the four-bit (mapped) state 11.
  • each of the first fifteen states 0000, 0001, up to 1110 which can be assumed by a four-bit variable are also input to fifteen instances of the mapping function 3 to produce the fifteen mapped values which are indicated by reference numerals 21 to 35 in figure 5.
  • These fifteen mapped values are in turn input into the module 41 which is represented in detail in figure 5.
  • the binary value 1111 is also generated for purposes described below in this specification.
  • the module 41 includes fifteen comparators labelled with reference numerals 57 to 71.
  • Each of comparators 57 to 71 receives, as the input referenced by numeral 501, the value of the highest valid output state (being the number Ah in the presently-described embodiment.)
  • Each such comparator also receives as an input one of the fifteen values which is produced by the mapping of values 0000 to 1110.
  • These fifteen states 0000 to 1110 are referenced by one of reference numerals 21 to 35 in figures 4 and 5. Each such state is compared with the value Ah in the respective comparator (57 to 71).
  • the module 41 further includes fourteen 'summing elements' which are referenced by the numerals 112 to 125 in figure 5, with a number of inputs which varies from two to fifteen. Each 'summing element' sums the number of 'True' (that is, '1') inputs to it.
  • the first summing element 112 has two inputs, one from each of comparators 57 and 58.
  • the second summing element 113 has three inputs, one from each of comparators 57, 58 and 59. The number of inputs to successive summing elements increments in this manner so that the fourteenth summing element, labeled with reference numeral 125, takes fifteen inputs, being one input from the outputs of each of comparators 57 to 71.
  • the output of comparator 57 passes through the module 41 to become an output value from the module 41 which is referenced by reference numeral 42.
  • each of the mapped values of the input states 0000 to 1110 indicated by reference numerals 21 to 36 is accordingly compared, in comparators indicated by reference numerals 57 to 71, against the maximum valid value for the output state.
  • the maximum valid value for the output state is Ah. This results in the value of the output 42 from figure 5 being 'one' when the mapped value of the input 0000 (that is, the value into which the input 0000 is mapped) is greater that Ah, and 'zero' when the mapped value of the input 0000 is greater than Ah.
  • the successive outputs 43 to 56 are each the sum of a number of mapped inputs which are greater than Ah.
  • one of the outputs 43 to 56 equals the sum of the number of input values, less than the given input value under consideration, which map to values which are greater than Ah.
  • the output 42 equals '1' if the input state 0000 maps to an output state which is greater than Ah.
  • Each of the fifteen outputs 42 to 56 from module 41 is input as a data input into multiplexer 131 which is illustrated in figure 4.
  • the sixteenth data input 130 into multiplexer 131 is the hard- wired value 0000.
  • the control inputs into multiplexer 131 are the four data bits of the mapped value which is indicated by reference number 11.
  • the control inputs to the multiplexer 131 are arranged such that control value 0000 sets the output 132 of the multiplexer equal to the input value on line 130 (that is, 0000).
  • control input corresponding to the mapped value 0001 sets the output equal to the input value on line 42; the control input corresponding to the mapped value 0010 sets the output equal to the input value on the line 43; the control input corresponding to the mapped value 0011 sets the output equal to the input value on line 44; the control input corresponding to the mapped value 0100 sets the output equal to the input value on the line 45; the control input corresponding to the mapped value 0101 sets the output equal to the input value on line 46; the control input corresponding to the mapped value 0110 sets the output equal to the input value on the line 47; the control input corresponding to the mapped value 0111 sets the output equal to the input value on line 48; the control input corresponding to the mapped value 1000 sets the output equal to the input value on the line 49; the control input corresponding to the mapped value 1001 sets the output equal to the input value on line 50; the control input corresponding to the mapped value 1010 sets the output equal to the input value on the line 49; the control input corresponding to the mapped
  • the output 132 of the multiplexer 131 is input to the subtracter 133 as the 'minus' input.
  • the mapped value 11 of the input value 10 is input to the subtracter 133 as the 'plus' input.
  • the 'minus' input is subtracted from the 'plus' input to generate the output 134.
  • the output value 134 from the subtracter 133 is thus the 'compressed' value of the mapped input value, as is illustrated by the following example.
  • the input value which is referenced by reference numeral 10 is the digital value 0000, also represented by the hexadecimal value Oh.
  • the input Oh maps to the output value 2h, also represented by 0010 in decimal notation. It is the third comparator 59 which corresponds to the un-mapped value 0010.
  • the output 44 from the module 41 will accordingly have the value Ih, indicating that one position to the left in line 4 of figure 3 will have received a mapped value which is greater than Ah. Accordingly, the value Ih is chosen by the multiplexer 131 and is subtracted from the value 2h in subtracter 134 to correctly compress the value 2h to the value Ih.
  • Figures 6 and 7 illustrate a further preferred embodiment of the invention which is a variation on the embodiments of figures 4 and 5.
  • Reference numeral 10 in figure 6 represents a four-bit input value which is mapped by the mapping operation 3 to produce the four-bit (mapped) state 11.
  • each of the first seven and the last seven states which can be assumed by a four-bit variable are also input to fourteen instances of the mapping function 3 to produce fourteen mapped values.
  • the fourteen states which are mapped are 0000 to 0110 inclusive and 1001 to 1111 inclusive, generating the output states which are indicated by reference numerals 151 to 157 and 160 to 166 respectively figure 6.
  • These fourteen mapped values are in turn input into the module 141 which is represented in detail in figure 7.
  • the binary value 1010 represented as Ah in hexadecimal
  • the module 141 includes fourteen comparators labelled with reference numerals 207 to 213 and 216 to 222.
  • These seven states 0000 to 0110 are referenced by one of reference numerals 151 to 157 in figures 6 and 7.
  • Each such state is compared against the value Ah in the respective comparator (207 to 213).
  • the comparator produces a 'True' output which is coded as the number T.
  • the comparator When the input state to the comparator is equal to or less than the threshold value Ah then the comparator produces a 'False' output which is coded as the number '0'.
  • the second group of seven these comparators the comparators which are referenced by reference numbers 216 to 222, each receives as an input one of the seven values which is produced by the mapping of values 1001 to 1111.
  • These seven states 1001 to 1111 are referenced by one of reference numerals 160 to 166 in figures 6 and 7.
  • Each such state is compared against the value Ah in the respective comparator (216 to 222).
  • the comparator When the input state to the comparator is less than or equal to the threshold value Ah then the comparator produces a 'True' output which is coded as the number T.
  • the comparator When the input state to the comparator is greater than the threshold value Ah then the comparator produces a 'False' output which is coded as the number '0' .
  • the module 141 further includes fourteen 'summing elements' which are referenced by the numerals 43 to 49 and 189 to 195 in figure 7.
  • the first seven of these summing elements (summing elements referenced 43 to 48) has a number of inputs which varies from two to seven.
  • the second seven of these summing elements (summing elements referenced 189 to 195) has a number of inputs which varies from seven to two.
  • Each 'summing element' sums the number of 'True' (that is, '1') inputs to it.
  • the right hand side of the circuit is the mirror-negative of the left hand side. Where the left hand side is concerned with counting wasted numbers left-to-right, the right hand side is concerned with counting valid numbers from right-to-left. Consequently the fixed 0000 input for the left hand side is mirrored on the right hand side. The same occurs for the right most entry of the left hand side not requiring a summing element being mirrored as the left most entry of the right hand side also not requiring a summing element.
  • the three low bits of mapped value 11 are used as control inputs to the multiplexers 251 and 252 providing a selection from 8 inputs for both the left and right hand multiplexer.
  • the singular high bit of mapped value 11 is used to select the result from the left subtracter 256 or the right subtracter 255, resulting in a singular final output.
  • the singular high bit of that mapped value is used to enable the logic corresponding to the left or right subtracters to reduce power usage.
  • the singular high bit of mapped value 11 selects the output of the left subtracter, the logic including and preceding the right subtracter is disabled reducing power consumption from the right summation circuitry and the right multiplexer.
  • the singular high bit of mapped value 11 selects the output of the right subtracter, the logic including and preceding the left subtracter is disabled.
  • Multiplexer 251 and subtracter 256 of figure 6 operate analogously to multiplexer 131 and subtracter 133 of figure 4, but with only 8 inputs not 16.
  • the subtracter 256 of figure 6 is used to correct the offset of the mapped value by subtracting the number of wasted spaces to the left.
  • the subtracter 255 of figure 6 is used to calculate the offset left of the maximum valid number taking into account the number of valid entries to the right.
  • the embodiment of figures 6 and 7 is preferred to embodiment of figures 4 and 5.
  • the embodiment of figures 6 and 7 significantly reduce the number of hardware gates required to implement the summation operations counting the outputs of the true/false flags. Effectively halving the number of inputs to the summation function also cuts the worst- case latency of the summation function in half.
  • the complete circuits illustrated by to figures 4 to 7 calculate the mapping function at each invocation without requiring the manufacture of read-only-memory (ROM) on an integrated chip.
  • ROM read-only-memory
  • the process described could be rendered as an apparatus comprising a look-up-table such that for every combination of the three inputs ⁇ input state, maximum valid state and key state ⁇ a valid mapped output is pre-computed without loss of generalisation.
  • the performance and circuit cost trade off between implementing a dynamically calculated three input mapping or using a large ROM space is dependent on the target hardware architecture. It is generally preferred by the industry to avoid the use of ROM where possible in preference to combinational logic circuits.
  • the look-up table is compressed.
  • a further mapping or randomizing process takes place between the mapping of the memory address and the compression of that mapping of the memory address.
  • Preferred forms of such further randomization include XORing the mapped address with a key value (that key value being represented by the input labelled 502 in the drawings).
  • an offset is added to or subtracted from the identifier m which has been mapped from the range of 2" values. It may, for example, be desired to map a range of m identifiers which runs from zero to (m - 1) into a range of hardware memory addresses which runs from an address which is offset from zero, in which case an offset is added to the mapped output address.

Abstract

An identifier such as a memory address (2) which is represented by n bits, but which is lower in value than (2n - 1) is mapped (3) to any position within the range (4) of 'zero' to (2n - 1). That value is mapped (9) back into the range (7) which is narrower than (2n - 1).

Description

METHOD OF AND APPARATUS FOR MAPPING n-BIT IDENTIFIERS OF
FEWER THAN 2" RESOURCES
Field of the invention The present invention relates to a method of and apparatus for mapping tags which identify resources and is particularly applicable to memory mapping and to resource load balancing.
This application: is related to our Australian provisional application 2004905639 entitled Method of and Apparatus for Mapping Identifiers, our reference P10001AUP4; and claims priority from our Australian provisional application 2004905506 entitled Method of and Apparatus for Mapping n-Bit Identifiers of Fewer than 2" Resources, our reference P 10003 AUPl; the content of each of which is incorporated herein by reference.
Background of the invention
In the field of computer hardware, there are situations in which it is of benefit to map identifiers such as logical addresses randomly into a physical address space. In the field of memory controllers, such identifiers are generally referred to as 'tags', and throughout this specification (including the claims) we use the terms 'tag' and 'identifier' as being synonymous. The present application teaches methodologies for mapping a set of numerical identifiers of fewer than 2" physical resources, although the numerical identifiers are n bits long. That is, the present invention caters for a situation where, for example, physical hardware does not include all of the physical 2" address locations which could be addressed by n mapped address bits. For example, the number of memory locations in 128Mbytes of physical memory is a number which is represented by base 2 raised to an integral exponent. However a combined memory pool of three modules of 128MByte memory contains a number of memory locations which is not representable by base 2 raised to an integral exponent, but as a practical matter an integral number of address bits must be used to address such a pool of memory. Summary of the invention
In one aspect, the present invention accordingly provides a method of mapping identifiers comprising the steps of: mapping an identifier which has a value falling in a range of m contiguous values and which is represented in n bits, m being less than 2", into an identifier which has a value falling in a range of 2" values, followed by; mapping the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values.
It is preferred that the range of m contiguous values is 0 to (m - 1).
It is preferred that the range of 2" values is 0 to (2" - 1).
It is preferred that the mapping of the identifier which has a value falling in a range of m contiguous values into the identifier which is in the range of 2" values comprises a step of keyed mixing of the identifier which has a value falling in the range of m contiguous values.
It is preferred that the step of keyed mixing of the identifier which has a value falling in the range of m contiguous values with a key comprises applying a key against at least one of (a) the identifier, and (b) the identifier which has been mapped into the range of 2" values.
It is preferred that the mapping of the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values comprises the steps of: ascertaining a number which must be subtracted from an identifier which has a value falling in the range of 2" values in order to map that identifier into an identifier which has a value falling in the range of m contiguous values; and subtracting the number so ascertained from the identifier which has a value falling in the range of 2". It is preferred that the mapping of the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values comprises the steps of: ascertaining a number which must be subtracted from (m - 1) in order to map an identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values; and subtracting the number so ascertained from (m - 1).
It is preferred that the method is implemented in circuitry, which circuitry comprises at least one component which is disabled depending on whether a number is to be subtracted from (m-1) or subtracted from a mapped identifier which has a value falling in the range of 2n values.
In another aspect, the present invention provides a method of mapping an input identifier onto an output identifier comprising the steps of: a first mapping of an input identifier which has a value falling in a range of m contiguous values and which is represented in n bits, m being less than 2", into an identifier which has a value falling in a range of 2" values, followed by; a second mapping of the identifier which has a value falling in the range of 2" values into an output identifier which has a value falling in the range of m contiguous values, in which the first mapping and the second mapping are performed by ascertaining from a look-up table the value in the range of m contiguous values onto which the input identifier is to be mapped in order to map it onto the output identifier; and assigning the value so ascertained to the output identifier.
It is preferred that the method further comprises the step of adding an offset to the identifier which has a value falling in the range of m contiguous values, which identifier has been mapped from a value falling in the range of 2" values.
It is preferred that the method further comprises the step of subtracting an offset from the identifier which has a value falling in the range of m contiguous values, which identifier has been mapped from a value falling in the range of 2" values. In another aspect, the present invention provides apparatus for mapping identifiers comprising: a mapper for mapping an identifier which has a value falling in a range of m contiguous values and which is represented in n bits, m being less than 2", into an identifier which has a value falling in a range of 2" values; and a mapper for mapping the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values.
It is preferred that the range of m contiguous values is 0 to (m - 1).
It' is preferred that the range of T values is 0 to (2" - 1).
It is preferred that the mapper for mapping an identifier which has a value falling in a range of m contiguous values into the identifier which has a value in the range of 2" values includes a keyed mixer.
It is preferred that the keyed mixer applies a key against at least one of (a) the identifier, and (b) the identifier which has been mapped into the range of 2" values with a key.
It is preferred that the mapper for mapping the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values comprises: a summer which ascertains a number which must be subtracted from an identifier which has a mapped value falling in the range of 2" values in order to map that identifier into an identifier which has a value falling in the range of m contiguous values; and a subtracter for subtracting the number so ascertained from the identifier which has a mapped value falling in the range of 2" values.
It is preferred that the summer which ascertains a number which must be subtracted from an identifier which has a value falling in the range of 2" values in order to map that identifier into an identifier which has a value falling in the range of m contiguous values comprises:
(2" - 1) mappers, each of said (2" - 1) mappers being adapted to receive as an input one of the values 'zero' to (2" - 2) and for mapping said input value into the range of 2" numbers as an output;
(2" - 1) comparators, each connected to the output of one of the (2" - 1) mappers, for ascertaining whether the number so mapped is greater than m, and outputting the value T when true and '0' when false; an output which is the output of the comparator which has as its input the mapped value of Oh;
(2" - 2) summing elements, each summing element: having a different number k of inputs varying from 2 to (2" - 1); taking as its inputs the outputs from the number of comparators corresponding to its number of inputs such that an adder which has k inputs takes as its inputs the outputs of the comparators which map the k lowest values from the range of 2" values; and generating as its output the sum of the number of its ' 1 ' inputs.
It is preferred that the summer which ascertains a number which must be subtracted from an identifier which has a value falling in the range of 2" values in order to map that identifier into an identifier which has a value falling in the range of m contiguous values further comprises: a multiplexer having:
2" data inputs, each of n bits, comprising: the value '0' (zero); and the outputs from each of the (2" - 2) summing elements; and the output of the comparator which has its input the mapped value of the input Oh; and n control inputs comprising the n bits of the identifier which has a mapped value falling in the range of 2" values; and a subtracter for subtracting the output of the multiplexer from the identifier which has a mapped value falling in the range of 2" values. It is preferred that the mapper for mapping the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values comprises: a summer which ascertains a number which must be subtracted from (m - 1) in order to map an identifier which has a mapped value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values; and a subtracter for subtracting the number so ascertained from (m - 1).
It is preferred that the summer which ascertains a number which must be subtracted from (m - 1) in order to map that identifier into an identifier which has a value falling in the range of m contiguous values comprises:
(2" - 1) mappers, each of said (2" - 1) mappers being adapted to receive as an input one of the values 'zero' to (2" -1) and for mapping said input value into the range of 2" numbers as an output;
(2" - 1) comparators, each connected to the output of one of the (2" - 1) mappers, for ascertaining whether the number so mapped is less than or equal to m, and outputting the value '1' when true and '0' when false; an output which is the output of the comparator which has as its input the mapped value of (2n-l);
(2" - 2) summing elements, each summing element: having a different number k of inputs varying from 2 to (2" - 1); taking as its inputs the outputs from the number of comparators corresponding to its number of inputs such that a summing element which has k inputs takes as its inputs the mapped values of the k highest values from the range of m values; and generating as its output the sum of the number of its ' 1 ' inputs.
It is preferred that the counter which ascertains a number which must be subtracted from (m - 1) in order to map that identifier into an identifier which has a value falling in the range of m contiguous values further comprises: a multiplexer having:
2" data inputs comprising: the value '0' (zero); and the output of the comparator which has its input the mapped value of the input (2n-l); and the outputs from each of the (2" - 2) summing elements; and n control inputs comprising the n bits of the identifier which has a mapped value falling in the range of 2" values; and a subtracter for subtracting the output of the multiplexer from (m - 1).
It is preferred that the mapper for mapping the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values comprises: a summer which ascertains a number which must be subtracted from an identifier which has a mapped value falling in the range of 2" values in order to map that identifier into an identifier which has a value falling in the range of m contiguous values, together with a subtracter for subtracting the number so ascertained from the identifier which has a mapped value falling in the range of 2" values; and a summer which ascertains a number which must be subtracted from the (m - 1) in order to map an identifier which has a mapped value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values, together with a subtracter for subtracting the number so ascertained from
(m - 1).
It is preferred that: the summer which ascertains a number which must be subtracted from an identifier which has a value falling in the range of 2" values in order to map that identifier into an identifier which has a value falling in the range of m contiguous values comprises: p mappers, each of saidp mappers being adapted to receive as an input one of the values 'zero' to (p - 1) and for mapping said input value into the range of T numbers as an output; p comparators, each connected to the output of one of the p mappers, for ascertaining whether the number so mapped is greater than m, and outputting the value '1' when true and '0' when false; the output which is the output of the comparator which has as its input the mapped value of Oh;
(p-1) summing elements, each summing element: having a different number k of inputs varying from 2 top; taking as its inputs the outputs from the number of comparators corresponding to its number of inputs such that a summing element which has k inputs takes as its inputs the mapped values of the k lowest numbers from the range of T values; and generating as its output the sum of the number of its ' 1 ' inputs; and that: the summer which ascertains a number which must be subtracted from (m -1) in order to map identifier which is in the range of 2" into an identifier which has a value falling in the range of m contiguous values comprises: q mappers, each of said q mappers being adapted to receive as an input one of the values (p + 2) to (2" - 1) and for mapping said input value into the range of 2" numbers as an output; q comparators, each connected to the output of one of the q mappers, for ascertaining whether the number so mapped is less than or equal to m, and outputting the value T when true and '0' when false; the output which is the output of the comparator which has as its input the mapped value of (21M); iq-1) summing elements, each summing element: having a different number Z of inputs varying from 2 to q; taking as its inputs the outputs from the number of comparators corresponding to its number of inputs such that a summing element which has Z inputs takes as its inputs the mapped values of the I highest values from the range of 2" values; and generating as its output the sum of the number of its ' 1 ' inputs; and in which (p + q + 2) = 2".
It is preferred that: the summer which ascertains a number which must be subtracted from an identifier which has a mapped value falling in the range of 2" values in order to map that identifier into an identifier which has a value falling in the range of m contiguous values further comprises: a first multiplexer having:
(p + 1) data inputs comprising: the value '0'; and the outputs from each of the (p-1) summing elements; and the output of the comparator which has its input the mapped value of the input Oh; and
(n - 1) control inputs comprising the least significant of the n bits of the identifier which has a mapped value falling in the range of 2" values; and a subtracter for subtracting the output of the multiplexer from the identifier which has a mapped value falling in the range of 2" values; and that: the summer which ascertains a number which must be subtracted from (m -1) in order to map that identifier into an identifier which has a value falling in the range of m contiguous values further comprises: a second multiplexer having:
(q + 1) data inputs comprising: the output of the comparator which has its input the mapped value of the input (2n-l); and the outputs from each of the (q-1) summing elements; and the value '0' (zero); and(n - 1) control inputs comprising the least significant of the n bits of the identifier which has a mapped value falling in the range of 2" values; and a subtracter for subtracting the output of the multiplexer from (m ~ 1).
It is preferred that the apparatus further comprises a third multiplexer which takes as its data inputs the outputs from the first and second multiplexers and which takes as its control input the most significant of the n bits of the identifier which has a mapped value falling in the range of 2" values.
It is preferred that the apparatus further comprises circuit-enable logic, which logic takes as its decision input the most significant of the n bits of the identifier which has a mapped value falling in the range of 2" values, and which disables circuitry given that its output was not chosen from the third multiplexer which takes as its data inputs the outputs from the first and second multiplexers.
It is preferred that the apparatus further comprises a look-up table which contains each value in the range of m contiguous values onto which the identifiers in the range of 2" values is to be mapped.
It is preferred that the apparatus further comprises a key to select from a plurality of look¬ up-tables which each contain values in the range of m contiguous values onto which the identifiers in the range of 2" values is to be mapped.
According to yet further aspects, the present invention provides apparatus for mapping an input identifier which has a value falling in a range of m contiguous values into an output identifier which has a value falling in a range of m contiguous values, the apparatus comprising a look-up table, the contents of which look-up table have been generated according to a process comprising the steps of: mapping an identifier which has a value falling in a range of m contiguous values and which is represented in n bits, m being less than 2", into an identifier which has a value falling in a range of 2" values, followed by; mapping the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values.
It is preferred that the apparatus further comprises an adder which adds an offset to the identifier which has a value falling in the range of m contiguous values, which identifier has been mapped from a value falling in the range of 2" values.
It is preferred that the apparatus further comprises a subtracter which subtracts an offset from the identifier which has a value falling in the range of m contiguous values, which identifier has been mapped from a value falling in the range of 2" values. Brief description of the drawings
Preferred embodiments of the invention are described below with reference to the following drawings in which: figures 1, 2 and 3 illustrate aspects of the operation of preferred embodiments of the present invention; figures 4 and 5 are block schematic diagrams illustrating the operation preferred embodiments of the present invention; and figures 6 and 7 are block schematic diagrams illustrating the operation of further preferred embodiments of the present invention.
Description of preferred embodiments of the invention
Although the present invention is described by reference to embodiments which use address widths of four bits, it will be appreciated that the invention is useable with address widths which are greater than four bits. The numbers which can be represented by four bits are the numbers which are represented by '0' (zero) to '15' (fifteen) in decimal notation or by 'Oh' to 'Fh' in hexadecimal notation. (These numbers may also equivalently be represented by 'OxO' to 'OxF' in an alternative form of hexadecimal notation.)
Although an n-bit memory address bus is wide enough to address 2" address locations, the physical hardware may not include all of the physical 2" address locations. A microcomputer which has a 4-bit wide address bus would be able to address the sixteen address locations which are identified as Oh to Fh. However the microcomputer may not actually have all sixteen memory locations installed. For the sake of illustration of embodiments of the present invention, it is assumed that the microcomputer has eleven physical address locations installed, numbered Oh to Ah (zero to ten in decimal notation), eleven being a number which cannot be represented by an integral exponent of base 2 as it falls between the values 'eight' (23) and 'sixteen' (24).
Figure 1 illustrates the mapping of a set of input states 2 (such as memory addresses) through a mapping operation 3 to produce a set of output states 4. Although the full set of hexadecimal numbers Oh to Fh are shown as potential input states 2, the numbers Bh to Fh are struck through to show that the potential input states represented by these latter numbers are not valid as they do not map to any available physical resource.. As shown at 4 in figure 1, the input state 4h maps to the output Oh, the input state Oh maps to the output state 2h, the input state 9h maps to the output state 3h, the input state 2h maps to the output state 5h, the input state 7h maps to the output state 6h, the input state 6h maps to the output state 9h, the input state 5h maps to the output state Ah, the input state Ih maps to the output state Bh, the input state 8h maps to the output state Ch, the input state Ah maps to the output state Eh and the input state 3h maps to the output state Fh. It will be appreciated that the set of mapping relationships described immediately above has been chosen arbitrarily for the purposes of illustration, and that, for example, the mapping relationships may be changed dynamically from clock cycle to clock cycle. It should also be appreciated that the upper valid memory address Ah has been chosen arbitrarily for the purpose of this description and that this limit may change dynamically (for example, on inserting additional memory into the machine).
The mapping operation distributes the input across the entire range of the potential output states. The set of possible output states 4 produced by the mapping operation 3 on the full set of sixteen potential input states represented by Oh to Fh is itself the states Oh to Fh. However, because the five input states represented by Bh to Fh are not valid, only eleven out of the sixteen potential output states which could have been utilized in the range Oh to Fh will be valid. In the mapping represented in figure 1, the six invalid input states Bh to Fh are represented as if they would map to the output states Ih, Dh, 4h, 8h, and 7h respectively. Conversely, the valid input states Ih, 8h, Ah and 3h map to the invalid output states Bh, Ch, Eh and Fh respectively. One implication of this outcome is that if, for example, the states Bh to Fh represented hardware memory addresses in a system which included only the eleven hardware memory locations Oh to Ah, then some valid logical memory addresses will map to hardware addresses which do not exist. Similarly, the memory hardware could not actually cater for the full eleven-member valid input set because the hardware addresses Ih, 4h, 7h and 8h are reserved by the mapping operation for the receipt of the invalid input addresses Bh, Dh, Fh and Eh respectively. Figure 2 illustrates a methodology for addressing these issues according to embodiments of the present invention. Again, figure 2 illustrates the mapping of a set of input states 2 through a mapping operation 3 to produce a set of output states 4 as is illustrated in figure 1. However, in accordance with embodiments of the present invention, a compression operation is then applied as illustrated at 6 in figure 2 to eliminate the wastage of output space which would otherwise result from the mapping of invalid inputs Bh, Ch, Dh, Eh, and Fh into output states Ih, Dh, 4h, 8h and 7h respectively which are illustrated at 7 in figure 2. As is illustrated in figure 3, the output states which are to the right of locations Ih, 4h, 7h, 8h and Dh are moved leftwards (that is, decreased in numerical value) to the extent that is necessary in order to fill those otherwise wasted output states. (These output states are 'wasted' in the sense that they will never be filled with valid data.)
In this way, for example: the input state Oh shown at 2 in figure 1 maps to the intermediate state 2h shown at
4 in figure 2 and compresses to the output state Ih as shown at 6 in figure 2; the input state Ih shown at 2 in figure 2 maps to the intermediate state Bh and compresses to the output state 7h; the input state 2h shown at 2 in figure 2 maps to the intermediate state 5h and compresses to the output state 3h; the input state 3h shown at 2 in figure 2 maps to the intermediate state Fh and compresses to the output state Ah; the input state 4h shown at 2 in figure 2 maps to the intermediate state Oh and cannot undergo compression; the input state 5h shown at 2 in figure 2 maps to the intermediate state Ah and compresses to the output state 6h; the input state 6h shown at 2 in figure 2 maps to the intermediate state 9h and compresses to the output state 5h; the input state 7h shown at 2 in figure 2 maps to the intermediate state 6h and compresses to the output state 4h; the input state 8h shown at 2 in figure 2 maps to the intermediate state Ch and compresses to the output state 8h; the input state 9h shown at 2 in figure 2 maps to the intermediate state 3h and compresses to the output state 2h; the input state Ah shown at 2 in figure 2 maps to the intermediate state Eh and compresses to the output state 9h; the invalid input state Bh shown at 2 in figure 2 would map to the intermediate state Ih but is eliminated by compression; the invalid input state Ch shown at 2 in figure 2 would map to the intermediate state but is eliminated by compression; the invalid input state Dh shown at 2 in figure 2 would map to the intermediate state 4h but is eliminated by compression; the invalid input state Eh shown at 2 in figure 2 would map to the intermediate state 8h but is eliminated by compression; the invalid input state Fh shown at 2 in figure 2 would map to the intermediate state 7h but is eliminated by compression.
Figure 3 further illustrates the mapping and compressing operations which take place according to embodiments of the present invention. As with figures 1 and 2, input states are referenced by reference numeral 2, mapped states by reference numeral 4 and compressed states by reference numeral 7. The line of arrows which is referenced by the reference numeral 9 in figure 3 represents the number of positions by which a mapped, valid input state 4 needs to be moved 'leftwise' (that is, decreased in numerical value) in order to compress it into the appropriate compressed state. As shown in figure 3, the input state 4h has been mapped to the state Oh and does not undergo compression because the value Oh is the lowest value. An arrow labelled '0' (zero) accordingly appears adjacent the state Oh to indicate that nothing need be subtracted from it in order to convert it into a valid compressed state. No arrow appears adjacent the state Ih. This initially indicates that there is no valid input state which can be mapped into the state Ih. However, an arrow labelled '1' appears adjacent the state 2h. This indicates that the value Ih is to be subtracted from the mapped state 2h in order to compress it into the compressed state Ih. In this fashion, various blanks or arrows appear in line 9 adjacent mapped states to indicate what operations, if any, are to take place in order to convert a mapped state into the compressed states. The last such arrow in line 9 is labelled '5' and is adjacent the mapped state Fh. This indicates that the value 5h is to be subtracted from the mapped state Fh in order to convert it into the compressed state Ah.
Figures 4 and 5 illustrate hardware which performs compression according to a presently preferred embodiment of the invention.
According to the presently described embodiment of the invention, this compression is performed real-time in hardware. Reference numeral 10 in figure 4 indicates a four-bit input value which is mapped by the mapping operation 3 to produce the four-bit (mapped) state 11. As is illustrated by the reference numerals 91 to 105 in figure 4, each of the first fifteen states 0000, 0001, up to 1110 which can be assumed by a four-bit variable are also input to fifteen instances of the mapping function 3 to produce the fifteen mapped values which are indicated by reference numerals 21 to 35 in figure 5. These fifteen mapped values are in turn input into the module 41 which is represented in detail in figure 5. As is also illustrated by reference numeral 106 in figure 4, the binary value 1111 is also generated for purposes described below in this specification.
As is illustrated in figure 5, the module 41 includes fifteen comparators labelled with reference numerals 57 to 71. Each of comparators 57 to 71 receives, as the input referenced by numeral 501, the value of the highest valid output state (being the number Ah in the presently-described embodiment.) Each such comparator also receives as an input one of the fifteen values which is produced by the mapping of values 0000 to 1110. These fifteen states 0000 to 1110 are referenced by one of reference numerals 21 to 35 in figures 4 and 5. Each such state is compared with the value Ah in the respective comparator (57 to 71). (As explained above, it is assumed for the purposes of exemplification that in the present embodiment there are eleven valid hardware memory addresses Oh to Ah, making the address Ah the threshold above which there cannot be a valid memory address.) When the input state to the comparator is greater than the threshold value Ah then the comparator produces a 'True' output which is coded as the number '1'. When the input state to the comparator is equal to or less than the threshold value Ah then the comparator produces a 'False' output which is coded as the number O'.
The module 41 further includes fourteen 'summing elements' which are referenced by the numerals 112 to 125 in figure 5, with a number of inputs which varies from two to fifteen. Each 'summing element' sums the number of 'True' (that is, '1') inputs to it. The first summing element 112 has two inputs, one from each of comparators 57 and 58. The second summing element 113 has three inputs, one from each of comparators 57, 58 and 59. The number of inputs to successive summing elements increments in this manner so that the fourteenth summing element, labeled with reference numeral 125, takes fifteen inputs, being one input from the outputs of each of comparators 57 to 71.
The output of comparator 57 passes through the module 41 to become an output value from the module 41 which is referenced by reference numeral 42. The outputs 43 to 56 from summing elements 112 to 125 which are referred to by the reference numerals 43 to 56 respectively also become outputs from the module 41.
It can be seen that each of the mapped values of the input states 0000 to 1110 indicated by reference numerals 21 to 36 is accordingly compared, in comparators indicated by reference numerals 57 to 71, against the maximum valid value for the output state. In the presently described example of hardware having eleven valid addresses, the maximum valid value for the output state is Ah. This results in the value of the output 42 from figure 5 being 'one' when the mapped value of the input 0000 (that is, the value into which the input 0000 is mapped) is greater that Ah, and 'zero' when the mapped value of the input 0000 is greater than Ah. The successive outputs 43 to 56 are each the sum of a number of mapped inputs which are greater than Ah. That is, for a given input value, one of the outputs 43 to 56 equals the sum of the number of input values, less than the given input value under consideration, which map to values which are greater than Ah. The output 42 equals '1' if the input state 0000 maps to an output state which is greater than Ah.
Each of the fifteen outputs 42 to 56 from module 41 is input as a data input into multiplexer 131 which is illustrated in figure 4. The sixteenth data input 130 into multiplexer 131 is the hard- wired value 0000. The control inputs into multiplexer 131 are the four data bits of the mapped value which is indicated by reference number 11. The control inputs to the multiplexer 131 are arranged such that control value 0000 sets the output 132 of the multiplexer equal to the input value on line 130 (that is, 0000). The other possible values of the control inputs operate such that: the control input corresponding to the mapped value 0001 sets the output equal to the input value on line 42; the control input corresponding to the mapped value 0010 sets the output equal to the input value on the line 43; the control input corresponding to the mapped value 0011 sets the output equal to the input value on line 44; the control input corresponding to the mapped value 0100 sets the output equal to the input value on the line 45; the control input corresponding to the mapped value 0101 sets the output equal to the input value on line 46; the control input corresponding to the mapped value 0110 sets the output equal to the input value on the line 47; the control input corresponding to the mapped value 0111 sets the output equal to the input value on line 48; the control input corresponding to the mapped value 1000 sets the output equal to the input value on the line 49; the control input corresponding to the mapped value 1001 sets the output equal to the input value on line 50; the control input corresponding to the mapped value 1010 sets the output equal to the input value on the line 51 ; the control input corresponding to the mapped value 1011 sets the output equal to the input value on line 52; the control input corresponding to the mapped value 1100 sets the output equal to the input value on the line 53; the control input corresponding to the mapped value 1101 sets the output equal to the input value on line 54; the control input corresponding to the mapped value 1110 sets the output equal to the input value on the line 55; the control input corresponding to the mapped value 1111 sets the output equal to the input value on line 56;
The output 132 of the multiplexer 131 is input to the subtracter 133 as the 'minus' input. The mapped value 11 of the input value 10 is input to the subtracter 133 as the 'plus' input. The 'minus' input is subtracted from the 'plus' input to generate the output 134. The output value 134 from the subtracter 133 is thus the 'compressed' value of the mapped input value, as is illustrated by the following example. Consider the example where the input value which is referenced by reference numeral 10 is the digital value 0000, also represented by the hexadecimal value Oh. The input Oh maps to the output value 2h, also represented by 0010 in decimal notation. It is the third comparator 59 which corresponds to the un-mapped value 0010. The output 44 from the module 41 will accordingly have the value Ih, indicating that one position to the left in line 4 of figure 3 will have received a mapped value which is greater than Ah. Accordingly, the value Ih is chosen by the multiplexer 131 and is subtracted from the value 2h in subtracter 134 to correctly compress the value 2h to the value Ih.
Figures 6 and 7 illustrate a further preferred embodiment of the invention which is a variation on the embodiments of figures 4 and 5.
Reference numeral 10 in figure 6 represents a four-bit input value which is mapped by the mapping operation 3 to produce the four-bit (mapped) state 11. As is illustrated by the reference numerals 91 to 97 and 100 to 106 in figure 6, each of the first seven and the last seven states which can be assumed by a four-bit variable are also input to fourteen instances of the mapping function 3 to produce fourteen mapped values. The fourteen states which are mapped are 0000 to 0110 inclusive and 1001 to 1111 inclusive, generating the output states which are indicated by reference numerals 151 to 157 and 160 to 166 respectively figure 6. These fourteen mapped values are in turn input into the module 141 which is represented in detail in figure 7. As is also illustrated by reference numeral 502 in figure 6, the binary value 1010 (represented as Ah in hexadecimal) is also generated for purposes described below in this specification.
As is illustrated in figure 7, the module 141 includes fourteen comparators labelled with reference numerals 207 to 213 and 216 to 222. The first seven of these comparators, the comparators which are referenced by reference numbers 207 to 213, each receives as an input one of the seven values which is produced by the mapping of values 0000 to 0110. These seven states 0000 to 0110 are referenced by one of reference numerals 151 to 157 in figures 6 and 7. Each such state is compared against the value Ah in the respective comparator (207 to 213). As with the previously described embodiment of figures 4 and 5, when the input state to the comparator is greater than the threshold value Ah then the comparator produces a 'True' output which is coded as the number T. When the input state to the comparator is equal to or less than the threshold value Ah then the comparator produces a 'False' output which is coded as the number '0'. The second group of seven these comparators, the comparators which are referenced by reference numbers 216 to 222, each receives as an input one of the seven values which is produced by the mapping of values 1001 to 1111. These seven states 1001 to 1111 are referenced by one of reference numerals 160 to 166 in figures 6 and 7. Each such state is compared against the value Ah in the respective comparator (216 to 222). Unlike the previously described embodiment of figures 4 and 5, when the input state to the comparator is less than or equal to the threshold value Ah then the comparator produces a 'True' output which is coded as the number T. When the input state to the comparator is greater than the threshold value Ah then the comparator produces a 'False' output which is coded as the number '0' .
The module 141 further includes fourteen 'summing elements' which are referenced by the numerals 43 to 49 and 189 to 195 in figure 7. The first seven of these summing elements (summing elements referenced 43 to 48) has a number of inputs which varies from two to seven. The second seven of these summing elements (summing elements referenced 189 to 195) has a number of inputs which varies from seven to two. Each 'summing element' sums the number of 'True' (that is, '1') inputs to it.
It can thus be seen that the left-hand sides of figures 6 and 7 operate analogously to the left-hand side of figures 4 and 5. In contrast, the right hand sides of figures 6 and 7 generate numbers which must be subtracted from the largest valid number referenced by reference numeral 502 (in the presently described embodiment, having the value Ah) in order to correctly compress the mapped value.
The right hand side of the circuit is the mirror-negative of the left hand side. Where the left hand side is concerned with counting wasted numbers left-to-right, the right hand side is concerned with counting valid numbers from right-to-left. Consequently the fixed 0000 input for the left hand side is mirrored on the right hand side. The same occurs for the right most entry of the left hand side not requiring a summing element being mirrored as the left most entry of the right hand side also not requiring a summing element. The three low bits of mapped value 11 are used as control inputs to the multiplexers 251 and 252 providing a selection from 8 inputs for both the left and right hand multiplexer. The singular high bit of mapped value 11 is used to select the result from the left subtracter 256 or the right subtracter 255, resulting in a singular final output.
In further preferred embodiments of the invention, after the mapped value 11 has been calculated, the singular high bit of that mapped value is used to enable the logic corresponding to the left or right subtracters to reduce power usage. In this manner if the singular high bit of mapped value 11 selects the output of the left subtracter, the logic including and preceding the right subtracter is disabled reducing power consumption from the right summation circuitry and the right multiplexer. Conversely, if the singular high bit of mapped value 11 selects the output of the right subtracter, the logic including and preceding the left subtracter is disabled.
Multiplexer 251 and subtracter 256 of figure 6 operate analogously to multiplexer 131 and subtracter 133 of figure 4, but with only 8 inputs not 16. The subtracter 256 of figure 6 is used to correct the offset of the mapped value by subtracting the number of wasted spaces to the left. The subtracter 255 of figure 6 is used to calculate the offset left of the maximum valid number taking into account the number of valid entries to the right.
The embodiment of figures 6 and 7 is preferred to embodiment of figures 4 and 5. The embodiment of figures 6 and 7 significantly reduce the number of hardware gates required to implement the summation operations counting the outputs of the true/false flags. Effectively halving the number of inputs to the summation function also cuts the worst- case latency of the summation function in half.
The complete circuits illustrated by to figures 4 to 7 calculate the mapping function at each invocation without requiring the manufacture of read-only-memory (ROM) on an integrated chip. The process described could be rendered as an apparatus comprising a look-up-table such that for every combination of the three inputs {input state, maximum valid state and key state} a valid mapped output is pre-computed without loss of generalisation. The performance and circuit cost trade off between implementing a dynamically calculated three input mapping or using a large ROM space is dependent on the target hardware architecture. It is generally preferred by the industry to avoid the use of ROM where possible in preference to combinational logic circuits. In alternative preferred embodiments, the look-up table is compressed.
According to yet further preferred embodiments of the invention, a further mapping or randomizing process takes place between the mapping of the memory address and the compression of that mapping of the memory address. Preferred forms of such further randomization include XORing the mapped address with a key value (that key value being represented by the input labelled 502 in the drawings).
According to yet further preferred embodiments of the invention, an offset is added to or subtracted from the identifier m which has been mapped from the range of 2" values. It may, for example, be desired to map a range of m identifiers which runs from zero to (m - 1) into a range of hardware memory addresses which runs from an address which is offset from zero, in which case an offset is added to the mapped output address.
'Comprises/comprising' when used in this specification is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.

Claims

Claims
1. A method of mapping identifiers comprising the steps of: mapping an identifier which has a value falling in a range of m contiguous values and which is represented in n bits, m being less than 2", into an identifier which has a value falling in a range of T values, followed by; mapping the identifier which has a value falling in the range of 2n values into an identifier which has a value falling in the range of rø contiguous values.
2. A method of mapping identifiers as claimed in claim 1 in which the range of m contiguous values is 0 to (m - 1).
3. A method of mapping identifiers as claimed in claim 1 or claim 2 in which the range of 2" values is 0 to (2" - 1).
4. A method of mapping identifiers as claimed in any one of the preceding claims in which the mapping of the identifier which has a value falling in a range of m contiguous values into the identifier which is in the range of 2" values comprises a step of keyed mixing of the identifier which has a value falling in the range of m contiguous values.
5. A method of mapping identifiers as claimed in claim 4 in which the step of keyed mixing of the identifier which has a value falling in the range of m contiguous values with a key comprises applying a key against at least one of (a) the identifier, and (b) the identifier which has been mapped into the range of 2" values.
6. A method of mapping identifiers as claimed in any one of the preceding claims in which the mapping of the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values comprises the steps of: ascertaining a number which must be subtracted from an identifier which has a value falling in the range of 2" values in order to map that identifier into an identifier which has a value falling in the range of m contiguous values; and subtracting the number so ascertained from the identifier which has a value falling in the range of 2".
7. A method of mapping identifiers as claimed in any one of claims 1 to 6 in which the mapping of the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values comprises the steps of: ascertaining a number which must be subtracted from (m - 1) in order to map an identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values; and subtracting the number so ascertained from (m - 1).
8. A method of mapping identifiers as claimed in claim 7, the method being implemented in circuitry, which circuitry comprises at least one component which is disabled depending on whether a number is to be subtracted from (m-1) or subtracted from a mapped identifier which has a value falling in the range of 2n values.
9. A method of mapping an input identifier onto an output identifier comprising the steps of: a first mapping of an input identifier which has a value falling in a range of m contiguous values and which is represented in n bits, m being less than 2n, into an identifier which has a value falling in a range of 2" values, followed by; a second mapping of the identifier which has a value falling in the range of 2" values into an output identifier which has a value falling in the range of m contiguous values, in which the first mapping and the second mapping are performed by ascertaining from a look-up table the value in the range of m contiguous values onto which the input identifier is to be mapped in order to map it onto the output identifier; and assigning the value so ascertained to the output identifier.
10. The method of mapping identifiers as claimed in any one of claims 1 to 9, further comprising the step of adding an offset to the identifier which has a value falling in the range of m contiguous values, which identifier has been mapped from a value falling in the range of 2" values.
11. The method of mapping identifiers as claimed in any one of claims 1 to 9, further comprising the step of subtracting an offset from the identifier which has a value falling in the range of m contiguous values, which identifier has been mapped from a value falling in the range of 2" values.
12. Apparatus for mapping identifiers comprising: a mapper for mapping an identifier which has a value falling in a range of m contiguous values and which is represented in n bits, m being less than 2", into an identifier which has a value falling in a range of 2" values; and a mapper for mapping the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values.
13. Apparatus for mapping identifiers as claimed in claim 12 in which the range of m contiguous values is 0 to (m - 1).
14. Apparatus for mapping identifiers as claimed in claim 12 or claim 13 in which the range of 2" values is 0 to (2" - 1).
15. Apparatus for mapping identifiers as claimed in any one of claims 12 to 14 in which the mapper for mapping an identifier which has a value falling in a range of m contiguous values into the identifier which has a value in the range of 2" values includes a keyed mixer.
16. Apparatus for mapping identifiers as claimed in claim 15 in which the keyed mixer applies a key against at least one of (a) the identifier, and (b) the identifier which has been mapped into the range of 2" values with a key.
17. Apparatus for mapping identifiers as claimed in any one of claims 12 to 16 in which the mapper for mapping the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values comprises: a summer which ascertains a number which must be subtracted from an identifier which has a mapped value falling in the range of 2" values in order to map that identifier into an identifier which has a value falling in the range of m contiguous values; and a subtracter for subtracting the number so ascertained from the identifier which has a mapped value falling in the range of 2" values.
18. Apparatus for mapping identifiers as claimed in claim 17 in which the summer which ascertains a number which must be subtracted from an identifier which has a value falling in the range of 2" values in order to map that identifier into an identifier which has a value falling in the range of m contiguous values comprises:
(2" - 1) mappers, each of said (2" - 1) mappers being adapted to receive as an input one of the values 'zero' to (2" - 2) and for mapping said input value into the range of 2" numbers as an output;
(2" - 1) comparators, each connected to the output of one of the (2" - 1) mappers, for ascertaining whether the number so mapped is greater than m, and outputting the value '1' when true and '0' when false; an output which is the output of the comparator which has as its input the mapped value of Oh;
(2" - 2) summing elements, each summing element: having a different number k of inputs varying from 2 to (2" - 1); taking as its inputs the outputs from the number of comparators corresponding to its number of inputs such that an adder which has k inputs takes as its inputs the outputs of the comparators which map the k lowest values from the range of 2" values; and generating as its output the sum of the number of its T inputs.
19. Apparatus for mapping identifiers as claimed in claim 18 in which the summer which ascertains a number which must be subtracted from an identifier which has a value falling in the range of 2" values in order to map that identifier into an identifier which has a value falling in the range of m contiguous values further comprises: a multiplexer having:
2" data inputs, each of n bits, comprising: the value '0' (zero); and the outputs from each of the (2" - 2) summing elements; and the output of the comparator which has its input the mapped value of the input Oh; and n control inputs comprising the n bits of the identifier which has a mapped value falling in the range of 2" values; and a subtracter for subtracting the output of the multiplexer from the identifier which has a mapped value falling in the range of 2" values.
20. Apparatus for mapping identifiers as claimed in any one of claims 12 to 16 in which the mapper for mapping the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values comprises: a summer which ascertains a number which must be subtracted from (m - 1) in order to map an identifier which has a mapped value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values; and a subtracter for subtracting the number so ascertained from (m - 1).
21. Apparatus for mapping identifiers as claimed in claim 20 in which the summer which ascertains a number which must be subtracted from (m - 1) in order to map that identifier into an identifier which has a value falling in the range of m contiguous values comprises:
(2" - 1) mappers, each of said (2" - 1) mappers being adapted to receive as an input one of the values 'zero' to (2" -1) and for mapping said input value into the range of 2" numbers as an output;
(2" - 1) comparators, each connected to the output of one of the (2" - 1) mappers, for ascertaining whether the number so mapped is less than or equal to m, and outputting the value ' 1 ' when true and '0' when false; an output which is the output of the comparator which has as its input the mapped value of (2n-l);
(2" - 2) summing elements, each summing element: having a different number k of inputs varying from 2 to (2" - 1); taking as its inputs the outputs from the number of comparators corresponding to its number of inputs such that a summing element which has k inputs takes as its inputs the mapped values of the k highest values from the range of m values; and generating as its output the sum of the number of its ' V inputs.
22. Apparatus for mapping identifiers as claimed in claim 21 in which the counter which ascertains a number which must be subtracted from (m - 1) in order to map that identifier into an identifier which has a value falling in the range of Vn contiguous values further comprises: a multiplexer having :
2" data inputs comprising: the value '0' (zero); and the output of the comparator which has its input the mapped value of the input (2n-l); and the outputs from each of the (2" - 2) summing elements; and n control inputs comprising the n bits of the identifier which has a mapped value falling in the range of 2" values; and a subtracter for subtracting the output of the multiplexer from (m - 1).
23 Apparatus for mapping identifiers as claimed in any one of claims 12 to 16 in which the mapper for mapping the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values comprises: a summer which ascertains a number which must be subtracted from an identifier which has a mapped value falling in the range of 2" values in order to map that identifier into an identifier which has a value falling in the range of m contiguous values, together with a subtracter for subtracting the number so ascertained from the identifier which has a mapped value falling in the range of T values; and a summer which ascertains a number which must be subtracted from the (m - 1) in order to map an identifier which has a mapped value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values, together with a subtracter for subtracting the number so ascertained from (m - 1).
Apparatus for mapping identifiers as claimed in claim 23 in which: the summer which ascertains a number which must be subtracted from an identifier which has a value falling in the range of 2" values in order to map that identifier into an identifier which has a value falling in the range of m contiguous values comprises: p mappers, each of saidp mappers being adapted to receive as an input one of the values 'zero' to (p - 1) and for mapping said input value into the range of 2" numbers as an output; p comparators, each connected to the output of one of the p mappers, for ascertaining whether the number so mapped is greater than m, and outputting the value T when true and '0' when false; the output which is the output of the comparator which has as its input the mapped value of Oh; (p-1) summing elements, each summing element: having a different number k of inputs varying from 2 to p; taking as its inputs the outputs from the number of comparators corresponding to its number of inputs such that a summing element which has k inputs takes as its inputs the mapped values of the k lowest numbers from the range of 2" values; and generating as its output the sum of the number of its '1' inputs; the summer which ascertains a number which must be subtracted from (m -1) in order to map identifier which is in the range of 2" into an identifier which has a value falling in the range of m contiguous values comprises: q mappers, each of said q mappers being adapted to receive as an input one of the values (p + 2) to (2" - 1) and for mapping said input value into the range of 2" numbers as an output; q comparators, each connected to the output of one of the q mappers, for ascertaining whether the number so mapped is less than or equal to m, and outputting the value T when true and '0' when false; the output which is the output of the comparator which has as its input the mapped value of (2n-l);
(q-1) summing elements, each summing element: having a different number Z of inputs varying from 2 to q\ taking as its inputs the outputs from the number of comparators corresponding to its number of inputs such that a summing element which has Z inputs takes as its inputs the mapped values of the I highest values from the range of 2" values; and generating as its output the sum of the number of its ' 1 ' inputs; and in which (p + q + 2) = 2".
25. Apparatus for mapping identifiers as claimed in claim 24 in which: the summer which ascertains a number which must be subtracted from an identifier which has a mapped value falling in the range of 2" values in order to map that identifier into an identifier which has a value falling in the range of m contiguous values further comprises: a first multiplexer having: (p + 1) data inputs comprising: the value '0' ; and the outputs from each of the (p-1) summing elements; and the output of the comparator which has its input the mapped value of the input Oh; and (n - 1) control inputs comprising the least significant of the n bits of the identifier which has a mapped value falling in the range of 2" values; and a subtracter for subtracting the output of the multiplexer from the identifier which has a mapped value falling in the range of 2" values; and in which: the summer which ascertains a number which must be subtracted from (m -1) in order to map that identifier into an identifier which has a value falling in the range of m contiguous values further comprises: a second multiplexer having: (q + 1) data inputs comprising: the output of the comparator which has its input the mapped value of the input (2n-l); and the outputs from each of the (q-1) summing elements; and the value '0' (zero); and
(n - 1) control inputs comprising the least significant of the n bits of the identifier which has a mapped value falling in the range of 2" values; and a subtracter for subtracting the output of the multiplexer from (m - 1).
26. Apparatus for mapping identifiers as claimed in claim 25 further comprising a third multiplexer which takes as its data inputs the outputs from the first and second multiplexers and which takes as its control input the most significant of the n bits of the identifier which has a mapped value falling in the range of 2" values.
27. Apparatus for mapping identifiers as claimed in 12 to 26, further comprising circuit-enable logic, which logic takes as its decision input the most significant of the n bits of the identifier which has a mapped value falling in the range of 2" values, and which disables circuitry given that its output was not chosen from the third multiplexer which takes as its data inputs the outputs from the first and second multiplexers.
28. Apparatus for mapping identifiers as claimed in any one of claims 12 to 16, further comprising a look-up table which contains each value in the range of m contiguous values onto which the identifiers in the range of 2" values is to be mapped.
29. Apparatus for mapping identifiers as claimed in claim 28, further comprising a key to select from a plurality of look-up-tables which each contain values in the range of m contiguous values onto which the identifiers in the range of 2" values is to be mapped.
30. Apparatus for mapping an input identifier which has a value falling in a range of m contiguous values into an output identifier which has a value falling in a range of m contiguous values, the apparatus comprising a look-up table, the contents of which look¬ up table have been generated according to a process comprising the steps of: mapping an identifier which has a value falling in a range of m contiguous values and which is represented in n bits, m being less than 2", into an identifier which has a value falling in a range of 2" values, followed by; mapping the identifier which has a value falling in the range of 2" values into an identifier which has a value falling in the range of m contiguous values.
31. The apparatus for mapping identifiers as claimed in any one of claims 12 to 30, further comprising an adder which adds an offset to the identifier which has a value falling in the range of m contiguous values, which identifier has been mapped from a value falling in the range of 2" values.
32. The apparatus for mapping identifiers as claimed in any one of claims 12 to 31, further comprising a subtracter which subtracts an offset from the identifier which has a value falling in the range of m contiguous values, which identifier has been mapped from a value falling in the range of 2" values.
PCT/AU2005/001460 2004-09-24 2005-09-23 METHOD OF AND APPARATUS FOR MAPPING n-BIT IDENTIFIERS OF FEWER THAN 2n RESOURCES WO2006032103A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
AU2004905506 2004-09-24
AU2004905506A AU2004905506A0 (en) 2004-09-24 Method of and apparatus for mapping n-bit identifiers of fewer than 2n resources

Related Child Applications (1)

Application Number Title Priority Date Filing Date
AU2007100161A Division AU2007100161A5 (en) 2004-09-24 2007-03-01 Method of and apparatus for mapping n-bit identifiers of fewer than 2n resources

Publications (1)

Publication Number Publication Date
WO2006032103A1 true WO2006032103A1 (en) 2006-03-30

Family

ID=36089785

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/AU2005/001460 WO2006032103A1 (en) 2004-09-24 2005-09-23 METHOD OF AND APPARATUS FOR MAPPING n-BIT IDENTIFIERS OF FEWER THAN 2n RESOURCES

Country Status (1)

Country Link
WO (1) WO2006032103A1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5784707A (en) * 1994-01-12 1998-07-21 Sun Microsystems, Inc. Method and apparatus for managing virtual computer memory with multiple page sizes
US5897662A (en) * 1995-08-18 1999-04-27 International Business Machines Corporation Pseudo-random address generation mechanism that reduces address translation time
US6381668B1 (en) * 1997-03-21 2002-04-30 International Business Machines Corporation Address mapping for system memory
US6629219B1 (en) * 2000-03-31 2003-09-30 Intel Corporation Method and apparatus for providing highly programmable memory mapping and improved interleaving

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5784707A (en) * 1994-01-12 1998-07-21 Sun Microsystems, Inc. Method and apparatus for managing virtual computer memory with multiple page sizes
US5897662A (en) * 1995-08-18 1999-04-27 International Business Machines Corporation Pseudo-random address generation mechanism that reduces address translation time
US6381668B1 (en) * 1997-03-21 2002-04-30 International Business Machines Corporation Address mapping for system memory
US6629219B1 (en) * 2000-03-31 2003-09-30 Intel Corporation Method and apparatus for providing highly programmable memory mapping and improved interleaving

Similar Documents

Publication Publication Date Title
JPH05113930A (en) Flexible n-way-memory interleaving method
CN110673823B (en) Multiplier, data processing method and chip
CN110554854A (en) Data processor, method, chip and electronic equipment
US20070180015A1 (en) High speed low power fixed-point multiplier and method thereof
CN111258633B (en) Multiplier, data processing method, chip and electronic equipment
CN111258544B (en) Multiplier, data processing method, chip and electronic equipment
CN101489129A (en) Integrated circuit and method for implementing high speed two-dimension discrete cosine transform
WO2006032103A1 (en) METHOD OF AND APPARATUS FOR MAPPING n-BIT IDENTIFIERS OF FEWER THAN 2n RESOURCES
CN111258541B (en) Multiplier, data processing method, chip and electronic equipment
AU2007100161A5 (en) Method of and apparatus for mapping n-bit identifiers of fewer than 2n resources
CN112955878B (en) Apparatus for implementing activation logic of neural network and method thereof
CN210006029U (en) Data processor
CN113031912A (en) Multiplier, data processing method, device and chip
CN210006031U (en) Multiplier and method for generating a digital signal
US7664809B2 (en) Method and device for calculating modulo operations
CN111258545B (en) Multiplier, data processing method, chip and electronic equipment
CN110688087B (en) Data processor, method, chip and electronic equipment
CN105930521A (en) Database management device and method
CN210006084U (en) Multiplier and method for generating a digital signal
CN210006083U (en) Multiplier, device, chip and electronic equipment
CN210006032U (en) Multiplier, machine learning arithmetic device and combination processing device
JPWO2005013105A1 (en) Look-up table and data acquisition method
CN113031915A (en) Multiplier, data processing method, device and chip
CN210006082U (en) Multiplier, device, neural network chip and electronic equipment
CN209879492U (en) Multiplier, machine learning arithmetic device and combination processing device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KP KR KZ LC LK LR LS LT LU LV LY MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU LV MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 05787077

Country of ref document: EP

Kind code of ref document: A1