AU2001232836A1 - Multiple ground signal path ldmos power package - Google Patents

Multiple ground signal path ldmos power package

Info

Publication number
AU2001232836A1
AU2001232836A1 AU2001232836A AU3283601A AU2001232836A1 AU 2001232836 A1 AU2001232836 A1 AU 2001232836A1 AU 2001232836 A AU2001232836 A AU 2001232836A AU 3283601 A AU3283601 A AU 3283601A AU 2001232836 A1 AU2001232836 A1 AU 2001232836A1
Authority
AU
Australia
Prior art keywords
signal path
ground signal
multiple ground
power package
ldmos power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001232836A
Inventor
Bengt Ahl
Henrik Hoyer
Larry Leighton
Thomas Moller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ericsson Inc
Original Assignee
Ericsson Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Inc filed Critical Ericsson Inc
Publication of AU2001232836A1 publication Critical patent/AU2001232836A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6644—Packaging aspects of high-frequency amplifiers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/01014—Silicon [Si]
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    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
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    • H01L2924/30—Technical effects
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    • H01L2924/30107—Inductance
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H01L2924/30111—Impedance matching
AU2001232836A 2000-01-28 2001-01-16 Multiple ground signal path ldmos power package Abandoned AU2001232836A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US49329800A 2000-01-28 2000-01-28
US09493298 2000-01-28
PCT/US2001/001572 WO2001056083A2 (en) 2000-01-28 2001-01-16 Ldmos power package with a plurality of ground signal paths

Publications (1)

Publication Number Publication Date
AU2001232836A1 true AU2001232836A1 (en) 2001-08-07

Family

ID=23959656

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001232836A Abandoned AU2001232836A1 (en) 2000-01-28 2001-01-16 Multiple ground signal path ldmos power package

Country Status (5)

Country Link
US (1) US6777791B2 (en)
EP (1) EP1250717A2 (en)
JP (1) JP2003521127A (en)
AU (1) AU2001232836A1 (en)
WO (1) WO2001056083A2 (en)

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US6614308B2 (en) * 2001-10-22 2003-09-02 Infineon Technologies Ag Multi-stage, high frequency, high power signal amplifier
DE102005008600B9 (en) * 2005-02-23 2012-06-21 Infineon Technologies Ag Chip carrier, chip carrier system and semiconductor chips, and method of making a chip carrier and system
US7564303B2 (en) * 2005-07-26 2009-07-21 Infineon Technologies Ag Semiconductor power device and RF signal amplifier
US7372334B2 (en) * 2005-07-26 2008-05-13 Infineon Technologies Ag Output match transistor
US7262974B2 (en) * 2005-10-28 2007-08-28 Cisco Technology, Inc. Techniques for alleviating the need for DC blocking capacitors in high-speed differential signal pairs
US8357942B2 (en) 2006-10-02 2013-01-22 Kabushiki Kaisha Toshiba Semiconductor device with a peripheral circuit formed therein
US7532073B2 (en) * 2007-09-12 2009-05-12 Viasat, Inc. Solid state power amplifier with multi-planar MMIC modules
EP2485253B1 (en) 2009-09-29 2019-12-18 Kyocera Corporation Device housing package
US8865525B2 (en) * 2010-11-22 2014-10-21 Bridge Semiconductor Corporation Method of making cavity substrate with built-in stiffener and cavity substrate manufactured thereby
US9093461B2 (en) 2011-05-17 2015-07-28 Telefonaktiebolaget L M Ericsson (Publ) Tie bar resonance suppression
US8963313B2 (en) * 2011-12-22 2015-02-24 Raytheon Company Heterogeneous chip integration with low loss interconnection through adaptive patterning
EP2879174B1 (en) * 2013-11-29 2021-09-08 Ampleon Netherlands B.V. Packaged RF power transistor device having next to each other ground leads and a video lead for connecting decoupling capacitors, RF power amplifier
WO2015116128A1 (en) * 2014-01-31 2015-08-06 Hewlett-Packard Development Company, L.P. Signal return path
US10468399B2 (en) 2015-03-31 2019-11-05 Cree, Inc. Multi-cavity package having single metal flange
KR102129556B1 (en) * 2018-11-29 2020-07-02 주식회사 웨이브피아 Method for manufacturing power amplifier package for incorporating input circuit and output circuit
US10784183B2 (en) * 2018-11-30 2020-09-22 Infineon Technologies Ag Semiconductor module with package extension frames

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US3784883A (en) * 1971-07-19 1974-01-08 Communications Transistor Corp Transistor package
US3982271A (en) * 1975-02-07 1976-09-21 Rca Corporation Heat spreader and low parasitic transistor mounting
US3958195A (en) * 1975-03-21 1976-05-18 Varian Associates R.f. transistor package having an isolated common lead
JPS61104673A (en) * 1984-10-27 1986-05-22 Mitsubishi Electric Corp Fet device for ultrahigh frequency
JPH04277665A (en) * 1991-03-06 1992-10-02 Nec Corp Socket of semiconductor ic device
US5889319A (en) * 1996-07-19 1999-03-30 Ericsson, Inc. RF power package with a dual ground
US6064113A (en) * 1998-01-13 2000-05-16 Lsi Logic Corporation Semiconductor device package including a substrate having bonding fingers within an electrically conductive ring surrounding a die area and a combined power and ground plane to stabilize signal path impedances
US6501157B1 (en) * 1998-04-15 2002-12-31 Micron Technology, Inc. Substrate for accepting wire bonded or flip-chip components
JP4290314B2 (en) * 2000-04-26 2009-07-01 Ｎｅｃエレクトロニクス株式会社 High-frequency circuit, module mounted with the same, and communication device
US6501664B1 (en) * 2000-06-30 2002-12-31 Intel Corporation Decoupling structure and method for printed circuit board component

Also Published As

Publication number Publication date
US6777791B2 (en) 2004-08-17
US20020140071A1 (en) 2002-10-03
JP2003521127A (en) 2003-07-08
WO2001056083A3 (en) 2002-03-28
WO2001056083A2 (en) 2001-08-02
EP1250717A2 (en) 2002-10-23

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