AU2001231482A1 - Method for filtering used in a digital phase locked loop - Google Patents

Method for filtering used in a digital phase locked loop

Info

Publication number
AU2001231482A1
AU2001231482A1 AU2001231482A AU3148201A AU2001231482A1 AU 2001231482 A1 AU2001231482 A1 AU 2001231482A1 AU 2001231482 A AU2001231482 A AU 2001231482A AU 3148201 A AU3148201 A AU 3148201A AU 2001231482 A1 AU2001231482 A1 AU 2001231482A1
Authority
AU
Australia
Prior art keywords
phase difference
difference value
local recovery
recovery clock
ideal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001231482A
Inventor
Tingbo He
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of AU2001231482A1 publication Critical patent/AU2001231482A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0994—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising an accumulator

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

A filtering method for digital Phase Lock Loop, comprises: define an ideal phase difference value between an input clock and a local recovery clock; calculate a phase difference between the input clock and the local recovery clock by a subtractor; compare the phase difference with the ideal phase difference value to adjust the local recovery clock in order to keep it phase difference stables in the ideal phase difference value. When adjusting the local recovery clock, taking the ideal phase difference value as a center, the phase difference is divided into different segments. For segment where the ideal phase difference value is located, the local recovery clock follows the phase difference with a minimum changing rate; and for segments farther apart from the ideal phase difference value, the local recovery clock follows the phase difference with a faster changing rate. The invention concerns non-error code and vibration minimization at the same time, so vibration tolerance is better raised, vibration transfer characteristic is very good, and net output vibration indicator at low band and high band parts is improved. <IMAGE>
AU2001231482A 2000-01-27 2001-01-20 Method for filtering used in a digital phase locked loop Abandoned AU2001231482A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN00101582 2000-01-27
CN00101582.6A CN1307406A (en) 2000-01-27 2000-01-27 Filtering method of digital phase lock loop
PCT/CN2001/000068 WO2001059931A1 (en) 2000-01-27 2001-01-20 Method for filtering used in a digital phase locked loop

Publications (1)

Publication Number Publication Date
AU2001231482A1 true AU2001231482A1 (en) 2001-08-20

Family

ID=4576075

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001231482A Abandoned AU2001231482A1 (en) 2000-01-27 2001-01-20 Method for filtering used in a digital phase locked loop

Country Status (9)

Country Link
US (1) US6819730B2 (en)
EP (1) EP1253719B1 (en)
CN (1) CN1307406A (en)
AT (1) ATE336826T1 (en)
AU (1) AU2001231482A1 (en)
BR (1) BR0107891A (en)
CA (1) CA2398596C (en)
DE (1) DE60122287D1 (en)
WO (1) WO2001059931A1 (en)

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GB2409383B (en) * 2003-12-17 2006-06-21 Wolfson Ltd Clock synchroniser
GB2413043B (en) * 2004-04-06 2006-11-15 Wolfson Ltd Clock synchroniser and clock and data recovery apparatus and method
US7646836B1 (en) * 2005-03-01 2010-01-12 Network Equipment Technologies, Inc. Dynamic clock rate matching across an asynchronous network
US7224638B1 (en) 2005-12-15 2007-05-29 Sun Microsystems, Inc. Reliability clock domain crossing
US7627065B2 (en) * 2005-12-21 2009-12-01 Sun Microsystems, Inc. Generating a clock crossing signal based on clock ratios
WO2007114944A2 (en) * 2006-04-04 2007-10-11 Rambus, Inc. Phase control block for managing multiple clock domains in systems with frequency offsets
CN100464503C (en) * 2006-09-12 2009-02-25 威盛电子股份有限公司 Time-vein signal regulating method and device
CN101083523B (en) * 2007-07-27 2010-08-11 华南理工大学 Method and device for realizing integrated time stamp clock synchronous phase-locked loop
KR100994128B1 (en) * 2008-09-23 2010-11-15 한국전자통신연구원 Timestamping method and Apparatus for precise network synchronization
KR20120114214A (en) * 2009-11-25 2012-10-16 신포니아 테크놀로지 가부시끼가이샤 Vibration damping device and vehicle provided therewith
TWI435596B (en) * 2010-07-06 2014-04-21 Realtek Semiconductor Corp Master/slave decision device and master/slave decision method applied to network device
US8959469B2 (en) 2012-02-09 2015-02-17 Altera Corporation Configuring a programmable device using high-level language
US9052900B2 (en) 2013-01-29 2015-06-09 Oracle International Corporation Serdes fast retrain method upon exiting power saving mode
US20180186546A1 (en) * 2016-12-29 2018-07-05 Dow Global Technologies Llc Packaging with Three-Dimensional Loop Material
CN107707263A (en) * 2017-08-04 2018-02-16 上海航天电子有限公司 Adapt to the universal integrated remote measurement ground checkout equipment of wide scope code check

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US3992580A (en) * 1975-04-24 1976-11-16 The United States Of America As Represented By The Secretary Of The Army Discrete control correction for synchronizing digital networks
CA1262173A (en) * 1986-05-29 1989-10-03 James Angus Mceachern Synchronization of asynchronous data signals
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US5033064A (en) * 1988-12-09 1991-07-16 Transwitch Corporation Clock dejitter circuit for regenerating DS1 signal
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JP2776098B2 (en) * 1991-11-27 1998-07-16 松下電器産業株式会社 Clock recovery circuit and time axis error correction device
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Also Published As

Publication number Publication date
EP1253719B1 (en) 2006-08-16
EP1253719A4 (en) 2004-10-20
US6819730B2 (en) 2004-11-16
US20030021371A1 (en) 2003-01-30
CA2398596C (en) 2008-04-15
CA2398596A1 (en) 2001-08-16
CN1307406A (en) 2001-08-08
ATE336826T1 (en) 2006-09-15
EP1253719A1 (en) 2002-10-30
BR0107891A (en) 2002-11-19
WO2001059931A1 (en) 2001-08-16
DE60122287D1 (en) 2006-09-28

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