AU2000262348A1 - Memory controller and interface - Google Patents

Memory controller and interface

Info

Publication number
AU2000262348A1
AU2000262348A1 AU2000262348A AU2000262348A AU2000262348A1 AU 2000262348 A1 AU2000262348 A1 AU 2000262348A1 AU 2000262348 A AU2000262348 A AU 2000262348A AU 2000262348 A AU2000262348 A AU 2000262348A AU 2000262348 A1 AU2000262348 A1 AU 2000262348A1
Authority
AU
Australia
Prior art keywords
interface
memory controller
controller
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2000262348A
Inventor
Arthur Y. Ng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Index Systems LLC
Original Assignee
Index Systems LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Index Systems LLC filed Critical Index Systems LLC
Publication of AU2000262348A1 publication Critical patent/AU2000262348A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
AU2000262348A 2000-07-26 2000-07-26 Memory controller and interface Abandoned AU2000262348A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2000/020135 WO2003100625A1 (en) 2000-07-26 2000-07-26 Memory controller and interface

Publications (1)

Publication Number Publication Date
AU2000262348A1 true AU2000262348A1 (en) 2003-12-12

Family

ID=29581721

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2000262348A Abandoned AU2000262348A1 (en) 2000-07-26 2000-07-26 Memory controller and interface

Country Status (2)

Country Link
AU (1) AU2000262348A1 (en)
WO (1) WO2003100625A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8171187B2 (en) 2008-07-25 2012-05-01 Freescale Semiconductor, Inc. System and method for arbitrating between memory access requests
EP2504768B1 (en) 2009-11-26 2015-08-26 Freescale Semiconductor, Inc. Integrated circuit and method for reducing violations of a timing constraint

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2625340B1 (en) * 1987-12-23 1990-05-04 Labo Electronique Physique GRAPHIC SYSTEM WITH GRAPHIC CONTROLLER AND DRAM CONTROLLER
EP0691616A1 (en) * 1994-07-08 1996-01-10 Advanced Micro Devices, Inc. RAM and ROM control unit
US6006303A (en) * 1997-08-28 1999-12-21 Oki Electric Industry Co., Inc. Priority encoding and decoding for memory architecture

Also Published As

Publication number Publication date
WO2003100625A1 (en) 2003-12-04

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase