AU2000239875A1 - Crosstalk analysis method, method for designing/manufacturing electronic circuitdevice by using the same, and recorded medium of electronic circuit library the refor - Google Patents

Crosstalk analysis method, method for designing/manufacturing electronic circuitdevice by using the same, and recorded medium of electronic circuit library the refor

Info

Publication number
AU2000239875A1
AU2000239875A1 AU2000239875A AU3987500A AU2000239875A1 AU 2000239875 A1 AU2000239875 A1 AU 2000239875A1 AU 2000239875 A AU2000239875 A AU 2000239875A AU 3987500 A AU3987500 A AU 3987500A AU 2000239875 A1 AU2000239875 A1 AU 2000239875A1
Authority
AU
Australia
Prior art keywords
circuitdevice
refor
designing
same
electronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2000239875A
Inventor
Yasuhiko Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of AU2000239875A1 publication Critical patent/AU2000239875A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
AU2000239875A 2000-04-21 2000-04-21 Crosstalk analysis method, method for designing/manufacturing electronic circuitdevice by using the same, and recorded medium of electronic circuit library the refor Abandoned AU2000239875A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2000/002624 WO2001082145A1 (en) 2000-04-21 2000-04-21 Crosstalk analysis method, method for designing/manufacturing electronic circuit device by using the same, and recorded medium of electronic circuit library therefor

Publications (1)

Publication Number Publication Date
AU2000239875A1 true AU2000239875A1 (en) 2001-11-07

Family

ID=11735952

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2000239875A Abandoned AU2000239875A1 (en) 2000-04-21 2000-04-21 Crosstalk analysis method, method for designing/manufacturing electronic circuitdevice by using the same, and recorded medium of electronic circuit library the refor

Country Status (5)

Country Link
US (1) US6772403B1 (en)
JP (1) JP3887231B2 (en)
CN (1) CN1244066C (en)
AU (1) AU2000239875A1 (en)
WO (1) WO2001082145A1 (en)

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US6651229B2 (en) * 2001-10-09 2003-11-18 International Business Machines Corporation Generation of refined switching windows in static timing analysis
JP2004185374A (en) * 2002-12-04 2004-07-02 Matsushita Electric Ind Co Ltd Crosstalk check method
TWI221238B (en) * 2002-05-17 2004-09-21 Via Tech Inc Circuitry cross-talk analysis with consideration of signal transitions
US7073140B1 (en) * 2002-08-30 2006-07-04 Cadence Design Systems, Inc. Method and system for performing crosstalk analysis
US7562323B1 (en) * 2003-09-19 2009-07-14 Cadence Design Systems, Inc. System, method and computer program product for handling small aggressors in signal integrity analysis
JPWO2005043420A1 (en) * 2003-11-04 2007-05-10 富士通株式会社 Electronic circuit design program, electronic circuit design method, and electronic circuit design apparatus
TWI249225B (en) * 2004-03-10 2006-02-11 Taiwan Semiconductor Mfg Interconnection routing method
US7159160B2 (en) * 2004-06-21 2007-01-02 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and apparatus for measuring switching noise in integrated circuits
US7383522B2 (en) * 2004-10-08 2008-06-03 Fujitsu Limited Crosstalk-aware timing analysis
EP1662410A1 (en) * 2004-11-30 2006-05-31 Infineon Technologies AG Method and device for analyzing crosstalk effects in an electronic device
US7225420B2 (en) * 2005-02-10 2007-05-29 Honeywell International Inc. System and method for signal integrity testing of electronic circuits
US20080148213A1 (en) * 2006-11-15 2008-06-19 Moussadek Belaidi Routing method for reducing coupling between wires of an electronic circuit
US8032851B2 (en) * 2006-11-15 2011-10-04 International Business Machines Corporation Structure for an integrated circuit design for reducing coupling between wires of an electronic circuit
JP5040463B2 (en) * 2007-06-20 2012-10-03 富士通セミコンダクター株式会社 Crosstalk noise analysis method
US8694946B1 (en) 2008-02-20 2014-04-08 Altera Corporation Simultaneous switching noise optimization
US7983880B1 (en) * 2008-02-20 2011-07-19 Altera Corporation Simultaneous switching noise analysis using superposition techniques
JP5353061B2 (en) * 2008-05-27 2013-11-27 富士通株式会社 Transmission delay analysis device, transmission delay analysis program, transmission delay analysis method
US8341574B2 (en) * 2009-03-06 2012-12-25 Synopsys, Inc. Crosstalk time-delay analysis using random variables
JP5691743B2 (en) * 2011-03-30 2015-04-01 富士通株式会社 Mounting design support program, method and apparatus
US9823298B2 (en) * 2015-08-12 2017-11-21 Arm Limited Critical path architect
CN106546904B (en) * 2016-10-18 2019-01-25 瑞斯康达科技发展股份有限公司 The method and system of crosstalk signal between a kind of determining signal wire

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0535824A (en) 1991-07-30 1993-02-12 Hokuriku Nippon Denki Software Kk Inter-layer orthogonal wiring inspection system
JP3076227B2 (en) 1995-08-29 2000-08-14 北陸日本電気ソフトウェア株式会社 Crosstalk error detector
JPH09147009A (en) 1995-11-24 1997-06-06 Hitachi Ltd Crosstalk delay deciding method and parallel wiring length limiting method
JP3175653B2 (en) 1997-07-18 2001-06-11 日本電気株式会社 Crosstalk error improvement method and method
JPH11154709A (en) 1997-11-20 1999-06-08 Hitachi Ltd Semiconductor device, and verifying device and method therefor
US5983006A (en) * 1997-12-31 1999-11-09 Intel Corporation Method for analyzing and efficiently eliminating timing problems induced by cross-coupling between signals
US6128769A (en) * 1997-12-31 2000-10-03 Intel Corporation Method for analyzing and efficiently reducing signal cross-talk noise
US6389581B1 (en) * 1999-07-16 2002-05-14 Silicone Graphics Inc. Optimizing repeaters positioning along interconnects
US6493854B1 (en) * 1999-10-01 2002-12-10 Motorola, Inc. Method and apparatus for placing repeaters in a network of an integrated circuit
US6449753B1 (en) * 2000-02-25 2002-09-10 Sun Microsystems, Inc. Hierarchical coupling noise analysis for submicron integrated circuit designs
US6507935B1 (en) * 2000-02-25 2003-01-14 Sun Microsystems, Inc. Method of analyzing crosstalk in a digital logic integrated circuit
US6637014B2 (en) * 2001-03-06 2003-10-21 Nec Corporation Crosstalk mitigation method and system

Also Published As

Publication number Publication date
JPWO2001082145A1 (en) 2004-05-13
JP3887231B2 (en) 2007-02-28
CN1452752A (en) 2003-10-29
WO2001082145A1 (en) 2001-11-01
CN1244066C (en) 2006-03-01
US6772403B1 (en) 2004-08-03

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