AU1427076A - Memory systems - Google Patents

Memory systems

Info

Publication number
AU1427076A
AU1427076A AU14270/76A AU1427076A AU1427076A AU 1427076 A AU1427076 A AU 1427076A AU 14270/76 A AU14270/76 A AU 14270/76A AU 1427076 A AU1427076 A AU 1427076A AU 1427076 A AU1427076 A AU 1427076A
Authority
AU
Australia
Prior art keywords
memory systems
memory
systems
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
AU14270/76A
Inventor
David William Wright
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Standard Electric Corp
Original Assignee
International Standard Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Standard Electric Corp filed Critical International Standard Electric Corp
Publication of AU1427076A publication Critical patent/AU1427076A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/328—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for runtime instruction patching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates
    • G06F8/66—Updates of program code stored in read-only memory [ROM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection
    • G06F9/264—Microinstruction selection based on results of processing
    • G06F9/267—Microinstruction selection based on results of processing by instruction selection on output of storage
AU14270/76A 1975-05-29 1976-05-25 Memory systems Expired AU1427076A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB2342375 1975-05-29

Publications (1)

Publication Number Publication Date
AU1427076A true AU1427076A (en) 1977-12-01

Family

ID=10195373

Family Applications (1)

Application Number Title Priority Date Filing Date
AU14270/76A Expired AU1427076A (en) 1975-05-29 1976-05-25 Memory systems

Country Status (4)

Country Link
AU (1) AU1427076A (en)
BE (1) BE842363A (en)
DE (1) DE2621399A1 (en)
FR (1) FR2312837A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2951040A1 (en) * 1979-01-16 1980-07-24 Digital Equipment Corp TAX STORAGE IN A TAX SECTION OF A CALCULATOR
US4484268A (en) * 1982-02-22 1984-11-20 Thoma Nandor G Apparatus and method for decoding an operation code using a plurality of multiplexed programmable logic arrays
DE68928112T2 (en) * 1988-03-18 1997-11-20 Toshiba Kawasaki Kk Mask rom with spare memory cells
JPH03142629A (en) * 1989-10-30 1991-06-18 Toshiba Corp Microcontroller
JPH04278299A (en) * 1991-03-07 1992-10-02 Sharp Corp Semiconductor memory
EP1244007A3 (en) * 2001-03-21 2007-05-23 Broadcom Corporation Dynamic microcode patching

Also Published As

Publication number Publication date
FR2312837A1 (en) 1976-12-24
DE2621399A1 (en) 1976-12-09
BE842363A (en) 1976-12-01

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