DE2951040A1 - TAX STORAGE IN A TAX SECTION OF A CALCULATOR - Google Patents

Description

Control memory in a control section of a computer

The invention relates to a control store in a control section a computer and relates in particular to a microprogram control memory in which a method for fast, flexible and efficient decoding of the machine script command is applied. Although the invention is only based on of high integration MOS (LSI) circuits for control stores is described, the basic method can also be used with other types of circuits, for example those with common bipolar elements.

In modern computers, micro-programming is used of their control section. This includes the storage of a microprogram which is the machine control sequence represents in a control store. This memory can be in the form of a read-only memory (ROM) or a writable one Memory. The sequential assignment through

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the microprogram is controlled by a microstep (micro-level) program counter or by the fact that the address of the next microinstruction in the control word is transmitted together with the microinstruction. The last mentioned procedure will described below, although the invention does not relate to this? Scheme is restricted.

In order to execute the machine language command, the assignment aligned with the correct part or parts of the microprogram for the current machine language instruction to be supplied and in the storage register lies. The normal procedure for decoding the computer instruction and directing the micro-program allocation is to the command operation code via a read-only memory (ROM) or a programmable logic array (PLA) into a start control memory address to be shown ("map"). In many cases, all that is required is an initial mapping. later The following mappings can be carried out, or a conditional microstep branching can be carried out by checking certain bits or bit combinations in the command register. Often there are microstep subroutines used to redirect control to other parts in the microprogram without the results of the initial mapping to lose which of course to learn from the address of the microprogram at the time of the subprogram call is. In general, a mapping scheme provides a control memory address which is then used to access to have the first microinstruction resulting from the instruction decoding. Serial operation to get an address first from the mapping operation and then having access to the first memory word is time consuming, and because the mapping time is generally about the same as that for access to a control store. The invention is therefore intended to achieve significant time savings when decoding the machine language command, it can also be used to control other inputs, such as interruptions, the on / off

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there would be a stack overflow etc. to decode.

The invention is therefore intended to provide a microprogram control store which employs a method for rapidly, flexibly and efficiently decoding a machine language instruction and in which a decoding of the machine language command and an access to the first control word, resulting from the decoding occurs at the same time. Furthermore, according to the invention, a microprogram control store can be created in which one or more control words modify bits or codes of other control words to modify their evaluation in order to reduce the number of control words that would otherwise were required.

Another object of the invention is to provide a microprogram control store having a programmable logic array (PLA) and read only memory (ROM) section, access to these control words not depending on the current instruction stored in the ROM section which is is generally cheaper and more compact than the PLA section, and access to these control words is dependent on the current instruction stored in the PLA section. Furthermore, a microprogram control memory is to be created with both a ROM and a PLA structure, the structure of which can be fused in the form of a MOS / LSI circuit, which results in a circuit reduction and a reduction in the connection lines and thus a smaller chip. In addition, the invention is according to a PLA part of the microprogram control memory are created, the control words have access to both the machine section as to be carried out also to the instruction, so that consequently the control section allocation of the computer a result of decoding of a through the PLA-section executed machine command. The invention is also intended to create a control store in which the PLA section of the microprogram control store is used for the performance of a command decoration.

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dation and the read-only memory (ROM) is used for the performance of a control word storage.

According to the invention, a microprogram control section for a computer is thus created, which both a PLA device for storing control words and a read-only memory (ROM) for storing control words. the Means to access the ROM storage mechanism relies on address inputs from an address register. The means to have access to the PLA control words are based on the address inputs and on a part or on all command inputs from a command register. A data transfer control unit or a multiplexer, which is coupled to the ROM and PLA Absehnitte, selects their Outputs due to a decoding of certain bits of the address inputs. This output creates the microinstruction and the next address. A feedback mechanism is also provided to the next address output from the multiplexer to be coupled to the next address register.

According to the invention, a control store thus includes both a PLA section and a ROM section for storage of control words. The ROM section is accessed through address inputs from the next address field to the Control words stored in the memory. The PLA portion of the memory is accessed through them Address inputs plus the inputs from the computer command register, with an accessed control word having a function of the current computer command. The selection between the PLA or the ROM section is made here by decoding certain bits of the address input.

The invention will now be described with reference to the drawings. Show it:

1 schematically shows a block diagram of the microprogram control memory according to the invention;

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Fig. 2 is a schematic block diagram of an embodiment of the invention in which the PLA and ROM sections merge together so that a single Column bit line of the PLA section or the -An- j order together with the corresponding ROM column-; bit line is set;

3 schematically shows an example of a combined ROM uno; PLA control memory, in which there are nine two-bit control words and one two-bit control output; !

Figures 4a and 4b schematically show the symbols used for logic links in the example in Figure 3; !

and <

FIG. 5 shows, in table form, the coding of the control memory in the example of FIG. 3.

In the invention, a computer control section is used with a control memory which is made up of both PLA and ROM structures for storing control words. Read only memory (ROM) is a direct access memory in which the data is permanently stored in the memory so that the memory can only be read. The memory has η address inputs, which are completely decoded in order to have access to 2 memory locations. EP Read-Only Memories (EPROMs) ₁ P read-only memories (PROMs) and similar devices belong in the same family.

A programmable logic field or a programmable logic arrangement (PLA) consists of two fields or arrangements: namely a group of AND gates and another group of OR gates. The AND gates indicate the correct one Input and the complement of the η inputs, which can be programmed for connections if necessary.

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The OR gates have inputs from the outputs of the AND gates and connections can be programmed if necessary.

Both the ROM and PLA structures or sections store control words consisting of a microinstruction and a next address. This control memory, which is made up of both a PLA section 2 and a ROM section for storing control words, is shown in FIG. Section 2 of the control store, which is implemented as a PLA section, is variable, but can normally be 1 / nth of the total store, where η is 2, 4 or 8. Each memory section 2 and 4 has an address input 12 and 14, respectively, from a register 4 for the next address. The register 4 contains the next address which has been fetched from the last memory word via a line 30 for the next address. The PLA section 2 also has an input 22 from an instruction register 8 or from some other source of inputs to be decoded. Normally, both the correct input and the complement of the inputs are used by the AND gate decoders of the PLA section 2 and the ROM section 4.

The ROM section 4 has a ROM memory field 16 for storing control words and a decoding field 18. The decoding field 18 receives part of the address as one input, and the row selection lines of the ROM memory field 16 are activated through its outputs. Each row select line from ROM decoder 18 selects a certain number of control words in memory array 16, one of which is then selected by output multiplexer 20 under control of the remaining address bits. The fact that the ROM decoder 16 is reused by a number of control words on each row select line and has fewer inputs than the AND gate decoder of the PLA section 2 of the control store is important when the silicon area is taken into account that is required to

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to machine the control store as a MOS / LSI element.

The PLA section 2 has two parts, namely an arrangement 24 of OR gates and an arrangement 26 of AND gates The arrangement 24 of OR gates is the same as the memory array 16 of the ROM section 4, except that only one control word can be selected for each line selection line. The array 26 of AND gates serves as a decoder for activating the row selection lines and consequently for selection each of the control words in the array 24 of OR gates, the PLA memory and logic gate array 24 is less effective than ROM memory array 16 because it there is only one decoder AND gate for each word and the AND gates 24 have inputs rather than the decoder of the ROM section 4. The reason is that it is a decoder AND gate per control word, since the programming of the arrangement 26 of AND gates is unique for each control word have to be. Access to any control word stored in the PLA section of the control store is made by the correct state of the address inputs 12 and of command inputs 22 to be decoded, such as by the contents of the command register of the computer.

The choice between the PLA assembly 24 and the ROM memory field 16 is carried out by a few bits or by a combination of bits from the next address 14 and 16. this depends on the number of lines (AND gates) in the PLA section 2, the number of lines in the ROM section 20 and the number Control words to which there is access in each line in the ROM section 20. This selection takes place in a multiplexer 28 instead. It is important here that the control words are in every part of the memory with this control memory organization. These control words, to which as a result of a certain decoding of the contents of the command register 8 access exists are set in the PLA memory field 24 while other words in the ROM memory array 16 as well as in the PLA

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Storage field 24 of the memory are housed. For consecutive Words can just as easily be accessed from the section in which a next address in dam Area of the desired memory is precisely designated. Microinstructions of the program can be stored between the ROM memory field 16 and the PLA field 24 with OR gates mixed in any way will. The correct assignments can be made by the assembler program be done when the microprogram is created.

As noted, the inputs to array 26 are generally with the AND gates of TLA section 22 the correct (address) and complements of the next address 12 and the parts of the command 22 that are required to generate the To control microprogram sequence. As a result, takes place in the AND gate arrangement 26 there is no exhaustive decoding of the inputs as in the case of the ROM decoder 18, there are only those Decodes of inputs 12 and 22 required, which are necessary to have access to each word. The next Address (12) acts as a "mapping code" which selects a group of the AND gates in array 26. The AND gate or the corresponding elements which are activated for each mapping code depend on the coding of the command input (26). This process is explained below using an example. The whole area of the addresses assigned to PLA section 2 are not necessarily used as the number of required Code is equal to the number of images required. By using the figure code next Address are represented locations in the microprogram at which access to the control word of codes or individual bits in the command register 8 depends. This figure actually corresponds to the one at the beginning for others Control modes have been described in which the mapping created a control address; however, here the PLA section generates 2 a microinstruction and not the address of the microinstruction. This results in faster access to the

0 3 0 0 3 0/0 5 9 9

Microinstruction as if the mapping were just removing the address of the instruction. The figure can also be in the control store and need not be entered in a separate section. Since each figure code is a Number of AND gates in the arrangement 26 can control, it is possible to have a number of images up to the number available of AND gates and the addresses assigned to PLA section 2. It's an adaptability for the control section, which involves mapping or checking the command inputs at any point in the microgram made possible without wasting time. In addition, AND elements can be programmed with corresponding ("don't care") inputs so that they respond to an area or group of mapping codes and / or command codes. this leads to high-performance programming methods if they are coupled with the possibility of modifying control words, such as will be described below.

The OR gate arrangement 24 stores control words similar to the memory field 16 of the ROM section 4. Each control word is accessed under the control of its AND element. One the special features of this control scheme is that a logic in the memory array 24 of OR gates can be carried out if more than one AND element is active at a certain point in time. This then has access result in more than one word at a given time, in which case the resulting output is OR or is the AND of all selected control words. The logical function performed then depends on the one used for the arrangement 24, logical polarity convention. One or more control words with priority ones or zeros can be used to modify another control word. The modification can be in the microinstruction or the next Address part of the control word. For this it is necessary to assign bits and micro instruction codes and addresses, so that the correct control word modification can take place. For example, a group of microinstructions for byte

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Operations are programmed, and all the microinstructions of the Groups can be accessed by a single word at the same time as one of the two microinstructions, can be modified in word operations. Such a thing Word would override the code or bit designating a byte operation by 1, creating a word operation is determined.

FIG. 2 shows the organization of a combined PLA and ROM section. (Here, the same reference symbols denote the same or corresponding parts) The control store is implemented using MOS-LSI circuit technology. The PLA and ROM-sections can dsssen be applied on the same silicon chip as a result _w. By applying the two memory structures, certain savings in terms of chip size can be achieved over two separate structures. In the conventional POM designs, all of the column bit lines for a specific bit are set next to one another in order to facilitate the design of the output multiplexer. When the PLA and ROM sections are combined as in Fig. 2, a single column bit line of the PLA array is defined with OR gates along with the corresponding ROM column bit lines; for the same reasons, an additional input on the output multiplexer selects the PLA column bit lines, while additional inputs on the multiplexer 40 select the ROM column bit lines. By defining the PLA bit lines together with the ROM bit lines, a significant number of connections to the chip are eliminated. This then boils down to a smaller chip and higher speed operation. This is shown in Fig. 3 on the right. PLA bit lines 103 and 104, which are closest to ROM bit lines 101 and 102, facilitate connection to multiplexer 105.

In the case of large read-only memories, it is common practice to set the decoder field in the middle of the memory field and the row select line from both sides of the decoder

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in the control memory array so as to halve the length of the row select lines. This gives a faster one Access time, internally the propagation delay on the Row select lines is decreased. Such an embodiment is shown in general form in FIG. In the The combined arrangement of FIG. 2 is a single arrangement 42 of AND gates in the middle of the entire memory array 4 4 established. This arrangement 42 serves both as the AND gate arrangement of the PLA section and as the decoder arrangement of the ROM section. Each line selection line is activated by the output of a single AND gate. The logic gate serves as the AND gate of the PLA section for the only control word on the row select line coming out of the PLA section and as the ROM decoder for the other control words on the row select line.

The AND gate arrangement 42 of the combined arrangement or structure 44 has two groups of inputs. A group 14 is the same as that of the ROM section 4 in Fig. 1, and the other group of inputs is the same as that on PLA section 2 of FIG are a combination of the AND element of the PLA section and of the decoder AND gate of the ROM section. To make the AND gate like the PLA AND gate of FIG. 2, the PLA group of inputs is used, and the ROM group of inputs is done correctly so that the link is a Function of PLA programming is. To make the AND gate similar to the ROM decoder of Fig. 2, the ROM group of inputs is used and the PLA group is made true. The combined AND gate decoder 42 operates like the PLA AND gates when the next address is in the range of those that assigned to the PLA section. At this point, the PLA column bit line is then passed through the output multiplexer 40 selected. If the next address is in the range of that assigned to the ROM section, will

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the AND gate 42 operated as the ROM decoder 18, and one the ROM column bit line is passed through the output complexer 4 0 selected. The. combined AND gate arrangement 4 2 is necessary to interdigitize the ROM and PLA bit lines, and at the same time it keeps the row select lines as short as possible · This also results in a saving anChipflache, as the ones intended for prior loading Circuits for a group of AND gates and their assigned No buffer amplifiers are required.

An illustrative example of a to «an ,, .- .; ngcf a £ th or combine τ. .:, ROM or PLA control memory is shown in FIG. Naturally this simplistic example is only more fundamental Type and is used for explanation only; however, the basic procedure outlined can be used with any of the myriad changes of control word and address bit lengths can be used. In this example, nine 2-bit control words are provided, four in the ROM storage section of the control store 100 and five in the PLA section of the control store 100. The store 100 is basically in a half with a Group of bit lines 101 and 102 for the ROM section and divided into another group 103 and 104 for the PLA section. These two groups of bit lines are made up of AND gates 106 to 109 and OR gates by a multiplexer 105 110 and 111 are used several times, which by means of an address input 304 (the A2 and A2 complement). In the example, the embodiment of Fig. 2 is not shown, in which the decoder field in the middle of the memory field and the line selection line is controlled from both sides. This can be done easily by doing this can be achieved that the row selection bit lines 200 to 204 are extended to the left and amplifiers 700 to 704 and a control memory 100, which are on the right-hand side, are arranged in mirror image. There are five row select lines 200 to 204 are provided, of which only four, namely lines 200 to 203, for the ROM section and five can be used for the PLA section. (This additional

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PLA selection line is somewhat inefficient as there is room for one fifth ROM word exists, but this word cannot

since the address inputs 303 and 304 for the ROM section are already fully decoded.) Es are 10 inputs to the control store, namely three address lines AO, A1 and A2, correct and complementary inputs (Address inputs 300, 301 and 304) and two command register lines 10 and 11, correct and complement inputs (Command inputs 302 and 303). Address input 304 selects between the ROM and PLA sections. If it doesn't is asserted, the ROM section is selected, with ROM bit lines 101 and 102 being the two output lines 600 and 601 are connected and the eight inputs (via OR gates 500 to 507) of the PLA AND gate part of the combined AND decoder cannot be asserted. When address input 304 is asserted, the PLA bit lines are 103 and 104 are connected to two output lines 600 and 601 and the four inputs are (via OR gates 4 00 to 403) at the decoding part of the composite AND part / decoder asserted.

In the example of FIG. 3, logic elements 800 and 900 are represented by half-filled circles and section lines. Two links 800 of the first orientation, which are separated by dashed lines, are shown in FIG. 4a. The filled parts 900 of the circle of the logic elements 800 designate inputs. Input lines 811 and 812 run to the logic gate inputs (99). A complete link is designated when any line (here line 820) runs perpendicular to an input line (811 and 812) and intersects circles 98. As a result, line 820 in FIG. 4a acts as an output line. If the control store is implemented using MOS / FET technology, a production route is shown in FIG. 4b. The "control" connection of the transistor 801 acts similarly to a logic element input in FIG. 4a and is connected to the input lines 811 and 812. A "sink" port 802 is

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connected to lines 811 and 812 , which run perpendicular to input line 820 on the schematic diagram. The second orientation 900 acts the same as the orientation 800, except that the feed lines and ports are rotated 90 degrees counterclockwise.

The decoding of the control store in the example of FIG. 3 is shown in FIG. The first four addresses ( 000-011) with an address bit 304 as 0 have access to the four words stored in the ROM portion of the memory. Addresses 100 and 101 act as mapping codes which enable parts of the PLA portion of the memory. The real word or corresponding words that have access to the PLA section depends on the decoding of inputs 302 and 303 from the command register. Only words in the control section have access to an address input 100 and a command input X, X (which mean "don't care") and as a result they generate an error output 0. The principle of overriding applies to the last three Inputs of FIG. 4 shown, which are all enabled by the translation code address input 101. The last two inputs are mutually exclusive, which means they are independent of the command input 302, and create outputs 10 and 01, respectively. The third of the latter inputs is a function of the command input 302. When the input 302 is asserted, it will selected together with one of the last two inputs. The resulting output is the OR function of the selected words or in this case 10 or 11.

The principle illustrated in the above example can be applied to many different processing systems with some of the advantages associated therewith.

End of description

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Claims (20)

Claims f 1./ control memory in a control section of a computer, characterized by first means (16) for storing control words which contain both a microinstruction and a next address; second means (24) for storing control words containing both a microinstruction and a next address; by means (18) for gaining access to the first means (16) storing control words on the basis of the decoding of address inputs; and by means (26) for gaining access to the second means (24) storing control words on the basis of the decoding of address inputs and at least a portion of the microinstruction inputs. 2. Control store according to claim 1, characterized by a multiplexer (28) which is connected to the two storage devices (16; 24) is coupled and which selects one of the storage devices. 3. Control store according to claim 2, characterized by a device (6) for coupling the next address output from the multiplexer (28) to the devices (18,26), 030030/0599 which allow access to the two memories (16, 24). 4. Control store according to claim 3, characterized in that net that the means (18) for access to the first storage means (16) is an exhaustive decoding of / virus inputs. 5. Control store according to claim 4, characterized in that that the means (18) to have access to the first memory means (16) have their address inputs receives the control words stored in the memory from the address field via an address register (6). 6. Control store according to claim 5, characterized in that that the means (18) to have access to the first memory (16) also receive their address inputs from a program counter. 7. Control store according to claim 5, characterized in that that the means (26) for accessing the second memory (24) have inputs from an instruction register (8) receives. 8. Control store according to claim 7, characterized in that that the second memory means (24) and the means (26) to access the second memory to have a programmable logic arrangement (PLA 2). 9. Control store according to claim 8, characterized in that that the means (26) to have access to the second memory (24) to a particular one Time allows access to more than one control word. 10. Control store according to claim 9, characterized in that g e k e η η-records, that the device (26), the access to 03C030 / 0599 the second memory (24), and which allows access to more than one control word at a given point in time, allows one or more accessed control words to modify another accessed control word. 11. Control memory according to claim 7 or 8, characterized geke η: .- characterized in that said first memory means (26) and the means (18) for access to have the first storage means, a read-only memory (ROM 4). 12. Control store according to Claim 11, characterized in that that the read-only memory (ROM 4) and the programmable logic arrangement (PLA 2) merged or are mixed. 13. Control store according to claim 14, characterized in that g e k e η n- show that the fused programmable Logic arrangement (PLA 4) and the read-only memory (ROM 2) a single AND gate arrangement with two groups of inputs have, of which one group is assigned to the ROM inputs and the other group to the PLA inputs. 14. Control memory according to claim 13, characterized in that the fused programmable logic arrangement (PLA 2) and the read-only memory (ROM 4) have a single AND element for each row selection line, which is used as the AND element (26) for the programmable logic arrangement (PLA 2) is used for the single control word on the row selection line from the programmable logic arrangement (PLA 2) and as a read-only memory decoder (18) for the remaining control words on the row selection line. 15. Control store according to claim 14, characterized in that that the column bit lines of the read-only memory (ROM 4) together with a corresponding bit line the programmable logic arrangement (2) are defined, D? Γ 0 30 / OB « ¹¹ thereby reducing the number of trunk lines and trunk line connection. 16. Control store according to Claim 15, characterized in that that the unused groups of inputs are made true or correct at a certain point in time, so as to act as "dont't cares" parts in the AND gates. 17. Control store according to claim 16, characterized in that that the control memory is divided so that a part of the control memory on the side of the combined ROM decoder and the PLA AND gate is applied, thereby reducing the propagation delay along the row select lines To shorten. 18. Control store according to one of claims 11 or 17, characterized in that the selection between the PLA part (2) of the memory is determined by decoding Bits of the address inputs. 19. Control store according to claim 18, characterized in that that both the correct input and the complement of the inputs are used. 20. A method of controlling a memory in a control section a computer, characterized in that control words that contain both a microinstruction and a Contain next address, both in a first (16) and a second means (24) for storing control words are stored in that the first storage device (16) has access due to a decoding of address inputs, and that the second memory device (24) due to the Decoding of the address inputs and at least part of the command inputs has access. 03 0 0 30/0599