AU1283300A - A serial-parallel binary multiplier - Google Patents

A serial-parallel binary multiplier

Info

Publication number
AU1283300A
AU1283300A AU12833/00A AU1283300A AU1283300A AU 1283300 A AU1283300 A AU 1283300A AU 12833/00 A AU12833/00 A AU 12833/00A AU 1283300 A AU1283300 A AU 1283300A AU 1283300 A AU1283300 A AU 1283300A
Authority
AU
Australia
Prior art keywords
serial
parallel binary
binary multiplier
multiplier
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU12833/00A
Inventor
Andrew Dewhurst
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Systolix Ltd
Original Assignee
Systolix Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Systolix Ltd filed Critical Systolix Ltd
Publication of AU1283300A publication Critical patent/AU1283300A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/527—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel
    • G06F7/5272—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel with row wise addition of partial products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5332—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by skipping over strings of zeroes or ones, e.g. using the Booth Algorithm
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4812—Multiplexers

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
AU12833/00A 1998-12-04 1999-11-24 A serial-parallel binary multiplier Abandoned AU1283300A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GBGB9826592.9A GB9826592D0 (en) 1998-12-04 1998-12-04 A serial binary multiplier
GB9826592 1998-12-04
PCT/GB1999/003897 WO2000034853A1 (en) 1998-12-04 1999-11-24 A serial-parallel binary multiplier

Publications (1)

Publication Number Publication Date
AU1283300A true AU1283300A (en) 2000-06-26

Family

ID=10843579

Family Applications (1)

Application Number Title Priority Date Filing Date
AU12833/00A Abandoned AU1283300A (en) 1998-12-04 1999-11-24 A serial-parallel binary multiplier

Country Status (3)

Country Link
AU (1) AU1283300A (en)
GB (1) GB9826592D0 (en)
WO (1) WO2000034853A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2908905A1 (en) * 2006-11-20 2008-05-23 R L Daniel Torno Sa METHOD AND MULTIPLE CIRCUIT OF BINARY NUMBERS
US8866662B1 (en) 2012-10-21 2014-10-21 Steve Naumov Sequential analog/digital conversion and multiplication

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4849921A (en) * 1985-06-19 1989-07-18 Nec Corporation Arithmetic circuit for calculating the absolute value of the difference between a pair of input signals
JPH03116327A (en) * 1989-09-29 1991-05-17 Toshiba Corp Multiplication system
JP3081710B2 (en) * 1992-08-18 2000-08-28 株式会社東芝 Multiplier with overflow detection function

Also Published As

Publication number Publication date
WO2000034853A1 (en) 2000-06-15
GB9826592D0 (en) 1999-01-27

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase