AU1219001A - Method of forming a microelectronic assembly - Google Patents

Method of forming a microelectronic assembly

Info

Publication number
AU1219001A
AU1219001A AU12190/01A AU1219001A AU1219001A AU 1219001 A AU1219001 A AU 1219001A AU 12190/01 A AU12190/01 A AU 12190/01A AU 1219001 A AU1219001 A AU 1219001A AU 1219001 A AU1219001 A AU 1219001A
Authority
AU
Australia
Prior art keywords
forming
microelectronic assembly
microelectronic
assembly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU12190/01A
Inventor
John A. Burroughs
Daniel Gamota
Jeffrey J. Norton
James A. Wrezel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of AU1219001A publication Critical patent/AU1219001A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
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    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
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    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
AU12190/01A 1999-10-19 2000-10-19 Method of forming a microelectronic assembly Abandoned AU1219001A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US42163399A 1999-10-19 1999-10-19
US09421633 1999-10-19
PCT/US2000/029014 WO2001029895A1 (en) 1999-10-19 2000-10-19 Method of forming a microelectronic assembly

Publications (1)

Publication Number Publication Date
AU1219001A true AU1219001A (en) 2001-04-30

Family

ID=23671368

Family Applications (1)

Application Number Title Priority Date Filing Date
AU12190/01A Abandoned AU1219001A (en) 1999-10-19 2000-10-19 Method of forming a microelectronic assembly

Country Status (2)

Country Link
AU (1) AU1219001A (en)
WO (1) WO2001029895A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100433320C (en) * 2005-10-28 2008-11-12 南茂科技股份有限公司 Chip package structure and lug manufacturing process

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0181615B1 (en) * 1995-01-30 1999-04-15 모리시다 요이치 Semiconductor unit package, semiconductor unit packaging method, and encapsulant for use in semiconductor unit packaging
JP3263288B2 (en) * 1995-09-13 2002-03-04 株式会社東芝 Semiconductor device
US6121689A (en) * 1997-07-21 2000-09-19 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
JP2924830B2 (en) * 1996-11-15 1999-07-26 日本電気株式会社 Semiconductor device and manufacturing method thereof
JPH1154662A (en) * 1997-08-01 1999-02-26 Nec Corp Flip-chip resin-sealed structure and resin-sealing method
JP3663938B2 (en) * 1997-10-24 2005-06-22 セイコーエプソン株式会社 Flip chip mounting method
KR100352865B1 (en) * 1998-04-07 2002-09-16 신꼬오덴기 고교 가부시키가이샤 Semiconductor device and method for manufacturing the same
US6040630A (en) * 1998-04-13 2000-03-21 Harris Corporation Integrated circuit package for flip chip with alignment preform feature and method of forming same

Also Published As

Publication number Publication date
WO2001029895A1 (en) 2001-04-26

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