ATE555560T1 - Fehlererkennung in asymmetrischen hochgeschwindigkeitsschnittstellen unter verwendung dedizierter schnittstellenleitungen - Google Patents

Fehlererkennung in asymmetrischen hochgeschwindigkeitsschnittstellen unter verwendung dedizierter schnittstellenleitungen

Info

Publication number
ATE555560T1
ATE555560T1 AT09013467T AT09013467T ATE555560T1 AT E555560 T1 ATE555560 T1 AT E555560T1 AT 09013467 T AT09013467 T AT 09013467T AT 09013467 T AT09013467 T AT 09013467T AT E555560 T1 ATE555560 T1 AT E555560T1
Authority
AT
Austria
Prior art keywords
component
signature
read
fault detection
interface
Prior art date
Application number
AT09013467T
Other languages
English (en)
Inventor
Joseph Macri
Stephen Morein
Claude Gauthier
Lee E Ming-Ju
Chen Lin
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE555560T1 publication Critical patent/ATE555560T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L2001/0092—Error control systems characterised by the topology of the transmission link
    • H04L2001/0094—Bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Communication Control (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Hardware Redundancy (AREA)
AT09013467T 2005-11-10 2006-11-10 Fehlererkennung in asymmetrischen hochgeschwindigkeitsschnittstellen unter verwendung dedizierter schnittstellenleitungen ATE555560T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US73573105P 2005-11-10 2005-11-10

Publications (1)

Publication Number Publication Date
ATE555560T1 true ATE555560T1 (de) 2012-05-15

Family

ID=37891946

Family Applications (1)

Application Number Title Priority Date Filing Date
AT09013467T ATE555560T1 (de) 2005-11-10 2006-11-10 Fehlererkennung in asymmetrischen hochgeschwindigkeitsschnittstellen unter verwendung dedizierter schnittstellenleitungen

Country Status (4)

Country Link
US (1) US8892963B2 (de)
EP (2) EP1955467A2 (de)
AT (1) ATE555560T1 (de)
WO (1) WO2007054808A2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9459960B2 (en) 2005-06-03 2016-10-04 Rambus Inc. Controller device for use with electrically erasable programmable memory chip with error detection and retry modes of operation
US7831882B2 (en) 2005-06-03 2010-11-09 Rambus Inc. Memory system with error detection and retry modes of operation
US7562285B2 (en) * 2006-01-11 2009-07-14 Rambus Inc. Unidirectional error code transfer for a bidirectional data link
US7644344B2 (en) * 2007-05-15 2010-01-05 Intel Corporation Latency by offsetting cyclic redundancy code lanes from data lanes
JP5482275B2 (ja) * 2009-04-01 2014-05-07 セイコーエプソン株式会社 記憶装置、基板、液体容器、データ記憶部に書き込むべきデータをホスト回路から受け付ける方法、ホスト回路に対し電気的に接続可能な記憶装置を含むシステム
CN101859235B (zh) * 2009-04-01 2013-09-18 精工爱普生株式会社 具有多个存储装置的系统以及用于该系统的数据传输方法
US8307270B2 (en) 2009-09-03 2012-11-06 International Business Machines Corporation Advanced memory device having improved performance, reduced power and increased reliability
JP5556371B2 (ja) 2010-05-25 2014-07-23 セイコーエプソン株式会社 記憶装置、基板、液体容器、データ記憶部に書き込むべきデータをホスト回路から受け付ける方法、ホスト回路に対し電気的に接続可能な記憶装置を含むシステム
US8943239B2 (en) * 2012-07-30 2015-01-27 Qualcomm Incorporated Data snooping direct memory access for pattern detection
US10216625B2 (en) * 2012-09-24 2019-02-26 Sk Hynix Memory Solutions Inc. Hardware integrity verification
MY180992A (en) 2013-03-13 2020-12-15 Intel Corp Memory latency management
FR3038188B1 (fr) * 2015-06-29 2017-08-11 Stmicroelectronics (Grenoble 2) Sas Systeme de verification de l’integrite d’une communication entre deux circuits
GB2574614B (en) * 2018-06-12 2020-10-07 Advanced Risc Mach Ltd Error detection in an interconnection network for an integrated circuit

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5150368A (en) * 1990-04-10 1992-09-22 Rolm Systems Minimization of modem retransmissions
US5754754A (en) * 1995-07-26 1998-05-19 International Business Machines Corporation Transmission order based selective repeat data transmission error recovery system and method
GB2313747A (en) 1996-05-30 1997-12-03 Motorola Ltd Data transmission verification
US6014767A (en) * 1996-09-04 2000-01-11 International Business Machines Corporation Method and apparatus for a simple calculation of CRC-10
US5745502A (en) * 1996-09-27 1998-04-28 Ericsson, Inc. Error detection scheme for ARQ systems
US6327688B1 (en) * 1998-08-07 2001-12-04 Analog Devices, Inc. Data bus with automatic data integrity verification and verification method
JP2002351689A (ja) * 2001-05-30 2002-12-06 Nec Corp データ転送システム
US6760814B2 (en) * 2001-12-17 2004-07-06 Lsi Logic Corporation Methods and apparatus for loading CRC values into a CRC cache in a storage controller
US6938188B1 (en) * 2002-01-29 2005-08-30 Advanced Digital Information Corporation Method for verifying functional integrity of computer hardware, particularly data storage devices

Also Published As

Publication number Publication date
US20070104327A1 (en) 2007-05-10
EP2141848A2 (de) 2010-01-06
WO2007054808A3 (en) 2007-10-04
US8892963B2 (en) 2014-11-18
EP1955467A2 (de) 2008-08-13
EP2141848B1 (de) 2012-04-25
EP2141848A3 (de) 2010-03-17
WO2007054808A2 (en) 2007-05-18

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