ATE536671T1 - Taktrückgewinnung mit mehrfacher eingabe über paketnetzwerke - Google Patents

Taktrückgewinnung mit mehrfacher eingabe über paketnetzwerke

Info

Publication number
ATE536671T1
ATE536671T1 AT10163407T AT10163407T ATE536671T1 AT E536671 T1 ATE536671 T1 AT E536671T1 AT 10163407 T AT10163407 T AT 10163407T AT 10163407 T AT10163407 T AT 10163407T AT E536671 T1 ATE536671 T1 AT E536671T1
Authority
AT
Austria
Prior art keywords
filtered
stream
packet networks
delays
input via
Prior art date
Application number
AT10163407T
Other languages
English (en)
Inventor
Kamran Rahbar
Original Assignee
Zarlink Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zarlink Semiconductor Inc filed Critical Zarlink Semiconductor Inc
Application granted granted Critical
Publication of ATE536671T1 publication Critical patent/ATE536671T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0679—Clock or time synchronisation in a network by determining clock distribution path in a network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0852—Delays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0644—External master-clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0852—Delays
    • H04L43/087—Jitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/10—Active monitoring, e.g. heartbeat, ping or trace-route
    • H04L43/106—Active monitoring, e.g. heartbeat, ping or trace-route using time related information in packets, e.g. by adding timestamps
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/28—Flow control; Congestion control in relation to timing considerations
    • H04L47/283—Flow control; Congestion control in relation to timing considerations in response to processing delays, e.g. caused by jitter or round trip time [RTT]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Environmental & Geological Engineering (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
AT10163407T 2009-05-22 2010-05-20 Taktrückgewinnung mit mehrfacher eingabe über paketnetzwerke ATE536671T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GBGB0908883.2A GB0908883D0 (en) 2009-05-22 2009-05-22 Multi input timing recovery over packet networks

Publications (1)

Publication Number Publication Date
ATE536671T1 true ATE536671T1 (de) 2011-12-15

Family

ID=40862865

Family Applications (1)

Application Number Title Priority Date Filing Date
AT10163407T ATE536671T1 (de) 2009-05-22 2010-05-20 Taktrückgewinnung mit mehrfacher eingabe über paketnetzwerke

Country Status (5)

Country Link
US (1) US8774227B2 (de)
EP (1) EP2254267B1 (de)
CN (1) CN101895381B (de)
AT (1) ATE536671T1 (de)
GB (1) GB0908883D0 (de)

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CN102907021B (zh) * 2010-05-17 2016-06-01 瑞典爱立信有限公司 优化定时分组传输
US9319054B2 (en) 2011-09-27 2016-04-19 Anue Systems, Inc. Systems and methods utilizing randomized clock rates to reduce systematic time-stamp granularity errors in network packet communications
JP5716229B2 (ja) * 2011-12-28 2015-05-13 株式会社日立製作所 時刻同期システム、管理ノード、及び時刻同期方法
KR102031268B1 (ko) 2012-01-04 2019-10-11 마벨 월드 트레이드 리미티드 시간-인식 디바이스들 사이에 시간 정보를 통신하는 방법 및 장치
US9806835B2 (en) 2012-02-09 2017-10-31 Marvell International Ltd. Clock synchronization using multiple network paths
US9112630B1 (en) * 2012-02-09 2015-08-18 Marvell Israel (M.I.S.L) Ltd. Clock synchronization in the presence of security threats
EP2813016B1 (de) 2012-02-09 2019-09-11 Marvell Israel (M.I.S.L) LTD. Taktsynchronisierung anhand von mehreren netzwerkpfaden
JP5811891B2 (ja) * 2012-02-24 2015-11-11 富士通株式会社 パケット転送遅延測定システム
US9547332B1 (en) 2012-03-21 2017-01-17 Marvell Israel (M.I.S.L) Ltd. Accurate time capture and transfer between clock domains
WO2013167977A1 (en) * 2012-05-09 2013-11-14 Marvell Israel (M.I.S.L.) Ltd. Clock synchronization using multiple network paths
WO2013170359A1 (en) * 2012-05-16 2013-11-21 Microsemi Semiconductor Ulc Method of adjusting a local clock in asynchronous packet networks
US9356721B2 (en) 2012-06-26 2016-05-31 Marvell World Trade Ltd. Methods and apparatus for precision time stamping
CN102841599B (zh) * 2012-08-24 2014-12-24 北京合锐赛尔电力科技股份有限公司 智能配电开关控制回路故障检测电路及该电路的检测方法
DK2709298T3 (en) * 2012-09-18 2018-08-27 Omicron Electronics Gmbh Synchronization method and electronic device using redundant connections
US9407733B1 (en) 2012-11-09 2016-08-02 Marvell Israel (M.I.S.L) Ltd. Time correction using extension fields
US9923710B2 (en) * 2016-06-15 2018-03-20 Silicon Laboratories Inc. Digital oversampling clock and data recovery circuit
US11689440B2 (en) 2019-02-06 2023-06-27 Marvell Israel (M.I.S.L) Ltd. Method and apparatus for transmit time timestamping
US11128742B2 (en) 2019-03-08 2021-09-21 Microsemi Storage Solutions, Inc. Method for adapting a constant bit rate client signal into the path layer of a telecom signal
US10972084B1 (en) 2019-12-12 2021-04-06 Microchip Technology Inc. Circuit and methods for transferring a phase value between circuits clocked by non-synchronous clock signals
US10917097B1 (en) 2019-12-24 2021-02-09 Microsemi Semiconductor Ulc Circuits and methods for transferring two differentially encoded client clock domains over a third carrier clock domain between integrated circuits
US10992301B1 (en) 2020-01-09 2021-04-27 Microsemi Semiconductor Ulc Circuit and method for generating temperature-stable clocks using ordinary oscillators
US11239933B2 (en) 2020-01-28 2022-02-01 Microsemi Semiconductor Ulc Systems and methods for transporting constant bit rate client signals over a packet transport network
WO2021195147A1 (en) 2020-03-23 2021-09-30 Marvell Israel (M.I.S.L) Ltd. One-step timestamping in network devices
US11424902B2 (en) 2020-07-22 2022-08-23 Microchip Technology Inc. System and method for synchronizing nodes in a network device
US11916662B2 (en) 2021-06-30 2024-02-27 Microchip Technology Inc. System and method for performing rate adaptation of constant bit rate (CBR) client data with a fixed number of idle blocks for transmission over a metro transport network (MTN)
US11838111B2 (en) 2021-06-30 2023-12-05 Microchip Technology Inc. System and method for performing rate adaptation of constant bit rate (CBR) client data with a variable number of idle blocks for transmission over a metro transport network (MTN)
US11736065B2 (en) 2021-10-07 2023-08-22 Microchip Technology Inc. Method and apparatus for conveying clock-related information from a timing device
US11799626B2 (en) 2021-11-23 2023-10-24 Microchip Technology Inc. Method and apparatus for carrying constant bit rate (CBR) client signals
US11924318B2 (en) 2022-02-24 2024-03-05 Marvell Israel (M.I.S.L) Ltd. Timestamping for multiple synchronization domains in a network device

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US4027263A (en) * 1975-04-24 1977-05-31 The United States Of America As Represented By The Secretary Of The Army Frequency generator
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US6259677B1 (en) * 1998-09-30 2001-07-10 Cisco Technology, Inc. Clock synchronization and dynamic jitter management for voice over IP and real-time data
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US7372875B2 (en) * 2002-09-30 2008-05-13 Lucent Technologies Inc. Systems and methods for synchronization in asynchronous transport networks
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GB2399263A (en) * 2003-03-07 2004-09-08 Zarlink Semiconductor Ltd Clock synchronisation over a packet network
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GB2421141A (en) * 2004-12-08 2006-06-14 Zarlink Semiconductor Ltd Adaptive clock recovery scheme
GB2443867A (en) * 2006-03-21 2008-05-21 Zarlink Semiconductor Ltd Timing source with packet size controller providing a distribution of packet sizes
GB2443868A (en) * 2006-03-21 2008-05-21 Zarlink Semiconductor Ltd Synchronising slave clocks in non-symmetric packet networks
GB2436421B (en) 2006-03-21 2011-09-07 Zarlink Semiconductor Ltd Timing source
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US8031747B2 (en) * 2009-04-29 2011-10-04 Juniper Networks, Inc. Apparatus and method of compensating for clock frequency and phase variations by processing packet delay values

Also Published As

Publication number Publication date
EP2254267A1 (de) 2010-11-24
CN101895381A (zh) 2010-11-24
US20100296524A1 (en) 2010-11-25
EP2254267B1 (de) 2011-12-07
GB0908883D0 (en) 2009-07-01
US8774227B2 (en) 2014-07-08
CN101895381B (zh) 2014-04-30

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