ATE524782T1 - Verfahren und system zur verbesserung der herstellbarkeit integrierter schaltungen - Google Patents

Verfahren und system zur verbesserung der herstellbarkeit integrierter schaltungen

Info

Publication number
ATE524782T1
ATE524782T1 AT04804495T AT04804495T ATE524782T1 AT E524782 T1 ATE524782 T1 AT E524782T1 AT 04804495 T AT04804495 T AT 04804495T AT 04804495 T AT04804495 T AT 04804495T AT E524782 T1 ATE524782 T1 AT E524782T1
Authority
AT
Austria
Prior art keywords
dfm
design
reserved
manufacturability
improving
Prior art date
Application number
AT04804495T
Other languages
English (en)
Inventor
Lionel Riviere-Cazeaux
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Application granted granted Critical
Publication of ATE524782T1 publication Critical patent/ATE524782T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AT04804495T 2004-11-30 2004-11-30 Verfahren und system zur verbesserung der herstellbarkeit integrierter schaltungen ATE524782T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2004/014918 WO2006058560A1 (en) 2004-11-30 2004-11-30 Method and system for improving the manufacurability of integrated circuits

Publications (1)

Publication Number Publication Date
ATE524782T1 true ATE524782T1 (de) 2011-09-15

Family

ID=34960152

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04804495T ATE524782T1 (de) 2004-11-30 2004-11-30 Verfahren und system zur verbesserung der herstellbarkeit integrierter schaltungen

Country Status (5)

Country Link
US (1) US7735029B2 (de)
EP (1) EP1820130B1 (de)
JP (1) JP4545798B2 (de)
AT (1) ATE524782T1 (de)
WO (1) WO2006058560A1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006129319A2 (en) * 2005-06-02 2006-12-07 Daro Semiconductors Ltd. Apparatus, method and computer-readable code for automated design of physical structures of integrated circuits
WO2008081227A1 (en) * 2007-01-05 2008-07-10 Freescale Semiconductor, Inc. Method and apparatus for designing an integrated circuit
US8863056B2 (en) * 2007-08-23 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated design-for-manufacturing platform
US7890909B2 (en) * 2008-01-02 2011-02-15 Oracle America, Inc. Automatic block composition tool for composing custom blocks having non-standard library cells in an integrated circuit design flow
US8434030B1 (en) 2012-01-05 2013-04-30 United Microelectronics Corporation Integrated circuit design and fabrication method by way of detecting and scoring hotspots
US8631375B2 (en) 2012-04-10 2014-01-14 International Business Machines Corporation Via selection in integrated circuit design
US8849440B2 (en) * 2012-05-31 2014-09-30 International Business Machines Corporation Manufacturing control based on a final design structure incorporating both layout and client-specific manufacturing information
US9026970B2 (en) 2013-03-07 2015-05-05 Freescale Semiconductor, Inc. Prioritized design for manufacturing virtualization with design rule checking filtering
US9081919B2 (en) * 2013-03-15 2015-07-14 Globalfoundries Singapore Pte. Ltd. Design-for-manufacturing—design-enabled-manufacturing (DFM-DEM) proactive integrated manufacturing flow
US9583488B2 (en) * 2013-12-30 2017-02-28 Texas Instruments Incorporated Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow
US9378326B2 (en) * 2014-09-09 2016-06-28 International Business Machines Corporation Critical region identification
WO2017151681A1 (en) 2016-02-29 2017-09-08 Synopsys, Inc. Creating and reusing customizable structured interconnects
DE102017127276A1 (de) * 2017-08-30 2019-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Standardzellen und abwandlungen davon innerhalb einer standardzellenbibliothek
US11074390B2 (en) * 2018-09-28 2021-07-27 Taiwan Semiconductor Manufacturing Company Ltd. Method of designing an integrated circuit and integrated circuit

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557533A (en) 1994-04-19 1996-09-17 Lsi Logic Corporation Cell placement alteration apparatus for integrated circuit chip physical design automation system
US5798937A (en) 1995-09-28 1998-08-25 Motorola, Inc. Method and apparatus for forming redundant vias between conductive layers of an integrated circuit
US6026224A (en) * 1996-11-20 2000-02-15 International Business Machines Corporation Redundant vias
US6490708B2 (en) 2001-03-19 2002-12-03 International Business Machines Corporation Method of integrated circuit design by selection of noise tolerant gates
JP2003031662A (ja) * 2001-07-16 2003-01-31 Mitsubishi Electric Corp 半導体集積回路の配線方法、半導体集積回路、及び配線方法をコンピュータに実行させるプログラム
US20050015740A1 (en) * 2003-07-18 2005-01-20 Mentor Graphics Corp. Design for manufacturability
US20050234684A1 (en) * 2004-04-19 2005-10-20 Mentor Graphics Corp. Design for manufacturability
JP4488727B2 (ja) * 2003-12-17 2010-06-23 株式会社東芝 設計レイアウト作成方法、設計レイアウト作成システム、マスクの製造方法、半導体装置の製造方法、及び設計レイアウト作成プログラム

Also Published As

Publication number Publication date
JP2008522259A (ja) 2008-06-26
WO2006058560A1 (en) 2006-06-08
US20080134106A1 (en) 2008-06-05
EP1820130A1 (de) 2007-08-22
JP4545798B2 (ja) 2010-09-15
EP1820130B1 (de) 2011-09-14
US7735029B2 (en) 2010-06-08

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Legal Events

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