ATE487982T1 - Erzeugung von paritätsprüfmatrizen - Google Patents

Erzeugung von paritätsprüfmatrizen

Info

Publication number
ATE487982T1
ATE487982T1 AT08776581T AT08776581T ATE487982T1 AT E487982 T1 ATE487982 T1 AT E487982T1 AT 08776581 T AT08776581 T AT 08776581T AT 08776581 T AT08776581 T AT 08776581T AT E487982 T1 ATE487982 T1 AT E487982T1
Authority
AT
Austria
Prior art keywords
matrix
row
vectors
generating
parity check
Prior art date
Application number
AT08776581T
Other languages
English (en)
Inventor
Paul Mcevoy
Jakub Wenus
Ted Hurley
Original Assignee
Technology From Ideas Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Technology From Ideas Ltd filed Critical Technology From Ideas Ltd
Application granted granted Critical
Publication of ATE487982T1 publication Critical patent/ATE487982T1/de

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148Structural properties of the code parity-check or generator matrix
    • H03M13/116Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033Theoretical methods to calculate these checking codes
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65Purpose and implementation aspects
    • H03M13/6522Intended application, e.g. transmission or communication standard
    • H03M13/6527IEEE 802.11 [WLAN]

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
AT08776581T 2007-07-02 2008-07-01 Erzeugung von paritätsprüfmatrizen ATE487982T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US92953307P 2007-07-02 2007-07-02
PCT/IE2008/000071 WO2009004601A2 (en) 2007-07-02 2008-07-01 Generation of parity-check matrices

Publications (1)

Publication Number Publication Date
ATE487982T1 true ATE487982T1 (de) 2010-11-15

Family

ID=40226613

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08776581T ATE487982T1 (de) 2007-07-02 2008-07-01 Erzeugung von paritätsprüfmatrizen

Country Status (7)

Country Link
US (1) US20090019333A1 (de)
EP (1) EP2176758B1 (de)
JP (1) JP2010532129A (de)
CN (1) CN101796488A (de)
AT (1) ATE487982T1 (de)
DE (1) DE602008003456D1 (de)
WO (1) WO2009004601A2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8423871B2 (en) * 2007-07-13 2013-04-16 Panasonic Corporation Transmitting device and transmitting method
US8219873B1 (en) 2008-10-20 2012-07-10 Link—A—Media Devices Corporation LDPC selective decoding scheduling using a cost function
US8397125B2 (en) * 2008-12-31 2013-03-12 Stmicroelectronics, Inc. Encoding apparatus, system, and method using low density parity check (LDPC) codes
US8196012B2 (en) * 2009-10-05 2012-06-05 The Hong Kong Polytechnic University Method and system for encoding and decoding low-density-parity-check (LDPC) codes
WO2011099281A1 (ja) * 2010-02-10 2011-08-18 パナソニック株式会社 送信装置、受信装置、送信方法及び受信方法
WO2011126578A1 (en) * 2010-04-09 2011-10-13 Link_A_Media Devices Corporation Implementation of ldpc selective decoding scheduling
WO2012039798A2 (en) * 2010-06-15 2012-03-29 California Institute Of Technology Rate-compatible protograph ldpc codes
US8918694B2 (en) 2011-02-28 2014-12-23 Clariphy Communications, Inc. Non-concatenated FEC codes for ultra-high speed optical transport networks
US10103751B2 (en) * 2011-02-28 2018-10-16 Inphi Corporation Non-concatenated FEC codes for ultra-high speed optical transport networks
US10063262B2 (en) * 2011-02-28 2018-08-28 Inphi Corporation Non-concatenated FEC codes for ultra-high speed optical transport networks
US8832520B2 (en) 2011-11-29 2014-09-09 California Institute Of Technology High order modulation protograph codes
US8914706B2 (en) 2011-12-30 2014-12-16 Streamscale, Inc. Using parity data for concurrent data authentication, correction, compression, and encryption
US8683296B2 (en) 2011-12-30 2014-03-25 Streamscale, Inc. Accelerated erasure coding system and method
US9100052B2 (en) * 2013-02-01 2015-08-04 Samsung Electronics Co., Ltd. QC-LDPC convolutional codes enabling low power trellis-based decoders
US9804925B1 (en) 2014-02-25 2017-10-31 Google Inc. Data reconstruction in distributed storage systems
US10367525B2 (en) * 2015-05-29 2019-07-30 National Instruments Corporation Incremental loop modification for LDPC encoding
CN106126187B (zh) * 2016-06-20 2019-02-22 符建 一种基于正交伪随机相位编码的光场并行计算装置及方法
US10110256B2 (en) * 2016-09-16 2018-10-23 Micron Technology, Inc. Apparatuses and methods for staircase code encoding and decoding for storage devices
CN106899310A (zh) * 2017-02-23 2017-06-27 重庆邮电大学 一种利用完备差集构造原模图qc‑ldpc码的方法
US10929226B1 (en) * 2017-11-21 2021-02-23 Pure Storage, Inc. Providing for increased flexibility for large scale parity
US11424766B1 (en) 2020-01-31 2022-08-23 Marvell Asia Pte Ltd. Method and device for energy-efficient decoders
CN112054809A (zh) * 2020-08-28 2020-12-08 杭州华澜微电子股份有限公司 改进的tpc纠错算法和装置
CN116800370A (zh) * 2022-03-14 2023-09-22 华为技术有限公司 一种网络编码方法以及装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6633856B2 (en) * 2001-06-15 2003-10-14 Flarion Technologies, Inc. Methods and apparatus for decoding LDPC codes
CA2536259C (en) 2002-08-20 2011-05-24 Flarion Technologies, Inc. Methods and apparatus for encoding ldpc codes
US7617441B2 (en) 2005-07-18 2009-11-10 Broadcom Corporation Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices
IE20050277A1 (en) * 2005-05-04 2006-11-29 Nat Univ Ireland Method and apparatus for generating error-correcting and error-detecting codes using zero-divisors and units in group rings
US7644335B2 (en) * 2005-06-10 2010-01-05 Qualcomm Incorporated In-place transformations with applications to encoding and decoding various classes of codes

Also Published As

Publication number Publication date
WO2009004601A3 (en) 2009-06-25
CN101796488A (zh) 2010-08-04
WO2009004601A9 (en) 2010-03-25
EP2176758B1 (de) 2010-11-10
EP2176758A2 (de) 2010-04-21
US20090019333A1 (en) 2009-01-15
DE602008003456D1 (de) 2010-12-23
JP2010532129A (ja) 2010-09-30
WO2009004601A2 (en) 2009-01-08

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