ATE477532T1 - Hardwarestapel mit einträgen mit einem datenteil und einem assoziierten zähler - Google Patents

Hardwarestapel mit einträgen mit einem datenteil und einem assoziierten zähler

Info

Publication number
ATE477532T1
ATE477532T1 AT05854568T AT05854568T ATE477532T1 AT E477532 T1 ATE477532 T1 AT E477532T1 AT 05854568 T AT05854568 T AT 05854568T AT 05854568 T AT05854568 T AT 05854568T AT E477532 T1 ATE477532 T1 AT E477532T1
Authority
AT
Austria
Prior art keywords
entries
data portion
entry
stack
new value
Prior art date
Application number
AT05854568T
Other languages
English (en)
Inventor
Michael Dwyer
Hong Jiang
Thomas Piazza
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE477532T1 publication Critical patent/ATE477532T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
    • G06F7/785—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using a RAM
AT05854568T 2004-12-15 2005-12-13 Hardwarestapel mit einträgen mit einem datenteil und einem assoziierten zähler ATE477532T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/012,688 US7434028B2 (en) 2004-12-15 2004-12-15 Hardware stack having entries with a data portion and associated counter
PCT/US2005/045887 WO2006066188A2 (en) 2004-12-15 2005-12-13 Hardware stack having entries with a data portion and associated counter

Publications (1)

Publication Number Publication Date
ATE477532T1 true ATE477532T1 (de) 2010-08-15

Family

ID=36390163

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05854568T ATE477532T1 (de) 2004-12-15 2005-12-13 Hardwarestapel mit einträgen mit einem datenteil und einem assoziierten zähler

Country Status (7)

Country Link
US (1) US7434028B2 (de)
EP (1) EP1839126B1 (de)
JP (1) JP4917045B2 (de)
CN (1) CN100498687C (de)
AT (1) ATE477532T1 (de)
DE (1) DE602005022938D1 (de)
WO (1) WO2006066188A2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8271959B2 (en) * 2008-04-27 2012-09-18 International Business Machines Corporation Detecting irregular performing code within computer programs
EP2328074A1 (de) * 2009-11-27 2011-06-01 STMicroelectronics S.r.l. Warteschlangeverwaltung
US8555259B2 (en) * 2009-12-04 2013-10-08 International Business Machines Corporation Verifying function performance based on predefined count ranges
GB2518912B (en) * 2014-01-17 2015-08-26 Imagination Tech Ltd Stack pointer value prediction
US20160179520A1 (en) * 2014-12-23 2016-06-23 Intel Corporation Method and apparatus for variably expanding between mask and vector registers

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4677546A (en) * 1984-08-17 1987-06-30 Signetics Guarded regions for controlling memory access
GB2177526B (en) * 1985-06-24 1990-02-14 Pixar Selective operation of processing elements in a single instruction, multiple data stream (simd)computer system
GB2178573B (en) 1985-07-10 1989-01-05 Nat Res Dev A data stack for data processors
JPH02112025A (ja) * 1988-10-21 1990-04-24 Hitachi Ltd 情報処理装置
US4988998A (en) * 1989-09-05 1991-01-29 Storage Technology Corporation Data compression system for successively applying at least two data compression methods to an input data stream
JPH07295812A (ja) * 1994-04-27 1995-11-10 Mitsubishi Electric Corp 条件分岐制御方法および装置
US6028962A (en) * 1996-05-10 2000-02-22 Apple Computer, Inc. System and method for variable encoding based on image content
US5862376A (en) * 1996-06-24 1999-01-19 Sun Microsystems, Inc. System and method for space and time efficient object locking
US5916305A (en) * 1996-11-05 1999-06-29 Shomiti Systems, Inc. Pattern recognition in data communications using predictive parsers
US6128654A (en) * 1997-02-14 2000-10-03 Advanced Micro Devices, Inc. Method and apparatus for transmitting multiple copies by replicating data identifiers
US5903769A (en) * 1997-03-31 1999-05-11 Sun Microsystems, Inc. Conditional vector processing
US6079008A (en) * 1998-04-03 2000-06-20 Patton Electronics Co. Multiple thread multiple data predictive coded parallel processing system and method
US6112288A (en) * 1998-05-19 2000-08-29 Paracel, Inc. Dynamic configurable system of parallel modules comprising chain of chips comprising parallel pipeline chain of processors with master controller feeding command and data

Also Published As

Publication number Publication date
DE602005022938D1 (de) 2010-09-23
CN100498687C (zh) 2009-06-10
US20060155924A1 (en) 2006-07-13
WO2006066188A2 (en) 2006-06-22
EP1839126B1 (de) 2010-08-11
EP1839126A2 (de) 2007-10-03
JP4917045B2 (ja) 2012-04-18
CN1804789A (zh) 2006-07-19
JP2008524721A (ja) 2008-07-10
WO2006066188A3 (en) 2006-10-05
US7434028B2 (en) 2008-10-07

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