ATE441148T1 - Ausgabeeinheit zum versetzen eines prozessors in eine allmähliche langsame betriebsart - Google Patents

Ausgabeeinheit zum versetzen eines prozessors in eine allmähliche langsame betriebsart

Info

Publication number
ATE441148T1
ATE441148T1 AT07727376T AT07727376T ATE441148T1 AT E441148 T1 ATE441148 T1 AT E441148T1 AT 07727376 T AT07727376 T AT 07727376T AT 07727376 T AT07727376 T AT 07727376T AT E441148 T1 ATE441148 T1 AT E441148T1
Authority
AT
Austria
Prior art keywords
processor
slow down
gradual
livelock
placing
Prior art date
Application number
AT07727376T
Other languages
English (en)
Inventor
Christopher Abernathy
Kurt Feiste
Norstrand Albert Van
Ronald Hall
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE441148T1 publication Critical patent/ATE441148T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Debugging And Monitoring (AREA)
  • Computer And Data Communications (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Power Sources (AREA)
AT07727376T 2006-04-14 2007-03-27 Ausgabeeinheit zum versetzen eines prozessors in eine allmähliche langsame betriebsart ATE441148T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/279,777 US7437539B2 (en) 2006-04-14 2006-04-14 Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline
PCT/EP2007/052903 WO2007118769A1 (en) 2006-04-14 2007-03-27 An issue unit for placing a processor into a gradual slow mode of operation

Publications (1)

Publication Number Publication Date
ATE441148T1 true ATE441148T1 (de) 2009-09-15

Family

ID=38179469

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07727376T ATE441148T1 (de) 2006-04-14 2007-03-27 Ausgabeeinheit zum versetzen eines prozessors in eine allmähliche langsame betriebsart

Country Status (7)

Country Link
US (2) US7437539B2 (de)
EP (1) EP2013712B1 (de)
JP (1) JP4608590B2 (de)
CN (1) CN101401066B (de)
AT (1) ATE441148T1 (de)
DE (1) DE602007002189D1 (de)
WO (1) WO2007118769A1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7748001B2 (en) * 2004-09-23 2010-06-29 Intel Corporation Multi-thread processing system for detecting and handling live-lock conditions by arbitrating livelock priority of logical processors based on a predertermined amount of time
US9626194B2 (en) 2004-09-23 2017-04-18 Intel Corporation Thread livelock unit
US7434033B2 (en) 2006-04-14 2008-10-07 International Business Machines Corporation Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline
US7437539B2 (en) 2006-04-14 2008-10-14 International Business Machines Corporation Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline
US8131980B2 (en) * 2006-09-11 2012-03-06 International Business Machines Corporation Structure for dynamic livelock resolution with variable delay memory access queue
US8171448B2 (en) * 2006-09-19 2012-05-01 International Business Machines Corporation Structure for a livelock resolution circuit
US7500035B2 (en) 2006-09-19 2009-03-03 International Business Machines Corporation Livelock resolution method
US20090182986A1 (en) * 2008-01-16 2009-07-16 Stephen Joseph Schwinn Processing Unit Incorporating Issue Rate-Based Predictive Thermal Management
US7953932B2 (en) * 2008-02-13 2011-05-31 International Business Machines Corporation System and method for avoiding deadlocks when performing storage updates in a multi-processor environment
US8006013B2 (en) * 2008-08-07 2011-08-23 International Business Machines Corporation Method and apparatus for preventing bus livelock due to excessive MMIO
US10102002B2 (en) * 2014-09-30 2018-10-16 International Business Machines Corporation Dynamic issue masks for processor hang prevention
US9690590B2 (en) * 2014-10-15 2017-06-27 Cavium, Inc. Flexible instruction execution in a processor pipeline
US9747109B2 (en) * 2014-10-15 2017-08-29 Cavium, Inc. Flexible instruction execution in a processor pipeline
GB2551524B (en) * 2016-06-20 2018-08-22 Imagination Tech Ltd Livelock detection in a hardware design using formal verification

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6785803B1 (en) * 1996-11-13 2004-08-31 Intel Corporation Processor including replay queue to break livelocks
US6697935B1 (en) 1997-10-23 2004-02-24 International Business Machines Corporation Method and apparatus for selecting thread switch events in a multithreaded processor
US6532574B1 (en) * 2000-08-17 2003-03-11 International Business Machines Corporation Post-manufacture signal delay adjustment to solve noise-induced delay variations
US6651158B2 (en) * 2001-06-22 2003-11-18 Intel Corporation Determination of approaching instruction starvation of threads based on a plurality of conditions
US6968431B2 (en) * 2001-11-15 2005-11-22 International Business Machines Corporation Method and apparatus for livelock prevention in a multiprocessor system
US20030115559A1 (en) * 2001-12-13 2003-06-19 International Business Machines Corporation Hardware validation through binary decision diagrams including functions and equalities
US7065596B2 (en) 2002-09-19 2006-06-20 Intel Corporation Method and apparatus to resolve instruction starvation
US20040093198A1 (en) * 2002-11-08 2004-05-13 Carbon Design Systems Hardware simulation with access restrictions
US7000047B2 (en) * 2003-04-23 2006-02-14 International Business Machines Corporation Mechanism for effectively handling livelocks in a simultaneous multithreading processor
US7748001B2 (en) * 2004-09-23 2010-06-29 Intel Corporation Multi-thread processing system for detecting and handling live-lock conditions by arbitrating livelock priority of logical processors based on a predertermined amount of time
US7434033B2 (en) 2006-04-14 2008-10-07 International Business Machines Corporation Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline
US7437539B2 (en) 2006-04-14 2008-10-14 International Business Machines Corporation Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline

Also Published As

Publication number Publication date
JP2009533738A (ja) 2009-09-17
EP2013712B1 (de) 2009-08-26
CN101401066B (zh) 2012-10-10
CN101401066A (zh) 2009-04-01
US8200946B2 (en) 2012-06-12
JP4608590B2 (ja) 2011-01-12
US20090006820A1 (en) 2009-01-01
US20070245129A1 (en) 2007-10-18
EP2013712A1 (de) 2009-01-14
DE602007002189D1 (de) 2009-10-08
WO2007118769A1 (en) 2007-10-25
US7437539B2 (en) 2008-10-14

Similar Documents

Publication Publication Date Title
ATE441148T1 (de) Ausgabeeinheit zum versetzen eines prozessors in eine allmähliche langsame betriebsart
TW200607262A (en) Exerted bolting mechanism of plug-and-play optical module
WO2014062588A3 (en) Incremental multi-word recognition
NO20084849L (no) Hoyhastighetsdiplaylukker for autostereoskopisk display
AR084437A1 (es) Metodo, sistema de computacion y medio de almacenamiento legible por computadora para insercion de sondeos mediante maquina virtual en segundo plano
GB2481565A (en) Screen capture
CL2007001505A1 (es) Metodo implementado por computador y sistema para evaluar el riesgo asociado a un cliente de organizacion financiera, donde el sistema comprende una interfaz grafica, una unidad de procesamiento acoplada a la interfaz grafica y una unidad de almacena
ES2535333T3 (es) Convertir una interrupción señalada por mensaje en una notificación de evento de adaptador de I/O
WO2008083093A3 (en) Detecting wake-up events for a chip based on an i/o power supply
EP1821201A3 (de) Grafikverarbeitungseinheit für kryptografische Verarbeitung
WO2012061090A3 (en) Conditional execution of regular expressions
TW200707178A (en) Reducing power by shutting down portions of a stacked register file
WO2008022331A3 (en) Multi-stage floating-point accumulator
MX2011013513A (es) Metodo para detectar un intento de ataque, medio de registro, y procesador de seguridad para dicho metodo.
BR112014014977A8 (pt) concentrador solar luminescente, e gerador fotovoltaico
EP2083352A3 (de) Verarbeitungseinheit
WO2008114315A1 (ja) Fault攻撃対策機能を搭載した組み込み装置
MX2009005970A (es) Analisis de control de calidad de datos de registro de pozo basado en un software.
TW200725632A (en) Memory diagnosing device
AR074198A1 (es) Metodo para procesar datos medidos
GB2425377B (en) External state cache for computer processor
BR112013002792A2 (pt) método e sistema para realizar operações em poços
EA200702043A1 (ru) Звукопоглощающая панель и способ ее производства
AR072599A1 (es) Optimizacion de la operacion de un procesador en un sistema de procesa-miento que incluye uno o varios filtros digitales
GB2442925A (en) Keyboard with extended connection

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties