MX2011013513A - Metodo para detectar un intento de ataque, medio de registro, y procesador de seguridad para dicho metodo. - Google Patents

Metodo para detectar un intento de ataque, medio de registro, y procesador de seguridad para dicho metodo.

Info

Publication number
MX2011013513A
MX2011013513A MX2011013513A MX2011013513A MX2011013513A MX 2011013513 A MX2011013513 A MX 2011013513A MX 2011013513 A MX2011013513 A MX 2011013513A MX 2011013513 A MX2011013513 A MX 2011013513A MX 2011013513 A MX2011013513 A MX 2011013513A
Authority
MX
Mexico
Prior art keywords
detecting
attack
security processor
attempted attack
recording medium
Prior art date
Application number
MX2011013513A
Other languages
English (en)
Inventor
Emmanuel Barau
Olivier Granet
Patrick Socquet
Original Assignee
Viaccess Sa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Viaccess Sa filed Critical Viaccess Sa
Publication of MX2011013513A publication Critical patent/MX2011013513A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/55—Detecting local intrusion or implementing counter-measures
    • G06F21/554—Detecting local intrusion or implementing counter-measures involving event detection and direct action
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Storage Device Security (AREA)
  • Debugging And Monitoring (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)

Abstract

La invención se refiere a un método para detectar un intento de ataque a un procesador de seguridad, la detección mediante un procesador de seguridad en sí mismo incluyendo: medir (50) una pluralidad de eventos separados que ocurren independientemente uno de otro en la ausencia de un intento de ataque; construir (52) el valor de al menos un indicador de ataque de acuerdo con al menos un índice de concomitancia entre al menos dos eventos medidos separados, el índice de concomitancia representa la proximidad en tiempo de los dos eventos medidos separados; y detectar (54) un intento de ataque si el valor del indicador de ataque excede un umbral predeterminado.
MX2011013513A 2009-06-29 2010-06-23 Metodo para detectar un intento de ataque, medio de registro, y procesador de seguridad para dicho metodo. MX2011013513A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0954431A FR2947361B1 (fr) 2009-06-29 2009-06-29 Procede de detection d'une tentative d'attaque, support d'enregistrement et processeur de securite pour ce procede
PCT/EP2010/058949 WO2011000756A1 (fr) 2009-06-29 2010-06-23 Procede de detection d'une tentative d'attaque, support d'enregistrement et processeur de securite pour ce procede

Publications (1)

Publication Number Publication Date
MX2011013513A true MX2011013513A (es) 2012-04-20

Family

ID=41508781

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2011013513A MX2011013513A (es) 2009-06-29 2010-06-23 Metodo para detectar un intento de ataque, medio de registro, y procesador de seguridad para dicho metodo.

Country Status (9)

Country Link
US (1) US9600667B2 (es)
EP (1) EP2449497A1 (es)
CN (1) CN102473209B (es)
BR (1) BRPI1013816A2 (es)
FR (1) FR2947361B1 (es)
MX (1) MX2011013513A (es)
RU (1) RU2568298C2 (es)
TW (1) TWI512519B (es)
WO (1) WO2011000756A1 (es)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9503785B2 (en) 2011-06-22 2016-11-22 Nagrastar, Llc Anti-splitter violation conditional key change
US9392319B2 (en) * 2013-03-15 2016-07-12 Nagrastar Llc Secure device profiling countermeasures
CN103678709B (zh) * 2013-12-30 2017-02-22 中国科学院自动化研究所 一种基于时序数据的推荐系统攻击检测方法
EP3270620A1 (en) * 2016-07-13 2018-01-17 Gemalto Sa Method and devices for managing a secure element
RU179302U1 (ru) * 2017-11-21 2018-05-07 Александра Владимировна Харжевская Устройство динамического контроля выполнения специальных вычислений
EP3663959B1 (en) 2018-12-06 2021-08-11 Mastercard International Incorporated An integrated circuit, method and computer program
US11848941B2 (en) * 2020-09-02 2023-12-19 Nxp B.V. Collection of diagnostic information in a device
CN115775419A (zh) * 2021-09-06 2023-03-10 华为技术有限公司 防护方法、智能锁及计算机可读存储介质
US20240031391A1 (en) * 2022-07-22 2024-01-25 Semperis Technologies Inc. (US) Attack path monitoring and risk mitigation in identity systems

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995028704A1 (fr) * 1994-04-18 1995-10-26 Matsushita Electric Industrial Co., Ltd. Procede et dispositif d'interdiction de la copie frauduleuse et l'inscription frauduleuse d'information sur un support d'enregistrement optique
US5533123A (en) * 1994-06-28 1996-07-02 National Semiconductor Corporation Programmable distributed personal security
US6075884A (en) * 1996-03-29 2000-06-13 Sarnoff Corporation Method and apparatus for training a neural network to learn and use fidelity metric as a control mechanism
GB2365153A (en) * 2000-01-28 2002-02-13 Simon William Moore Microprocessor resistant to power analysis with an alarm state
EP1447976B1 (en) 2003-02-12 2019-06-19 Irdeto B.V. Method of controlling descrambling of a plurality of program transport streams, receiver system and portable secure device
US7681235B2 (en) * 2003-05-19 2010-03-16 Radware Ltd. Dynamic network protection
EP1575293A1 (en) 2004-03-11 2005-09-14 Canal+ Technologies Dynamic smart card management
US8190731B2 (en) * 2004-06-15 2012-05-29 Alcatel Lucent Network statistics processing device
EP1612639A1 (en) * 2004-06-30 2006-01-04 ST Incard S.r.l. Method for detecting and reacting against possible attack to security enforcing operation performed by a cryptographic token or card
JP4899442B2 (ja) * 2005-11-21 2012-03-21 ソニー株式会社 情報処理装置、情報記録媒体製造装置、情報記録媒体、および方法、並びにコンピュータ・プログラム
FR2907930B1 (fr) 2006-10-27 2009-02-13 Viaccess Sa Procede de detection d'une utilisation anormale d'un processeur de securite.

Also Published As

Publication number Publication date
RU2012102988A (ru) 2013-08-20
US9600667B2 (en) 2017-03-21
TWI512519B (zh) 2015-12-11
RU2568298C2 (ru) 2015-11-20
WO2011000756A1 (fr) 2011-01-06
FR2947361B1 (fr) 2011-08-26
CN102473209A (zh) 2012-05-23
EP2449497A1 (fr) 2012-05-09
US20120096547A1 (en) 2012-04-19
TW201101090A (en) 2011-01-01
BRPI1013816A2 (pt) 2016-04-12
CN102473209B (zh) 2016-04-13
FR2947361A1 (fr) 2010-12-31

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