ATE424041T1 - Flip-chip verbindung mit verbesserter strombelastbarkeit - Google Patents

Flip-chip verbindung mit verbesserter strombelastbarkeit

Info

Publication number
ATE424041T1
ATE424041T1 AT04076664T AT04076664T ATE424041T1 AT E424041 T1 ATE424041 T1 AT E424041T1 AT 04076664 T AT04076664 T AT 04076664T AT 04076664 T AT04076664 T AT 04076664T AT E424041 T1 ATE424041 T1 AT E424041T1
Authority
AT
Austria
Prior art keywords
pad portion
electrical paths
solder bump
current
flip
Prior art date
Application number
AT04076664T
Other languages
English (en)
Inventor
Pankaj Mithal
William D Higdon
Mark W Gose
John M Dikeman
Original Assignee
Delphi Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Delphi Tech Inc filed Critical Delphi Tech Inc
Application granted granted Critical
Publication of ATE424041T1 publication Critical patent/ATE424041T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections

Landscapes

  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
AT04076664T 2003-06-13 2004-06-04 Flip-chip verbindung mit verbesserter strombelastbarkeit ATE424041T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/461,318 US6822327B1 (en) 2003-06-13 2003-06-13 Flip-chip interconnected with increased current-carrying capability

Publications (1)

Publication Number Publication Date
ATE424041T1 true ATE424041T1 (de) 2009-03-15

Family

ID=33299792

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04076664T ATE424041T1 (de) 2003-06-13 2004-06-04 Flip-chip verbindung mit verbesserter strombelastbarkeit

Country Status (4)

Country Link
US (2) US6822327B1 (de)
EP (1) EP1487016B1 (de)
AT (1) ATE424041T1 (de)
DE (1) DE602004019598D1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7501708B2 (en) * 2006-07-31 2009-03-10 International Business Machines Corporation Microelectronic device connection structure
US7911803B2 (en) * 2007-10-16 2011-03-22 International Business Machines Corporation Current distribution structure and method
US9214385B2 (en) 2009-12-17 2015-12-15 Globalfoundries Inc. Semiconductor device including passivation layer encapsulant
US8446006B2 (en) 2009-12-17 2013-05-21 International Business Machines Corporation Structures and methods to reduce maximum current density in a solder ball
US8492892B2 (en) 2010-12-08 2013-07-23 International Business Machines Corporation Solder bump connections
ES2799421T3 (es) 2011-02-25 2020-12-17 Senju Metal Industry Co Uso de una aleación de soldadura y una unión soldada de alta densidad de corriente
US8487447B2 (en) 2011-05-19 2013-07-16 International Business Machines Corporation Semiconductor structure having offset passivation to reduce electromigration
US9123544B2 (en) 2011-10-21 2015-09-01 Infineon Technologies Ag Semiconductor device and method
US9515035B2 (en) 2014-12-19 2016-12-06 International Business Machines Corporation Three-dimensional integrated circuit integration

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3902189A (en) * 1974-04-10 1975-08-26 Hunt Electronics Prefabricated article and methods of maintaining the orientation of parts being bonded thereto
JPH0274039A (ja) * 1988-09-09 1990-03-14 Texas Instr Japan Ltd 電子回路装置
US5438749A (en) * 1993-09-02 1995-08-08 Delco Electronics Corp. Method of making a flex circuit interconnect for a microprocessor emulator and a method of testing
US5491364A (en) * 1994-08-31 1996-02-13 Delco Electronics Corporation Reduced stress terminal pattern for integrated circuit devices and packages
US6064576A (en) * 1997-01-02 2000-05-16 Texas Instruments Incorporated Interposer having a cantilevered ball connection and being electrically connected to a printed circuit board
US6191481B1 (en) * 1998-12-18 2001-02-20 Philips Electronics North America Corp. Electromigration impeding composite metallization lines and methods for making the same
US6259608B1 (en) * 1999-04-05 2001-07-10 Delphi Technologies, Inc. Conductor pattern for surface mount devices and method therefor
JP3523189B2 (ja) * 2000-12-27 2004-04-26 株式会社東芝 半導体装置
US6674174B2 (en) * 2001-11-13 2004-01-06 Skyworks Solutions, Inc. Controlled impedance transmission lines in a redistribution layer
US6960828B2 (en) * 2002-06-25 2005-11-01 Unitive International Limited Electronic structures including conductive shunt layers
US20050116344A1 (en) * 2003-10-29 2005-06-02 Tessera, Inc. Microelectronic element having trace formed after bond layer
CN1635634A (zh) * 2003-12-30 2005-07-06 中芯国际集成电路制造(上海)有限公司 生产芯片级封装用焊垫的方法与装置

Also Published As

Publication number Publication date
EP1487016A2 (de) 2004-12-15
US6822327B1 (en) 2004-11-23
EP1487016A3 (de) 2006-10-04
US20050046024A1 (en) 2005-03-03
US20040251542A1 (en) 2004-12-16
DE602004019598D1 (de) 2009-04-09
EP1487016B1 (de) 2009-02-25

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Legal Events

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