ATE407393T1 - Verfahren, einrichtung und computerlesbares speichermedium zur erkennung und abwicklung eines fehlausgerichteten datenzugriffs - Google Patents

Verfahren, einrichtung und computerlesbares speichermedium zur erkennung und abwicklung eines fehlausgerichteten datenzugriffs

Info

Publication number
ATE407393T1
ATE407393T1 AT04796265T AT04796265T ATE407393T1 AT E407393 T1 ATE407393 T1 AT E407393T1 AT 04796265 T AT04796265 T AT 04796265T AT 04796265 T AT04796265 T AT 04796265T AT E407393 T1 ATE407393 T1 AT E407393T1
Authority
AT
Austria
Prior art keywords
data access
handling
detecting
misaliginated
computer
Prior art date
Application number
AT04796265T
Other languages
English (en)
Inventor
Harold Devor
Orna Etzion
Jian-Ping Chen
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE407393T1 publication Critical patent/ATE407393T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Indexing, Searching, Synchronizing, And The Amount Of Synchronization Travel Of Record Carriers (AREA)
  • Devices For Executing Special Programs (AREA)
AT04796265T 2003-11-26 2004-10-25 Verfahren, einrichtung und computerlesbares speichermedium zur erkennung und abwicklung eines fehlausgerichteten datenzugriffs ATE407393T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/721,879 US7493599B2 (en) 2003-11-26 2003-11-26 Device, system and method for detection and handling of misaligned data access

Publications (1)

Publication Number Publication Date
ATE407393T1 true ATE407393T1 (de) 2008-09-15

Family

ID=34591909

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04796265T ATE407393T1 (de) 2003-11-26 2004-10-25 Verfahren, einrichtung und computerlesbares speichermedium zur erkennung und abwicklung eines fehlausgerichteten datenzugriffs

Country Status (7)

Country Link
US (1) US7493599B2 (de)
EP (1) EP1687714B1 (de)
JP (2) JP4415019B2 (de)
CN (2) CN101593094B (de)
AT (1) ATE407393T1 (de)
DE (1) DE602004016375D1 (de)
WO (1) WO2005057407A1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7934012B2 (en) * 2004-03-12 2011-04-26 Sap Ag Automatic translation code generation
US8117404B2 (en) 2005-08-10 2012-02-14 Apple Inc. Misalignment predictor
US20080162522A1 (en) * 2006-12-29 2008-07-03 Guei-Yuan Lueh Methods and apparatuses for compaction and/or decompaction
US20080162879A1 (en) * 2006-12-29 2008-07-03 Hong Jiang Methods and apparatuses for aligning and/or executing instructions
JP5304443B2 (ja) * 2009-05-28 2013-10-02 富士通セミコンダクター株式会社 描画データ処理方法、図形描画システム、及び図形描画データ作成プログラム
GB2482710A (en) * 2010-08-12 2012-02-15 Advanced Risc Mach Ltd Enabling stack access alignment checking independently of other memory access alignment checking
BR112015029860B1 (pt) * 2013-06-27 2021-12-07 Intel Corporation Dispositivo de processamento, método e mídia legível por máquina
US9996329B2 (en) 2016-02-16 2018-06-12 Microsoft Technology Licensing, Llc Translating atomic read-modify-write accesses
CN108228235B (zh) * 2016-12-21 2020-11-13 龙芯中科技术有限公司 基于mips架构的数据操作处理方法和装置
CN111338997B (zh) * 2020-03-05 2021-07-20 苏州浪潮智能科技有限公司 一种arm服务器bios支持tcm通信的方法、装置、设备和介质
US20250060966A1 (en) * 2023-08-15 2025-02-20 Arm Limited Operating system pagesize compatibility workarounds

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5193180A (en) * 1991-06-21 1993-03-09 Pure Software Inc. System for modifying relocatable object code files to monitor accesses to dynamically allocated memory
US5265254A (en) * 1991-08-14 1993-11-23 Hewlett-Packard Company System of debugging software through use of code markers inserted into spaces in the source code during and after compilation
US5835747A (en) * 1996-01-26 1998-11-10 Advanced Micro Devices, Inc. Hierarchical scan logic for out-of-order load/store execution control
US5754812A (en) 1995-10-06 1998-05-19 Advanced Micro Devices, Inc. Out-of-order load/store execution control
US5907708A (en) * 1996-06-03 1999-05-25 Sun Microsystems, Inc. System and method for facilitating avoidance of an exception of a predetermined type in a digital computer system by providing fix-up code for an instruction in response to detection of an exception condition resulting from execution thereof
US6314558B1 (en) * 1996-08-27 2001-11-06 Compuware Corporation Byte code instrumentation
US6112297A (en) * 1998-02-10 2000-08-29 International Business Machines Corporation Apparatus and method for processing misaligned load instructions in a processor supporting out of order execution
US6327704B1 (en) * 1998-08-06 2001-12-04 Hewlett-Packard Company System, method, and product for multi-branch backpatching in a dynamic translator
US6289428B1 (en) 1999-08-03 2001-09-11 International Business Machines Corporation Superscaler processor and method for efficiently recovering from misaligned data addresses
US7107584B2 (en) * 2001-10-23 2006-09-12 Microsoft Corporation Data alignment between native and non-native shared data structures

Also Published As

Publication number Publication date
CN101593094B (zh) 2013-08-14
US7493599B2 (en) 2009-02-17
DE602004016375D1 (de) 2008-10-16
WO2005057407A1 (en) 2005-06-23
JP2007513412A (ja) 2007-05-24
CN100524203C (zh) 2009-08-05
JP2009282990A (ja) 2009-12-03
JP5404204B2 (ja) 2014-01-29
EP1687714B1 (de) 2008-09-03
EP1687714A1 (de) 2006-08-09
US20050114845A1 (en) 2005-05-26
CN101593094A (zh) 2009-12-02
JP4415019B2 (ja) 2010-02-17
CN1886727A (zh) 2006-12-27

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