ATE398804T1 - Vorrichtung und verfahren für taktlose datenrückgewinnung - Google Patents

Vorrichtung und verfahren für taktlose datenrückgewinnung

Info

Publication number
ATE398804T1
ATE398804T1 AT03724242T AT03724242T ATE398804T1 AT E398804 T1 ATE398804 T1 AT E398804T1 AT 03724242 T AT03724242 T AT 03724242T AT 03724242 T AT03724242 T AT 03724242T AT E398804 T1 ATE398804 T1 AT E398804T1
Authority
AT
Austria
Prior art keywords
data
tactless
data recovery
input rate
serial data
Prior art date
Application number
AT03724242T
Other languages
English (en)
Inventor
Seyed-Ali Hajimiri
Behnam Analui
Original Assignee
California Inst Of Techn
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by California Inst Of Techn filed Critical California Inst Of Techn
Application granted granted Critical
Publication of ATE398804T1 publication Critical patent/ATE398804T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Information Transfer Systems (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Control Of Eletrric Generators (AREA)
  • Gyroscopes (AREA)
  • Optical Integrated Circuits (AREA)
AT03724242T 2002-04-26 2003-04-25 Vorrichtung und verfahren für taktlose datenrückgewinnung ATE398804T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US37574802P 2002-04-26 2002-04-26

Publications (1)

Publication Number Publication Date
ATE398804T1 true ATE398804T1 (de) 2008-07-15

Family

ID=29270694

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03724242T ATE398804T1 (de) 2002-04-26 2003-04-25 Vorrichtung und verfahren für taktlose datenrückgewinnung

Country Status (7)

Country Link
US (2) US7274230B2 (de)
EP (1) EP1502180B1 (de)
JP (1) JP2005524142A (de)
AT (1) ATE398804T1 (de)
AU (1) AU2003231112A1 (de)
DE (1) DE60321675D1 (de)
WO (1) WO2003091871A2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7502601B2 (en) * 2003-12-22 2009-03-10 Black Sand Technologies, Inc. Power amplifier with digital power control and associated methods
US7522892B2 (en) * 2003-12-22 2009-04-21 Black Sand Technologies, Inc. Power amplifier with serial interface and associated methods
JP6038959B2 (ja) 2012-02-15 2016-12-07 ザ マスワークス， インクＴｈｅ Ｍａｔｈｗｏｒｋｓ， Ｉｎｃ． 状態機械モデルを記述する統合状態遷移表
WO2013123376A1 (en) * 2012-02-15 2013-08-22 The Mathworks, Inc. Unified state transition table describing a state machine model
US9235798B2 (en) 2012-07-18 2016-01-12 Micron Technology, Inc. Methods and systems for handling data received by a state machine engine
US9547333B2 (en) 2013-10-10 2017-01-17 General Electric Company System and method for synchronizing networked components

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4922141A (en) * 1986-10-07 1990-05-01 Western Digital Corporation Phase-locked loop delay line
GB8715597D0 (en) * 1987-07-02 1987-08-12 Indep Broadcasting Authority Digital synchronisation
US5220325A (en) * 1991-03-28 1993-06-15 At&T Bell Laboratories Hierarchical variable length decoder for digital video data
AU665072B2 (en) * 1992-05-21 1995-12-14 Alcatel N.V. TDM synchronous state machine
US5408200A (en) * 1992-12-18 1995-04-18 Storage Technology Corporation Intelligent phase detector
US5552733A (en) * 1993-01-19 1996-09-03 Credence Systems Corporation Precise and agile timing signal generator based on a retriggered oscillator
US5511181A (en) * 1993-04-26 1996-04-23 Apple Computer, Inc. Polycyclic timing system and apparatus for pipelined computer operation
JP3989532B2 (ja) 1993-09-30 2007-10-10 スカイワークス ソリューションズ，インコーポレイテッド ディジタルコードレス電話のための複数アンテナホームベース
US5640398A (en) * 1995-11-01 1997-06-17 Pmc-Sierra, Inc. State machine architecture for concurrent processing of multiplexed data streams
US5958077A (en) * 1995-12-27 1999-09-28 Nec Usa, Inc. Method for testing asynchronous circuits
FR2743248B1 (fr) * 1995-12-29 1998-03-20 Sgs Thomson Microelectronics Dispositif de demultiplexage d'informations codees selon une norme mpeg
WO1997031314A1 (en) * 1996-02-23 1997-08-28 Simtech Beheer B.V. Fault tolerant, self-diagnosing and fail-safe logic circuits and methods to design such circuits
US5787273A (en) * 1996-12-13 1998-07-28 Advanced Micro Devices, Inc. Multiple parallel identical finite state machines which share combinatorial logic
US6028903A (en) * 1997-03-31 2000-02-22 Sun Microsystems, Inc. Delay lock loop with transition recycling for clock recovery of NRZ run-length encoded serial data signals
DE19723539C2 (de) 1997-06-05 2000-07-20 Lucent Tech Network Sys Gmbh Digitales Schaltwerk
EP0987853A1 (de) * 1998-09-17 2000-03-22 STMicroelectronics S.r.l. Vollständig digitaler Phasenausrichter
US6043717A (en) * 1998-09-22 2000-03-28 Intel Corporation Signal synchronization and frequency synthesis system configurable as PLL or DLL
US6265996B1 (en) * 1999-04-29 2001-07-24 Cypress Semiconductor Corp. Low latency, low power deserializer
GB2395823B (en) * 2000-01-27 2004-08-25 Automatic Parallel Designs Ltd Method and apparatus for binary encoding logic circuits
TW465194B (en) * 2000-10-17 2001-11-21 Mediatek Inc Data dividing circuit and method for diving data
CA2338458A1 (en) * 2001-02-27 2001-08-14 Ioan Dancea Method and vlsi circuits allowing to change dynamically the logical behaviour
US7042971B1 (en) * 2001-06-12 2006-05-09 Lsi Logic Corporation Delay-locked loop with built-in self-test of phase margin
US20030052719A1 (en) * 2001-09-20 2003-03-20 Na Kwang Jin Digital delay line and delay locked loop using the digital delay line
US20030081709A1 (en) * 2001-10-30 2003-05-01 Sun Microsystems, Inc. Single-ended IO with dynamic synchronous deskewing architecture
US7131077B1 (en) * 2003-03-28 2006-10-31 Xilinx, Inc Using an embedded processor to implement a finite state machine

Also Published As

Publication number Publication date
US20030202622A1 (en) 2003-10-30
EP1502180B1 (de) 2008-06-18
JP2005524142A (ja) 2005-08-11
AU2003231112A1 (en) 2003-11-10
DE60321675D1 (de) 2008-07-31
EP1502180A2 (de) 2005-02-02
US7274230B2 (en) 2007-09-25
US20080080653A1 (en) 2008-04-03
WO2003091871A3 (en) 2004-02-05
WO2003091871A2 (en) 2003-11-06
US8295423B2 (en) 2012-10-23

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Legal Events

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