ATE392664T1 - INTELLIGENT DATA BUS INTERFACE USING MULTITOR MEMORY - Google Patents

INTELLIGENT DATA BUS INTERFACE USING MULTITOR MEMORY

Info

Publication number
ATE392664T1
ATE392664T1 AT98950672T AT98950672T ATE392664T1 AT E392664 T1 ATE392664 T1 AT E392664T1 AT 98950672 T AT98950672 T AT 98950672T AT 98950672 T AT98950672 T AT 98950672T AT E392664 T1 ATE392664 T1 AT E392664T1
Authority
AT
Austria
Prior art keywords
data
bus interface
memory
processor
triple
Prior art date
Application number
AT98950672T
Other languages
German (de)
Inventor
Volker Lehrstuhl Lindenstruth
Original Assignee
Icore Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Icore Technologies Inc filed Critical Icore Technologies Inc
Application granted granted Critical
Publication of ATE392664T1 publication Critical patent/ATE392664T1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/82—Protecting input, output or interconnection devices
    • G06F21/85—Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/03—Indexing scheme relating to G06F21/50, monitoring users, programs or devices to maintain the integrity of platforms
    • G06F2221/034—Test or assess a computer or a system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2129—Authenticate client device independently of the user
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2153—Using hardware token as a secondary aspect

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Bus Control (AREA)
  • Storage Device Security (AREA)
  • Communication Control (AREA)

Abstract

An intelligent data bus interface using a triple-port memory having three independent data ports that provide simultaneous access to the data stored in the memory to two bi-directional data buses and to a data processor. The two data buses and the processor are coupled to separate data ports and each is able to independently access data in the triple-port memory at the full data rate of each. Because of the use of the triple-port memory, no data copying or moving is required in order to provide access to the data to the processor or the data buses. The intelligent data bus interface is particularly suitable for handling encryption/decryption, network protocol and PCI/SCI bridging at full speed at any of its ports without burdening a host processor.
AT98950672T 1997-09-23 1998-09-22 INTELLIGENT DATA BUS INTERFACE USING MULTITOR MEMORY ATE392664T1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/935,921 US6067595A (en) 1997-09-23 1997-09-23 Method and apparatus for enabling high-performance intelligent I/O subsystems using multi-port memories

Publications (1)

Publication Number Publication Date
ATE392664T1 true ATE392664T1 (en) 2008-05-15

Family

ID=25467893

Family Applications (1)

Application Number Title Priority Date Filing Date
AT98950672T ATE392664T1 (en) 1997-09-23 1998-09-22 INTELLIGENT DATA BUS INTERFACE USING MULTITOR MEMORY

Country Status (9)

Country Link
US (1) US6067595A (en)
EP (1) EP1047994B1 (en)
JP (1) JP2001517844A (en)
KR (1) KR20010015608A (en)
CN (1) CN1154934C (en)
AT (1) ATE392664T1 (en)
AU (1) AU9665798A (en)
DE (1) DE69839374T2 (en)
WO (1) WO1999016200A2 (en)

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EP1047994A4 (en) 2002-07-24
CN1279785A (en) 2001-01-10
KR20010015608A (en) 2001-02-26
CN1154934C (en) 2004-06-23
EP1047994A2 (en) 2000-11-02
DE69839374T2 (en) 2009-06-25
JP2001517844A (en) 2001-10-09
DE69839374D1 (en) 2008-05-29
WO1999016200A3 (en) 2000-07-27
US6067595A (en) 2000-05-23
WO1999016200A2 (en) 1999-04-01
EP1047994B1 (en) 2008-04-16
AU9665798A (en) 1999-04-12

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