ATE386300T1 - Architektur eines kommunikationsknoten in einem global asynchronen netzwerk on-chip-system - Google Patents

Architektur eines kommunikationsknoten in einem global asynchronen netzwerk on-chip-system

Info

Publication number
ATE386300T1
ATE386300T1 AT06110721T AT06110721T ATE386300T1 AT E386300 T1 ATE386300 T1 AT E386300T1 AT 06110721 T AT06110721 T AT 06110721T AT 06110721 T AT06110721 T AT 06110721T AT E386300 T1 ATE386300 T1 AT E386300T1
Authority
AT
Austria
Prior art keywords
architecture
communication node
chip system
asynchronous network
hierarchy
Prior art date
Application number
AT06110721T
Other languages
English (en)
Inventor
Edith Beigne
Pascal Vivet
Marc Renaudin
Jerome Quartana
Original Assignee
Commissariat Energie Atomique
Centre Nat Rech Scient
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique, Centre Nat Rech Scient filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of ATE386300T1 publication Critical patent/ATE386300T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)
AT06110721T 2005-03-08 2006-03-06 Architektur eines kommunikationsknoten in einem global asynchronen netzwerk on-chip-system ATE386300T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0550611A FR2883117B1 (fr) 2005-03-08 2005-03-08 Architecture de noeud de communication dans un systeme de reseau sur puce globalement asynchrone.

Publications (1)

Publication Number Publication Date
ATE386300T1 true ATE386300T1 (de) 2008-03-15

Family

ID=34954683

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06110721T ATE386300T1 (de) 2005-03-08 2006-03-06 Architektur eines kommunikationsknoten in einem global asynchronen netzwerk on-chip-system

Country Status (6)

Country Link
US (1) US7940666B2 (de)
EP (1) EP1701274B8 (de)
JP (1) JP4808514B2 (de)
AT (1) ATE386300T1 (de)
DE (1) DE602006000516T2 (de)
FR (1) FR2883117B1 (de)

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JP5287718B2 (ja) * 2007-06-08 2013-09-11 日本電気株式会社 半導体集積回路及びフィルタ制御方法
US7783823B2 (en) * 2007-07-31 2010-08-24 Hewlett-Packard Development Company, L.P. Hardware device data buffer
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FR2925187B1 (fr) * 2007-12-14 2011-04-08 Commissariat Energie Atomique Systeme comportant une pluralite d'unites de traitement permettant d'executer des taches en parallele,en mixant le mode d'execution de type controle et le mode d'execution de type flot de donnees
US8473667B2 (en) * 2008-01-11 2013-06-25 International Business Machines Corporation Network on chip that maintains cache coherency with invalidation messages
US8490110B2 (en) 2008-02-15 2013-07-16 International Business Machines Corporation Network on chip with a low latency, high bandwidth application messaging interconnect
WO2009133918A1 (ja) 2008-04-30 2009-11-05 日本電気株式会社 ルータ、そのルータを有する情報処理装置及びパケットのルーティング方法
US8423715B2 (en) 2008-05-01 2013-04-16 International Business Machines Corporation Memory management among levels of cache in a memory hierarchy
US8494833B2 (en) 2008-05-09 2013-07-23 International Business Machines Corporation Emulating a computer run time environment
US8214845B2 (en) * 2008-05-09 2012-07-03 International Business Machines Corporation Context switching in a network on chip by thread saving and restoring pointers to memory arrays containing valid message data
US8392664B2 (en) 2008-05-09 2013-03-05 International Business Machines Corporation Network on chip
US8040799B2 (en) * 2008-05-15 2011-10-18 International Business Machines Corporation Network on chip with minimum guaranteed bandwidth for virtual communications channels
US8230179B2 (en) * 2008-05-15 2012-07-24 International Business Machines Corporation Administering non-cacheable memory load instructions
US8438578B2 (en) 2008-06-09 2013-05-07 International Business Machines Corporation Network on chip with an I/O accelerator
US8131975B1 (en) 2008-07-07 2012-03-06 Ovics Matrix processor initialization systems and methods
US8327114B1 (en) 2008-07-07 2012-12-04 Ovics Matrix processor proxy systems and methods
US8145880B1 (en) 2008-07-07 2012-03-27 Ovics Matrix processor data switch routing systems and methods
US7958341B1 (en) 2008-07-07 2011-06-07 Ovics Processing stream instruction in IC of mesh connected matrix of processors containing pipeline coupled switch transferring messages over consecutive cycles from one link to another link or memory
US8195884B2 (en) 2008-09-18 2012-06-05 International Business Machines Corporation Network on chip with caching restrictions for pages of computer memory
DE102008049620A1 (de) * 2008-09-30 2010-04-01 Bayerische Motoren Werke Aktiengesellschaft Kommunikationssystem
US8108908B2 (en) 2008-10-22 2012-01-31 International Business Machines Corporation Security methodology to prevent user from compromising throughput in a highly threaded network on a chip processor
JP5307525B2 (ja) * 2008-12-03 2013-10-02 キヤノン株式会社 データ処理装置及びその制御方法
US8509078B2 (en) * 2009-02-12 2013-08-13 Microsoft Corporation Bufferless routing in on-chip interconnection networks
DE102009002007B3 (de) * 2009-03-31 2010-07-01 Robert Bosch Gmbh Netzwerkcontroller in einem Netzwerk, Netzwerk und Routingverfahren für Nachrichten in einem Netzwerk
FR2948840B1 (fr) 2009-07-29 2011-09-16 Kalray Reseau de communication sur puce avec garantie de service
FR2949879B1 (fr) 2009-09-04 2014-07-18 Kalray Noeuds d'entree/sortie d'un reseau sur puce torique.
FR2951868B1 (fr) 2009-10-28 2012-04-06 Kalray Briques de construction d'un reseau sur puce
FR2957176B1 (fr) * 2010-03-02 2012-04-06 Commissariat Energie Atomique Puce electronique et circuit integre comportant une telle puce electronique
CN102523764B (zh) 2010-09-03 2015-02-18 松下电器产业株式会社 中继装置
JP2012146201A (ja) * 2011-01-13 2012-08-02 Toshiba Corp オンチップルータ及びそれを用いたマルチコアシステム
JP2012186539A (ja) * 2011-03-03 2012-09-27 Renesas Electronics Corp ルータ装置、ルータ装置の制御方法
US9537679B2 (en) * 2011-03-16 2017-01-03 The Trustees Of Columbia University In The City Of New York Bi-modal arbitration nodes for a low-latency adaptive asynchronous interconnection network and methods for using the same
CN102158403B (zh) * 2011-03-24 2014-03-05 山东大学 一种适用于片上网络的高效数据流传输通信系统及其工作方法
WO2013014851A1 (ja) * 2011-07-22 2013-01-31 パナソニック株式会社 中継装置
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Also Published As

Publication number Publication date
FR2883117A1 (fr) 2006-09-15
FR2883117B1 (fr) 2007-04-27
DE602006000516D1 (de) 2008-03-27
JP2006254450A (ja) 2006-09-21
EP1701274A1 (de) 2006-09-13
JP4808514B2 (ja) 2011-11-02
DE602006000516T2 (de) 2009-04-02
EP1701274B1 (de) 2008-02-13
EP1701274B8 (de) 2008-07-16
US20060203825A1 (en) 2006-09-14
US7940666B2 (en) 2011-05-10

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