ATE384296T1 - Datenverarbeitungssystem und verfahren zur verbindungs-arbitrierung - Google Patents

Datenverarbeitungssystem und verfahren zur verbindungs-arbitrierung

Info

Publication number
ATE384296T1
ATE384296T1 AT05746720T AT05746720T ATE384296T1 AT E384296 T1 ATE384296 T1 AT E384296T1 AT 05746720 T AT05746720 T AT 05746720T AT 05746720 T AT05746720 T AT 05746720T AT E384296 T1 ATE384296 T1 AT E384296T1
Authority
AT
Austria
Prior art keywords
interconnect
memory
processing units
data
arbitration
Prior art date
Application number
AT05746720T
Other languages
English (en)
Inventor
Milind Kulkarni
Bijo Thomas
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE384296T1 publication Critical patent/ATE384296T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Power Sources (AREA)
  • Multi Processors (AREA)
  • Communication Control (AREA)
AT05746720T 2004-06-21 2005-06-14 Datenverarbeitungssystem und verfahren zur verbindungs-arbitrierung ATE384296T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04102834 2004-06-21

Publications (1)

Publication Number Publication Date
ATE384296T1 true ATE384296T1 (de) 2008-02-15

Family

ID=34981920

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05746720T ATE384296T1 (de) 2004-06-21 2005-06-14 Datenverarbeitungssystem und verfahren zur verbindungs-arbitrierung

Country Status (7)

Country Link
US (1) US7698514B2 (de)
EP (1) EP1761855B1 (de)
JP (1) JP2008503823A (de)
CN (1) CN100541461C (de)
AT (1) ATE384296T1 (de)
DE (1) DE602005004408T2 (de)
WO (1) WO2006000944A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006082551A1 (en) * 2005-02-07 2006-08-10 Nxp B.V. Data processing system and method of cache replacement
JP5481329B2 (ja) 2010-09-13 2014-04-23 株式会社東芝 半導体集積回路、インターコネクト、及び制御プログラム
US10216671B2 (en) * 2017-02-27 2019-02-26 Qualcomm Incorporated Power aware arbitration for bus access

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5345562A (en) * 1992-02-12 1994-09-06 Industrial Technology Research Institute Data bus arbitration for split transaction computer bus
US5669003A (en) * 1994-12-23 1997-09-16 Intel Corporation Method of monitoring system bus traffic by a CPU operating with reduced power
US5632013A (en) * 1995-06-07 1997-05-20 International Business Machines Corporation Memory and system for recovery/restoration of data using a memory controller
US6163857A (en) * 1998-04-30 2000-12-19 International Business Machines Corporation Computer system UE recovery logic
CN1483166A (zh) * 2000-11-07 2004-03-17 英特尔公司 采用动态总线倒置来降低同步转换输出噪音的方法和装置
US20030120878A1 (en) * 2001-12-21 2003-06-26 Andreassen Jens Kloster Resource sharing using a locking mechanism in a multiprocessor environment
DE60210438T2 (de) 2002-07-10 2006-10-12 Stmicroelectronics S.R.L., Agrate Brianza Verfahren und Gerät zur Verminderung der Busschaltaktivität und Rechnerprogrammprodukt
DE60209690D1 (de) 2002-09-25 2006-05-04 St Microelectronics Srl Verfahren und Gerät, um ein digitales Signal über einem Rechnerbus zu übertragen und Rechnerprogrammprodukt dafür

Also Published As

Publication number Publication date
DE602005004408D1 (de) 2008-03-06
CN100541461C (zh) 2009-09-16
US20090172226A1 (en) 2009-07-02
EP1761855B1 (de) 2008-01-16
JP2008503823A (ja) 2008-02-07
WO2006000944A1 (en) 2006-01-05
US7698514B2 (en) 2010-04-13
EP1761855A1 (de) 2007-03-14
CN101002185A (zh) 2007-07-18
DE602005004408T2 (de) 2008-05-21

Similar Documents

Publication Publication Date Title
US9965392B2 (en) Managing coherent memory between an accelerated processing device and a central processing unit
TWI396088B (zh) 執行原子信號操作之方法及裝置
US9798686B2 (en) Slave side bus arbitration
US20080126643A1 (en) Semiconductor circuit
ATE259081T1 (de) Mehrprozessorsystem prüfungsschaltung
DE602007009290D1 (de) Verfahren zum aufrechterhalten eines usb-aktivzustands ohne datentransfer
WO2011068614A3 (en) Controller device coprocessor architecture
DE602005014540D1 (de) Verfahren und vorrichtungen zum task-management in einem mehrprozessorsystem
TW200630799A (en) Memory system and method having uni-directional data buses
WO2004066059A3 (en) Microprocessor systems
TW200710674A (en) Processor, data processing system, and method for initializing a memory block
WO2006078002A3 (en) Method and apparatus for providing synchronization of shared data
RU2013146508A (ru) СПОСОБ И УСТРОЙСТВО ДЛЯ ОБЕСПЕЧЕНИЯ ПОТОКОВ НА ОСНОВЕ ИДЕНТИФИКАТОРА ЧЕРЕЗ ШИНУ PCI Express
WO2007127489A3 (en) System and method for target device access arbitration using queuing devices
US20150193358A1 (en) Prioritized Memory Reads
US8943449B1 (en) Method and apparatus of enabling direct memory access into a target system memory modeled in dual abstractions while ensuring coherency
EP1701267A3 (de) Adress-Snoop-Verfahren und Mehrprozessorsystem
ATE384296T1 (de) Datenverarbeitungssystem und verfahren zur verbindungs-arbitrierung
ATE463011T1 (de) Hierarchische prozessorarchitektur zur videoverarbeitung
US7765349B1 (en) Apparatus and method for arbitrating heterogeneous agents in on-chip busses
TW200727139A (en) Computer system and memory bridge thereof
ATE363690T1 (de) Methode und vorrichtung welche einen externen zugriff zu internen konfigurationsregistern erlauben
TW200715122A (en) Arbitration scheme for shared memory device
TW200728985A (en) Reduction of snoop accesses
JP2010257134A5 (ja) 半導体データ処理装置

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties