ATE377879T1 - SPREAD BAND CLOCK TOLERANT RECEIVER - Google Patents

SPREAD BAND CLOCK TOLERANT RECEIVER

Info

Publication number
ATE377879T1
ATE377879T1 AT02796022T AT02796022T ATE377879T1 AT E377879 T1 ATE377879 T1 AT E377879T1 AT 02796022 T AT02796022 T AT 02796022T AT 02796022 T AT02796022 T AT 02796022T AT E377879 T1 ATE377879 T1 AT E377879T1
Authority
AT
Austria
Prior art keywords
data signal
signal
clock
spread band
band clock
Prior art date
Application number
AT02796022T
Other languages
German (de)
Inventor
Harry Skinner
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE377879T1 publication Critical patent/ATE377879T1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B15/00—Suppression or limitation of noise or interference
    • H04B15/02—Reducing interference from electric apparatus by means located at or near the interfering apparatus
    • H04B15/04—Reducing interference from electric apparatus by means located at or near the interfering apparatus the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2215/00—Reducing interference at the transmission system level
    • H04B2215/064—Reduction of clock or synthesizer reference frequency harmonics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2215/00—Reducing interference at the transmission system level
    • H04B2215/064—Reduction of clock or synthesizer reference frequency harmonics
    • H04B2215/067—Reduction of clock or synthesizer reference frequency harmonics by modulation dispersion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0066—Detection of the synchronisation error by features other than the received signal transition detection of error based on transmission code rule

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Measuring Pulse, Heart Rate, Blood Pressure Or Blood Flow (AREA)
  • Eye Examination Apparatus (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Cleaning And De-Greasing Of Metallic Materials By Chemical Methods (AREA)
  • Burglar Alarm Systems (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)

Abstract

In some embodiments, the invention includes a system having a clock recovery circuitry to receive a data signal and a reference clock signal and in response thereto to produce an in phase clock signal which is in phase with the data signal and mirrors frequency changes in the data signal, wherein the data signal has embedded clock information and a varying frequency. The system also includes a receiving gate to receive the data signal and the in phase clock signal and to gate the data signal to produce a gated data signal in response to the in phase clock signal. Other embodiments are described and claimed.
AT02796022T 2001-12-26 2002-12-19 SPREAD BAND CLOCK TOLERANT RECEIVER ATE377879T1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/034,398 US6937679B2 (en) 2001-12-26 2001-12-26 Spread spectrum clocking tolerant receivers

Publications (1)

Publication Number Publication Date
ATE377879T1 true ATE377879T1 (en) 2007-11-15

Family

ID=21876139

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02796022T ATE377879T1 (en) 2001-12-26 2002-12-19 SPREAD BAND CLOCK TOLERANT RECEIVER

Country Status (8)

Country Link
US (1) US6937679B2 (en)
EP (1) EP1459473B1 (en)
KR (1) KR100693985B1 (en)
CN (1) CN100334828C (en)
AT (1) ATE377879T1 (en)
AU (1) AU2002360740A1 (en)
DE (1) DE60223403T2 (en)
WO (1) WO2003058874A1 (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7209525B2 (en) * 2002-11-18 2007-04-24 Agere Systems Inc. Clock and data recovery with extended integration cycles
US7315595B2 (en) * 2003-12-22 2008-01-01 International Business Machines Corporation Methods and arrangements for link power reduction
US7738617B1 (en) 2004-09-29 2010-06-15 Pmc-Sierra, Inc. Clock and data recovery locking technique for large frequency offsets
US7558357B1 (en) 2004-10-26 2009-07-07 Pmc-Sierra, Inc. Systems and methods for reducing frequency-offset induced jitter
US7664204B1 (en) * 2005-03-10 2010-02-16 Marvell International Ltd. Adaptive timing using clock recovery
JP2007151099A (en) * 2005-10-28 2007-06-14 Seiko Epson Corp Wireless communication device
US8483703B2 (en) * 2005-11-14 2013-07-09 Motorola Solutions, Inc. Method and apparatus for locating a transceiver
US20070159744A1 (en) * 2006-01-06 2007-07-12 Ramen Dutta High voltage pin for low voltage process
US8705680B2 (en) 2006-06-29 2014-04-22 Nippon Telegraph And Telephone Corporation CDR circuit
JP2008011173A (en) * 2006-06-29 2008-01-17 Nippon Telegr & Teleph Corp <Ntt> Cdr circuit
US8311176B2 (en) 2006-10-06 2012-11-13 Rambus Inc. Clock and data recovery employing piece-wise estimation on the derivative of the frequency
GB2453732B (en) * 2007-10-16 2012-03-07 Virtensys Ltd Data switch
US8169369B2 (en) * 2008-12-15 2012-05-01 Motorola Solutions, Inc. Method and device for generating a location signal
KR101642833B1 (en) * 2010-02-05 2016-07-26 삼성전자주식회사 clock embedded interface method, transceiver and display device using the method
JP6421515B2 (en) * 2014-09-25 2018-11-14 富士通株式会社 Signal reproduction circuit and signal reproduction method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU4971096A (en) 1995-03-08 1996-09-23 Intel Corporation Frequency modulated clock for reduced radiation
JP3403849B2 (en) 1995-03-17 2003-05-06 富士通株式会社 Clock phase detection circuit and clock recovery circuit provided in receiving section of multiplex radio apparatus
US5696800A (en) 1995-03-22 1997-12-09 Intel Corporation Dual tracking differential manchester decoder and clock recovery circuit
JP3120833B2 (en) 1997-05-20 2000-12-25 日本電気株式会社 Burst signal demodulator
US6236697B1 (en) * 1998-05-28 2001-05-22 Integrated Device Technology, Inc. Clock recovery for multiple frequency input data
US6347128B1 (en) * 1998-07-20 2002-02-12 Lucent Technologies Inc. Self-aligned clock recovery circuit with proportional phase detector

Also Published As

Publication number Publication date
US20030118137A1 (en) 2003-06-26
DE60223403T2 (en) 2008-09-04
EP1459473A1 (en) 2004-09-22
KR100693985B1 (en) 2007-03-13
CN1608360A (en) 2005-04-20
CN100334828C (en) 2007-08-29
WO2003058874A1 (en) 2003-07-17
US6937679B2 (en) 2005-08-30
EP1459473B1 (en) 2007-11-07
KR20040074103A (en) 2004-08-21
AU2002360740A1 (en) 2003-07-24
DE60223403D1 (en) 2007-12-20

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties