ATE373263T1 - Multiplizierer mit nachschlagetabellen - Google Patents

Multiplizierer mit nachschlagetabellen

Info

Publication number
ATE373263T1
ATE373263T1 AT03769792T AT03769792T ATE373263T1 AT E373263 T1 ATE373263 T1 AT E373263T1 AT 03769792 T AT03769792 T AT 03769792T AT 03769792 T AT03769792 T AT 03769792T AT E373263 T1 ATE373263 T1 AT E373263T1
Authority
AT
Austria
Prior art keywords
words
word
result
fragmented
bits
Prior art date
Application number
AT03769792T
Other languages
English (en)
Inventor
Gerardus Hubert
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE373263T1 publication Critical patent/ATE373263T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49931—Modulo N reduction of final result
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5318—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with column wise addition of partial products, e.g. using Wallace tree, Dadda counters

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Steroid Compounds (AREA)
AT03769792T 2002-11-29 2003-11-11 Multiplizierer mit nachschlagetabellen ATE373263T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GBGB0227793.7A GB0227793D0 (en) 2002-11-29 2002-11-29 Multiplier with look up tables

Publications (1)

Publication Number Publication Date
ATE373263T1 true ATE373263T1 (de) 2007-09-15

Family

ID=9948709

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03769792T ATE373263T1 (de) 2002-11-29 2003-11-11 Multiplizierer mit nachschlagetabellen

Country Status (9)

Country Link
US (1) US7536429B2 (de)
EP (1) EP1573510B1 (de)
JP (1) JP2006508464A (de)
CN (1) CN1717653B (de)
AT (1) ATE373263T1 (de)
AU (1) AU2003278492A1 (de)
DE (1) DE60316342T2 (de)
GB (1) GB0227793D0 (de)
WO (1) WO2004051456A2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7526518B2 (en) * 2004-10-13 2009-04-28 Cisco Technology, Inc. Galois field multiplication system and method
WO2008030916A2 (en) * 2006-09-06 2008-03-13 The Research Foundation Of State University Of New York A parameterized vlsi architecture and method for binary multipliers
US8346839B2 (en) * 2007-03-30 2013-01-01 Intel Corporation Efficient advanced encryption standard (AES) datapath using hybrid rijndael S-box
US8572406B2 (en) * 2010-03-31 2013-10-29 Inside Contactless Integrated circuit protected against horizontal side channel analysis
US8457919B2 (en) * 2010-03-31 2013-06-04 Inside Secure Process for testing the resistance of an integrated circuit to a side channel analysis
CN102508632B (zh) * 2011-09-30 2014-10-29 飞天诚信科技股份有限公司 一种在嵌入式系统中实现乘法运算的方法和装置
CN102411489B (zh) * 2011-10-18 2014-06-04 飞天诚信科技股份有限公司 一种嵌入式系统中的数据处理方法及装置
JP7183079B2 (ja) * 2019-03-08 2022-12-05 株式会社東芝 半導体装置
TWI784406B (zh) * 2020-06-04 2022-11-21 熵碼科技股份有限公司 採用迭代計算的模數運算電路
KR102885930B1 (ko) * 2020-12-02 2025-11-12 삼성전자주식회사 상수 승산을 위한 집적 회로 및 이를 포함하는 장치

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4864529A (en) 1986-10-09 1989-09-05 North American Philips Corporation Fast multiplier architecture
US5121431A (en) * 1990-07-02 1992-06-09 Northern Telecom Limited Processor method of multiplying large numbers
US5509129A (en) * 1993-11-30 1996-04-16 Guttag; Karl M. Long instruction word controlling plural independent processor operations
US6421698B1 (en) * 1998-11-04 2002-07-16 Teleman Multimedia, Inc. Multipurpose processor for motion estimation, pixel processing, and general processing
US6598064B1 (en) * 2000-01-04 2003-07-22 National Semiconductor Corporation Split multiplier array and method of operation
AU2001273653A1 (en) 2000-06-29 2002-01-14 The State of Oregon acting by and through The State Board of Higher Education on behalf of TheUniversity Of Oregon Method and apparatus for incomplete modular arithmetic
US6813627B2 (en) * 2001-07-31 2004-11-02 Hewlett-Packard Development Company, L.P. Method and apparatus for performing integer multiply operations using primitive multi-media operations that operate on smaller operands
JP3732450B2 (ja) * 2002-03-19 2006-01-05 沖電気工業株式会社 剰余演算器
US7296049B2 (en) * 2002-03-22 2007-11-13 Intel Corporation Fast multiplication circuits

Also Published As

Publication number Publication date
CN1717653A (zh) 2006-01-04
DE60316342D1 (de) 2007-10-25
JP2006508464A (ja) 2006-03-09
AU2003278492A1 (en) 2004-06-23
EP1573510B1 (de) 2007-09-12
AU2003278492A8 (en) 2004-06-23
WO2004051456A2 (en) 2004-06-17
WO2004051456A3 (en) 2004-12-16
US7536429B2 (en) 2009-05-19
GB0227793D0 (en) 2003-01-08
EP1573510A2 (de) 2005-09-14
DE60316342T2 (de) 2008-06-05
CN1717653B (zh) 2010-04-28
US20060020654A1 (en) 2006-01-26

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