ATE354852T1 - Datenspeichergerät sowie verfahren zum auffrischen der auf einem solchen gerät gespeicherten daten - Google Patents

Datenspeichergerät sowie verfahren zum auffrischen der auf einem solchen gerät gespeicherten daten

Info

Publication number
ATE354852T1
ATE354852T1 AT02077116T AT02077116T ATE354852T1 AT E354852 T1 ATE354852 T1 AT E354852T1 AT 02077116 T AT02077116 T AT 02077116T AT 02077116 T AT02077116 T AT 02077116T AT E354852 T1 ATE354852 T1 AT E354852T1
Authority
AT
Austria
Prior art keywords
storage device
refreshing
data storage
data stored
data
Prior art date
Application number
AT02077116T
Other languages
English (en)
Inventor
Pierre Christophe Fazan
Serguei Okhonin
Original Assignee
Innovative Silicon Sa
Ecole Polytech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Innovative Silicon Sa, Ecole Polytech filed Critical Innovative Silicon Sa
Application granted granted Critical
Publication of ATE354852T1 publication Critical patent/ATE354852T1/de

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Semiconductor Memories (AREA)
AT02077116T 2002-04-18 2002-05-29 Datenspeichergerät sowie verfahren zum auffrischen der auf einem solchen gerät gespeicherten daten ATE354852T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02405314A EP1355317A1 (de) 2002-04-18 2002-04-18 Anordnung zum Auffrischen eines Speichers

Publications (1)

Publication Number Publication Date
ATE354852T1 true ATE354852T1 (de) 2007-03-15

Family

ID=28459619

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02077116T ATE354852T1 (de) 2002-04-18 2002-05-29 Datenspeichergerät sowie verfahren zum auffrischen der auf einem solchen gerät gespeicherten daten

Country Status (3)

Country Link
EP (1) EP1355317A1 (de)
AT (1) ATE354852T1 (de)
DE (1) DE60218283T2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7410856B2 (en) 2006-09-14 2008-08-12 Micron Technology, Inc. Methods of forming vertical transistors

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448513A (en) * 1993-12-02 1995-09-05 Regents Of The University Of California Capacitorless DRAM device on silicon-on-insulator substrate
JP3759648B2 (ja) * 1996-03-04 2006-03-29 株式会社ルネサステクノロジ 半導体記憶装置
US5881010A (en) * 1997-05-15 1999-03-09 Stmicroelectronics, Inc. Multiple transistor dynamic random access memory array architecture with simultaneous refresh of multiple memory cells during a read operation

Also Published As

Publication number Publication date
DE60218283D1 (de) 2007-04-05
EP1355317A1 (de) 2003-10-22
DE60218283T2 (de) 2007-11-15

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Legal Events

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