ATE329312T1 - Verfahren zur verwaltung eines speichers mit fifo-organisation, und zugehörige vorrichtung - Google Patents

Verfahren zur verwaltung eines speichers mit fifo-organisation, und zugehörige vorrichtung

Info

Publication number
ATE329312T1
ATE329312T1 AT04292872T AT04292872T ATE329312T1 AT E329312 T1 ATE329312 T1 AT E329312T1 AT 04292872 T AT04292872 T AT 04292872T AT 04292872 T AT04292872 T AT 04292872T AT E329312 T1 ATE329312 T1 AT E329312T1
Authority
AT
Austria
Prior art keywords
data
queue
reading
managing
memory
Prior art date
Application number
AT04292872T
Other languages
English (en)
Inventor
Cesar Douady
Philippe Boucard
Original Assignee
Arteris
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Arteris filed Critical Arteris
Application granted granted Critical
Publication of ATE329312T1 publication Critical patent/ATE329312T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/6205—Arrangements for avoiding head of line blocking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/06—Indexing scheme relating to groups G06F5/06 - G06F5/16
    • G06F2205/065—With bypass possibility
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Multi Processors (AREA)
AT04292872T 2003-12-09 2004-12-03 Verfahren zur verwaltung eines speichers mit fifo-organisation, und zugehörige vorrichtung ATE329312T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0314376A FR2863377B1 (fr) 2003-12-09 2003-12-09 Procede de gestion d'un dispositif de memorisation de donnees organisees en file d'attente, et dispositif associe

Publications (1)

Publication Number Publication Date
ATE329312T1 true ATE329312T1 (de) 2006-06-15

Family

ID=34508615

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04292872T ATE329312T1 (de) 2003-12-09 2004-12-03 Verfahren zur verwaltung eines speichers mit fifo-organisation, und zugehörige vorrichtung

Country Status (5)

Country Link
US (1) US20050154843A1 (de)
EP (1) EP1542131B1 (de)
AT (1) ATE329312T1 (de)
DE (1) DE602004001120D1 (de)
FR (1) FR2863377B1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2890766B1 (fr) * 2005-09-12 2007-11-30 Arteris Sa Systeme et procede de communication asynchrone sur circuit, entre des sous-circuits synchrones
FR2899413B1 (fr) * 2006-03-31 2008-08-08 Arteris Sa Systeme de commutation de message
FR2900017B1 (fr) * 2006-04-12 2008-10-31 Arteris Sa Systeme d'interconnexions de blocs fonctionnels externes sur puce muni d'un unique protocole parametrable de communication
FR2901437B1 (fr) * 2006-05-16 2008-08-08 Arteris Sa Procede de realisation d'un circuit de synchronisation de donnees echangees de maniere asynchrone entre deux blocs synchrones, et circuit de synchronisation elabore a partir d'un tel procede
FR2902957B1 (fr) * 2006-06-23 2008-09-12 Arteris Sa Systeme et procede de gestions de messages transmis dans un reseau d'interconnexions
FR2904445B1 (fr) * 2006-07-26 2008-10-10 Arteris Sa Systeme de gestion de messages transmis dans un reseau d'interconnexions sur puce
FR2921507B1 (fr) * 2007-09-26 2011-04-15 Arteris Dispositif de memoire electronique
JP2012221038A (ja) * 2011-04-05 2012-11-12 Toshiba Corp メモリシステム

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0388019A (ja) * 1989-08-31 1991-04-12 Toshiba Corp データ処理装置
US5313649A (en) * 1991-05-28 1994-05-17 International Business Machines Corporation Switch queue structure for one-network parallel processor systems
US5473761A (en) * 1991-12-17 1995-12-05 Dell Usa, L.P. Controller for receiving transfer requests for noncontiguous sectors and reading those sectors as a continuous block by interspersing no operation requests between transfer requests
US5541932A (en) * 1994-06-13 1996-07-30 Xerox Corporation Circuit for freezing the data in an interface buffer
US6151316A (en) * 1997-02-14 2000-11-21 Advanced Micro Devices, Inc. Apparatus and method for synthesizing management packets for transmission between a network switch and a host controller
US6269433B1 (en) * 1998-04-29 2001-07-31 Compaq Computer Corporation Memory controller using queue look-ahead to reduce memory latency
US6651148B2 (en) * 2000-05-23 2003-11-18 Canon Kabushiki Kaisha High-speed memory controller for pipelining memory read transactions
US6886048B2 (en) * 2001-11-15 2005-04-26 Hewlett-Packard Development Company, L.P. Techniques for processing out-of-order requests in a processor-based system
US20040088472A1 (en) * 2002-10-31 2004-05-06 Nystuen John M. Multi-mode memory controller

Also Published As

Publication number Publication date
FR2863377B1 (fr) 2006-02-17
FR2863377A1 (fr) 2005-06-10
DE602004001120D1 (de) 2006-07-20
EP1542131B1 (de) 2006-06-07
EP1542131A1 (de) 2005-06-15
US20050154843A1 (en) 2005-07-14

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Legal Events

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