ATE322713T1 - Spacecake coprozessor kommunikation - Google Patents

Spacecake coprozessor kommunikation

Info

Publication number
ATE322713T1
ATE322713T1 AT03727825T AT03727825T ATE322713T1 AT E322713 T1 ATE322713 T1 AT E322713T1 AT 03727825 T AT03727825 T AT 03727825T AT 03727825 T AT03727825 T AT 03727825T AT E322713 T1 ATE322713 T1 AT E322713T1
Authority
AT
Austria
Prior art keywords
fifo memory
counter
coprocessor
data elements
count
Prior art date
Application number
AT03727825T
Other languages
English (en)
Inventor
Jan Hoogerbrugge
Paul Stravers
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE322713T1 publication Critical patent/ATE322713T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/10—Indexing scheme relating to groups G06F5/10 - G06F5/14
    • G06F2205/106—Details of pointers, i.e. structure of the address generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/12—Indexing scheme relating to groups G06F5/12 - G06F5/14
    • G06F2205/123—Contention resolution, i.e. resolving conflicts between simultaneous read and write operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Stored Programmes (AREA)
  • Testing Of Coins (AREA)
  • Executing Machine-Instructions (AREA)
  • Communication Control (AREA)
  • Bus Control (AREA)
AT03727825T 2002-06-07 2003-05-21 Spacecake coprozessor kommunikation ATE322713T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02077223 2002-06-07

Publications (1)

Publication Number Publication Date
ATE322713T1 true ATE322713T1 (de) 2006-04-15

Family

ID=29724463

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03727825T ATE322713T1 (de) 2002-06-07 2003-05-21 Spacecake coprozessor kommunikation

Country Status (8)

Country Link
US (1) US20050177659A1 (de)
EP (1) EP1514172B1 (de)
JP (1) JP2005529397A (de)
CN (1) CN100437466C (de)
AT (1) ATE322713T1 (de)
AU (1) AU2003233024A1 (de)
DE (1) DE60304468T2 (de)
WO (1) WO2003104968A2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107135200A (zh) * 2017-03-29 2017-09-05 中国航空无线电电子研究所 基于fpga的高速串行总线数据发送方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4486854A (en) * 1981-10-15 1984-12-04 Codex Corporation First-in, first-out memory system
DE3689151D1 (de) * 1986-12-30 1993-11-11 Ibm Nicht-sperrender Warteschlangenmechanismus.
CA1286421C (en) * 1987-10-14 1991-07-16 Martin Claude Lefebvre Message fifo buffer controller
US5450546A (en) * 1992-01-31 1995-09-12 Adaptec, Inc. Intelligent hardware for automatically controlling buffer memory storage space in a disk drive
US5313638A (en) * 1992-03-24 1994-05-17 International Business Machines Corp. Method using semaphores for synchronizing communication between programs or processes resident in a computer system
US5434975A (en) * 1992-09-24 1995-07-18 At&T Corp. System for interconnecting a synchronous path having semaphores and an asynchronous path having message queuing for interprocess communications
GB2291230B (en) * 1992-10-15 1996-10-16 Fujitsu Ltd Fifo memory devices
US5544327A (en) * 1994-03-01 1996-08-06 International Business Machines Corporation Load balancing in video-on-demand servers by allocating buffer to streams with successively larger buffer requirements until the buffer requirements of a stream can not be satisfied
US5664223A (en) * 1994-04-05 1997-09-02 International Business Machines Corporation System for independently transferring data using two independently controlled DMA engines coupled between a FIFO buffer and two separate buses respectively
US5717954A (en) * 1995-10-13 1998-02-10 Compaq Computer Corporation Locked exchange FIFO
US6192427B1 (en) * 1997-05-02 2001-02-20 Texas Instruments Incorporated Input/output buffer managed by sorted breakpoint hardware/software
US6188699B1 (en) * 1997-12-11 2001-02-13 Pmc-Sierra Ltd. Multi-channel encoder/decoder
US6122713A (en) * 1998-06-01 2000-09-19 National Instruments Corporation Dual port shared memory system including semaphores for high priority and low priority requestors
US6279062B1 (en) * 1998-12-28 2001-08-21 Compaq Computer Corp. System for reducing data transmission between coprocessors in a video compression/decompression environment by determining logical data elements of non-zero value and retrieving subset of the logical data elements
US6401149B1 (en) * 1999-05-05 2002-06-04 Qlogic Corporation Methods for context switching within a disk controller
US20010004747A1 (en) * 1999-12-16 2001-06-21 International Business Machines Corporation Method and system for operating a computer system
EP1182543B1 (de) * 2000-08-17 2005-08-24 Texas Instruments Incorporated Unterhaltung einer entfernten Warteschlange unter Benutzung von zwei Zählern in der Verschiebesteuerung mit Hubs und Ports
US20020146023A1 (en) * 2001-01-09 2002-10-10 Regan Myers Transport stream multiplexer utilizing smart FIFO-meters
US6877049B1 (en) * 2002-05-30 2005-04-05 Finisar Corporation Integrated FIFO memory management control system using a credit value

Also Published As

Publication number Publication date
WO2003104968A2 (en) 2003-12-18
CN1659508A (zh) 2005-08-24
WO2003104968A3 (en) 2004-12-29
DE60304468T2 (de) 2007-03-15
EP1514172B1 (de) 2006-04-05
DE60304468D1 (de) 2006-05-18
EP1514172A2 (de) 2005-03-16
US20050177659A1 (en) 2005-08-11
AU2003233024A1 (en) 2003-12-22
CN100437466C (zh) 2008-11-26
JP2005529397A (ja) 2005-09-29

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties