ATE309660T1 - System, welches zwei oder mehr paketschnittstellen, einen schalter, einen gemeinsamen paket-dma (direct memory access)- schaltkreis sowie einen l2 (level 2) cache aufweist - Google Patents

System, welches zwei oder mehr paketschnittstellen, einen schalter, einen gemeinsamen paket-dma (direct memory access)- schaltkreis sowie einen l2 (level 2) cache aufweist

Info

Publication number
ATE309660T1
ATE309660T1 AT02025690T AT02025690T ATE309660T1 AT E309660 T1 ATE309660 T1 AT E309660T1 AT 02025690 T AT02025690 T AT 02025690T AT 02025690 T AT02025690 T AT 02025690T AT E309660 T1 ATE309660 T1 AT E309660T1
Authority
AT
Austria
Prior art keywords
packet
circuit
switch
dma
interface
Prior art date
Application number
AT02025690T
Other languages
English (en)
Inventor
Barton J Sano
Laurent R Moll
Koray Oner
Manu Gulati
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of ATE309660T1 publication Critical patent/ATE309660T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/60—Software-defined switches
    • H04L49/602—Multilayer or multiprotocol switching, e.g. IP switching
AT02025690T 2001-11-20 2002-11-20 System, welches zwei oder mehr paketschnittstellen, einen schalter, einen gemeinsamen paket-dma (direct memory access)- schaltkreis sowie einen l2 (level 2) cache aufweist ATE309660T1 (de)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US33178901P 2001-11-20 2001-11-20
US34471301P 2001-12-24 2001-12-24
US34877702P 2002-01-14 2002-01-14
US34871702P 2002-01-14 2002-01-14
US38074002P 2002-05-15 2002-05-15
US10/269,666 US6912602B2 (en) 2001-11-20 2002-10-11 System having two or more packet interfaces, a switch, and a shared packet DMA circuit

Publications (1)

Publication Number Publication Date
ATE309660T1 true ATE309660T1 (de) 2005-11-15

Family

ID=27559476

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02025690T ATE309660T1 (de) 2001-11-20 2002-11-20 System, welches zwei oder mehr paketschnittstellen, einen schalter, einen gemeinsamen paket-dma (direct memory access)- schaltkreis sowie einen l2 (level 2) cache aufweist

Country Status (4)

Country Link
US (2) US6912602B2 (de)
EP (1) EP1313273B1 (de)
AT (1) ATE309660T1 (de)
DE (1) DE60207177T2 (de)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7016295B2 (en) * 2000-04-26 2006-03-21 Optical Disc Corporation Hybrid discs displaying certain dimensional values
US7239641B1 (en) * 2001-04-24 2007-07-03 Brocade Communications Systems, Inc. Quality of service using virtual channel translation
US7206879B2 (en) * 2001-11-20 2007-04-17 Broadcom Corporation Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems
JP2004005382A (ja) * 2002-03-29 2004-01-08 Fujitsu Ltd データ転送装置および方法
US7650413B2 (en) * 2003-02-07 2010-01-19 Fujitsu Limited Managing shared memory resources in a high-speed switching environment
US7519060B2 (en) * 2003-03-19 2009-04-14 Intel Corporation Reducing inter-packet gaps in packet-based input/output communications
US7103320B2 (en) * 2003-04-19 2006-09-05 International Business Machines Corporation Wireless communication system within a system on a chip
US7200695B2 (en) * 2003-09-15 2007-04-03 Intel Corporation Method, system, and program for processing packets utilizing descriptors
US7111102B2 (en) * 2003-10-06 2006-09-19 Cisco Technology, Inc. Port adapter for high-bandwidth bus
US6981074B2 (en) * 2003-10-14 2005-12-27 Broadcom Corporation Descriptor-based load balancing
US7543037B2 (en) * 2003-12-02 2009-06-02 International Business Machines Corporation RDMA completion and retransmit system and method
US7185147B2 (en) * 2003-12-12 2007-02-27 Intel Corporation Striping across multiple cache lines to prevent false sharing
US7340548B2 (en) * 2003-12-17 2008-03-04 Microsoft Corporation On-chip bus
US20060013135A1 (en) * 2004-06-21 2006-01-19 Schmidt Steven G Flow control in a switch
US7499452B2 (en) * 2004-12-28 2009-03-03 International Business Machines Corporation Self-healing link sequence counts within a circular buffer
US7496695B2 (en) * 2005-09-29 2009-02-24 P.A. Semi, Inc. Unified DMA
US7620746B2 (en) * 2005-09-29 2009-11-17 Apple Inc. Functional DMA performing operation on DMA data and writing result of operation
US20080095050A1 (en) * 2006-03-07 2008-04-24 Qualcomm Incorporated Method and system for de-assignment of resources in a wireless communication system
US8738019B2 (en) * 2006-03-07 2014-05-27 Qualcomm Incorporated Method and system for deassignment of resources in a wireless communication system
US20070268903A1 (en) * 2006-05-22 2007-11-22 Fujitsu Limited System and Method for Assigning Packets to Output Queues
US20070268926A1 (en) * 2006-05-22 2007-11-22 Fujitsu Limited System and Method for Allocating Memory Resources in a Switching Environment
US20070280104A1 (en) * 2006-06-01 2007-12-06 Takashi Miyoshi System and Method for Managing Forwarding Database Resources in a Switching Environment
US7826468B2 (en) * 2006-08-04 2010-11-02 Fujitsu Limited System and method for bypassing an output queue structure of a switch
US7742408B2 (en) * 2006-08-04 2010-06-22 Fujitsu Limited System and method for filtering packets in a switching environment
US20080052463A1 (en) * 2006-08-25 2008-02-28 Nagabhushan Chitlur Method and apparatus to implement cache-coherent network interfaces
US8069279B2 (en) * 2007-03-05 2011-11-29 Apple Inc. Data flow control within and between DMA channels
US8112559B2 (en) * 2008-09-30 2012-02-07 International Business Machines Corporation Increasing available FIFO space to prevent messaging queue deadlocks in a DMA environment
US8631086B2 (en) * 2008-09-30 2014-01-14 International Business Machines Corporation Preventing messaging queue deadlocks in a DMA environment
US8103847B2 (en) 2009-04-08 2012-01-24 Microsoft Corporation Storage virtual containers
US8671172B2 (en) * 2009-07-09 2014-03-11 International Business Machines Corporation Network device configuration
US9424213B2 (en) * 2012-11-21 2016-08-23 Coherent Logix, Incorporated Processing system with interspersed processors DMA-FIFO
US10230665B2 (en) * 2013-12-20 2019-03-12 Intel Corporation Hierarchical/lossless packet preemption to reduce latency jitter in flow-controlled packet-based networks
US9606926B2 (en) * 2014-11-29 2017-03-28 Freescale Semiconductor, Inc. System for pre-fetching data frames using hints from work queue scheduler
US10715441B2 (en) * 2015-09-04 2020-07-14 Arista Networks, Inc. System and method of a high buffered high bandwidth network element
US10379899B2 (en) * 2015-11-18 2019-08-13 Nxp Usa, Inc. Systems and methods for frame presentation and modification in a networking environment
US11134221B1 (en) 2017-11-21 2021-09-28 Daniel Brown Automated system and method for detecting, identifying and tracking wildlife
US10725942B2 (en) 2018-11-09 2020-07-28 Xilinx, Inc. Streaming platform architecture for inter-kernel circuit communication for an integrated circuit
US10924430B2 (en) * 2018-11-09 2021-02-16 Xilinx, Inc. Streaming platform flow and architecture for an integrated circuit
US10990547B2 (en) 2019-08-11 2021-04-27 Xilinx, Inc. Dynamically reconfigurable networking using a programmable integrated circuit
US11232053B1 (en) * 2020-06-09 2022-01-25 Xilinx, Inc. Multi-host direct memory access system for integrated circuits
US11539770B1 (en) 2021-03-15 2022-12-27 Xilinx, Inc. Host-to-kernel streaming support for disparate platforms
US11456951B1 (en) 2021-04-08 2022-09-27 Xilinx, Inc. Flow table modification for network accelerators
US11606317B1 (en) 2021-04-14 2023-03-14 Xilinx, Inc. Table based multi-function virtualization

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4788679A (en) * 1986-09-02 1988-11-29 Nippon Telegraph And Telephone Corporation Packet switch with variable data transfer rate links
CH670715A5 (de) 1986-10-03 1989-06-30 Bbc Brown Boveri & Cie
US5765011A (en) * 1990-11-13 1998-06-09 International Business Machines Corporation Parallel processing system having a synchronous SIMD processing with processing elements emulating SIMD operation using individual instruction streams
US5963745A (en) * 1990-11-13 1999-10-05 International Business Machines Corporation APAP I/O programmable router
EP0692893B1 (de) * 1994-07-12 2000-03-01 Ascom AG Vorrichtung zur Vermittlung in digitalen Datennetzen für asynchronen Transfermodus
US5764895A (en) * 1995-01-11 1998-06-09 Sony Corporation Method and apparatus for directing data packets in a local area network device having a plurality of ports interconnected by a high-speed communication bus
EP0735487B1 (de) * 1995-03-31 2001-10-31 Sun Microsystems, Inc. Schnelle Zweitor-Cachesteuerungsschaltung für Datenprozessoren in einem paketvermittelten cachekohärenten Multiprozessorsystem
US6009527A (en) * 1995-11-13 1999-12-28 Intel Corporation Computer system security
US5805920A (en) 1995-11-13 1998-09-08 Tandem Computers Incorporated Direct bulk data transfers
US5961623A (en) * 1996-08-29 1999-10-05 Apple Computer, Inc. Method and system for avoiding starvation and deadlocks in a split-response interconnect of a computer system
WO1998015155A1 (de) 1996-09-30 1998-04-09 Siemens Aktiengesellschaft Verfahren zur mehrpunktverbindung in einem atm-übertragungssystem mit verbindungsindividuellen warteschlangen
JPH10154100A (ja) * 1996-11-25 1998-06-09 Canon Inc 情報処理システム及び装置及びその制御方法
US5991824A (en) * 1997-02-06 1999-11-23 Silicon Graphics, Inc. Method and system for simultaneous high bandwidth input output
US6298370B1 (en) * 1997-04-04 2001-10-02 Texas Instruments Incorporated Computer operating process allocating tasks between first and second processors at run time based upon current processor load
FR2762418B1 (fr) * 1997-04-17 1999-06-11 Alsthom Cge Alcatel Procede de gestion d'une memoire partagee
JP3524337B2 (ja) 1997-07-25 2004-05-10 キヤノン株式会社 バス管理装置及びそれを有する複合機器の制御装置
US6128728A (en) * 1997-08-01 2000-10-03 Micron Technology, Inc. Virtual shadow registers and virtual register windows
FR2771573B1 (fr) 1997-11-27 2001-10-19 Alsthom Cge Alkatel Element de commutation de paquets a memoires tampons
US6279052B1 (en) * 1998-01-13 2001-08-21 Intel Corporation Dynamic sizing of FIFOs and packets in high speed serial bus applications
JP3563257B2 (ja) 1998-02-20 2004-09-08 Ｎｅｃエレクトロニクス株式会社 Ａｔｍスイッチ回路
US6185520B1 (en) * 1998-05-22 2001-02-06 3Com Corporation Method and system for bus switching data transfers
US6226338B1 (en) * 1998-06-18 2001-05-01 Lsi Logic Corporation Multiple channel data communication buffer with single transmit and receive memories
US6195739B1 (en) * 1998-06-29 2001-02-27 Cisco Technology, Inc. Method and apparatus for passing data among processor complex stages of a pipelined processing engine
US6266731B1 (en) * 1998-09-03 2001-07-24 Compaq Computer Corporation High speed peripheral interconnect apparatus, method and system
US6526451B2 (en) * 1998-09-30 2003-02-25 Stmicroelectronics, Inc. Method and network device for creating circular queue structures in shared memory
US6631401B1 (en) 1998-12-21 2003-10-07 Advanced Micro Devices, Inc. Flexible probe/probe response routing for maintaining coherency
US6651131B1 (en) * 2000-09-06 2003-11-18 Sun Microsystems, Inc. High bandwidth network and storage card
US6691185B2 (en) * 2001-07-13 2004-02-10 Sun Microsystems, Inc. Apparatus for merging a plurality of data streams into a single data stream

Also Published As

Publication number Publication date
EP1313273A1 (de) 2003-05-21
EP1313273B1 (de) 2005-11-09
DE60207177D1 (de) 2005-12-15
US20050147105A1 (en) 2005-07-07
DE60207177T2 (de) 2006-08-03
US6912602B2 (en) 2005-06-28
US20030097498A1 (en) 2003-05-22

Similar Documents

Publication Publication Date Title
ATE309660T1 (de) System, welches zwei oder mehr paketschnittstellen, einen schalter, einen gemeinsamen paket-dma (direct memory access)- schaltkreis sowie einen l2 (level 2) cache aufweist
WO2002073619A3 (en) System latency levelization for read data
WO2003043254A3 (en) Transferring data using direct memory access
MY137269A (en) Memory command handler for use in an image signal processor having a data driven architecture
AU1546095A (en) Data exchange system comprising portable data processing units
EP0902370A3 (de) Doppelte Plattenspeichersteuerungen
DE60119268D1 (de) Terminalgerät und Verfahren zur Datenübertragungssteuerung im Terminalgerät
MY149454A (en) Apparatus and method for data caching to reduce channel change times
WO2002023352A3 (en) System and method for providing reliable transmission in a buffered memory system
DE60212190D1 (de) Übermittlung von transaktionstypen zwischen agenten in einem computersystem durch verwendung von paketkopfteilen mit einem erweiterten typen-/längenerweiterungsfeld
ATE303040T1 (de) Faksimilegerät
DE60205809D1 (de) Datensteueranlage, elektronisches Gerät und Datenübertragungssteuerverfahren
EP1258798A3 (de) Datentransfersteueranlage, elektronisches Gerät und Datentransfersteuerverfahren
TW200502834A (en) Universal serial bus device for exchange data each other
TW375706B (en) Programmable memory access
MY125924A (en) Minimal frame buffer manager for use in data storage devices
MY140857A (en) Programmable display device
WO2003009222A1 (fr) Appareil electronique, appareil de traitement d'informations, appareil adaptateur et systeme d'echange d'informations
EP0814401A3 (de) Computer mit Vorrichtungsbus mit Puffern für externe Geräte
EP1003290A3 (de) Elektronische Vorrichtung und Verfahren zur Unterspannungserkennung
WO2003090231A3 (en) Method of performing access to a single-port memory device, memory access device, integrated circuit device and method of use of an integrated circuit device
DE50016084D1 (de) Datenverarbeitungseinrichtung
AU2003241076A1 (en) Method and apparatus for writing data to a non-volatile memory
WO2001065356A3 (en) Entertainment apparatus, control method and computer program with kernel function realizing mechanism
EP1619607A4 (de) Halbleiteraufzeichnungsvorrichtung

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties