ATE30796T1 - Schaltung zum ausdehnen des daten-fangfensters. - Google Patents

Schaltung zum ausdehnen des daten-fangfensters.

Info

Publication number
ATE30796T1
ATE30796T1 AT84301152T AT84301152T ATE30796T1 AT E30796 T1 ATE30796 T1 AT E30796T1 AT 84301152 T AT84301152 T AT 84301152T AT 84301152 T AT84301152 T AT 84301152T AT E30796 T1 ATE30796 T1 AT E30796T1
Authority
AT
Austria
Prior art keywords
data
permits
expanding
circuit
subcircuits
Prior art date
Application number
AT84301152T
Other languages
English (en)
Inventor
William Ambrosius Iii
Randall Chung
Original Assignee
Western Digital Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Digital Corp filed Critical Western Digital Corp
Application granted granted Critical
Publication of ATE30796T1 publication Critical patent/ATE30796T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Dc Digital Transmission (AREA)
  • Interface Circuits In Exchanges (AREA)
  • Control Of El Displays (AREA)
  • Image Analysis (AREA)
  • Image Generation (AREA)
AT84301152T 1983-02-22 1984-02-22 Schaltung zum ausdehnen des daten-fangfensters. ATE30796T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/468,129 US4550391A (en) 1983-02-22 1983-02-22 Data capture window extension circuit
EP84301152A EP0119766B1 (de) 1983-02-22 1984-02-22 Schaltung zum Ausdehnen des Daten-Fangfensters

Publications (1)

Publication Number Publication Date
ATE30796T1 true ATE30796T1 (de) 1987-11-15

Family

ID=23858542

Family Applications (1)

Application Number Title Priority Date Filing Date
AT84301152T ATE30796T1 (de) 1983-02-22 1984-02-22 Schaltung zum ausdehnen des daten-fangfensters.

Country Status (5)

Country Link
US (1) US4550391A (de)
EP (1) EP0119766B1 (de)
JP (1) JPS6057749A (de)
AT (1) ATE30796T1 (de)
DE (1) DE3467444D1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4780844A (en) * 1986-07-18 1988-10-25 Commodore-Amiga, Inc. Data input circuit with digital phase locked loop
US4884198A (en) * 1986-12-18 1989-11-28 Sun Microsystems, Inc. Single cycle processor/cache interface
US4789838A (en) * 1987-03-23 1988-12-06 Cheng Jyi Min Pulse detection circuit using amplitude and time qualification
US6341326B1 (en) * 1998-12-23 2002-01-22 Intel Corporation Method and apparatus for data capture using latches, delays, parallelism, and synchronization

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3414889A (en) * 1965-09-07 1968-12-03 Westinghouse Electric Corp Electronically multiplexed dynamic serial storage register
US3794987A (en) * 1972-11-01 1974-02-26 Burroughs Corp Mfm readout with assymetrical data window
US3877027A (en) * 1974-01-23 1975-04-08 Ibm Data demodulation employing integration techniques
US4109236A (en) * 1977-06-17 1978-08-22 Honeywell Information Systems Inc. Apparatus for digital data recovery from mass storage devices
US4281356A (en) * 1979-11-28 1981-07-28 R. C. Sanders Technology Systems, Inc. Magnetic disk memory
US4393458A (en) * 1980-02-06 1983-07-12 Sperry Corporation Data recovery method and apparatus using variable window

Also Published As

Publication number Publication date
EP0119766A1 (de) 1984-09-26
EP0119766B1 (de) 1987-11-11
DE3467444D1 (en) 1987-12-17
JPS6057749A (ja) 1985-04-03
US4550391A (en) 1985-10-29

Similar Documents

Publication Publication Date Title
NO166309C (no) Anordning for omkastning av audiosignaler og for gjenopprettelse av omkastet signal.
ATE170996T1 (de) Fehlertolerantes datenverarbeitungssystem
ATE77509T1 (de) Schaltungsanordnung zur gewinnung oder wiederherstellung von rahmensynchronisiersignalen.
NL189482C (nl) Informatie verwerkend stelsel en data-terminal daarvoor.
NO167773C (no) Fremgangsmaate og anordning for behandling av geofysiske data.
KR830007002A (ko) 디지탈 신호 처리장치
GB1557672A (en) Input output data processing system
NO872175L (no) Fremgangsmaate og anordning for behandling av seismiske data ved korrelasjon.
JPS5639642A (en) Decoding circuit
DE3688308D1 (de) Belegleseverfahren und einen bildpuffer benutzendes beleglesegeraet.
ATE30796T1 (de) Schaltung zum ausdehnen des daten-fangfensters.
NL193804B (nl) Storingsveilige gegevensverwerkende inrichting.
JPS51113427A (en) Information processing device
GB1501562A (en) Signal detection apparatus
DE3485191D1 (de) Musterdatenverarbeitungsanlage.
NL193336B (nl) Videosignaalverwerkingsinrichting.
BE844026A (fr) Systeme de lecture et de traitement de donnees, notamment pour horairevariables
IT8220058A0 (it) Complesso circuitale per derivare un segnale di sincronizzazione di campo da un segnale in arrivo.
NL7609963A (nl) Signaalverwerkend stelsel.
JPS5750313A (en) Synchronizing circuit of digital signal reproducer
JPS53124015A (en) Facsimile signal decoding device
JPS5374012A (en) Data demodulating system
NO995556L (no) Fremgangsmåte og anordning for å forbinde en prosessor med en ASIC
NO145318C (no) Fremgangsmaate til og anlegg for utledning og behandling av seismiske data.
JPS5419346A (en) Digital phase synchronous system