ATE255738T1 - Bedingte befehlsausführung in einem rechner - Google Patents

Bedingte befehlsausführung in einem rechner

Info

Publication number
ATE255738T1
ATE255738T1 AT00940607T AT00940607T ATE255738T1 AT E255738 T1 ATE255738 T1 AT E255738T1 AT 00940607 T AT00940607 T AT 00940607T AT 00940607 T AT00940607 T AT 00940607T AT E255738 T1 ATE255738 T1 AT E255738T1
Authority
AT
Austria
Prior art keywords
computer
computer system
command execution
conditional command
computer instruction
Prior art date
Application number
AT00940607T
Other languages
English (en)
Inventor
Sophie Wilson
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of ATE255738T1 publication Critical patent/ATE255738T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Saccharide Compounds (AREA)
AT00940607T 1999-07-21 2000-06-26 Bedingte befehlsausführung in einem rechner ATE255738T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9917127A GB2352536A (en) 1999-07-21 1999-07-21 Conditional instruction execution
PCT/GB2000/002441 WO2001006353A1 (en) 1999-07-21 2000-06-26 Conditional instruction execution in a computer

Publications (1)

Publication Number Publication Date
ATE255738T1 true ATE255738T1 (de) 2003-12-15

Family

ID=10857675

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00940607T ATE255738T1 (de) 1999-07-21 2000-06-26 Bedingte befehlsausführung in einem rechner

Country Status (7)

Country Link
US (2) US7191317B1 (de)
EP (1) EP1204918B1 (de)
AT (1) ATE255738T1 (de)
AU (1) AU5552000A (de)
DE (1) DE60006971T2 (de)
GB (1) GB2352536A (de)
WO (1) WO2001006353A1 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2352536A (en) * 1999-07-21 2001-01-31 Element 14 Ltd Conditional instruction execution
US20040114609A1 (en) 2001-02-14 2004-06-17 Ian Swarbrick Interconnection system
US7127593B2 (en) 2001-06-11 2006-10-24 Broadcom Corporation Conditional execution with multiple destination stores
US7017032B2 (en) 2001-06-11 2006-03-21 Broadcom Corporation Setting execution conditions
US6986025B2 (en) * 2001-06-11 2006-01-10 Broadcom Corporation Conditional execution per lane
US7861071B2 (en) 2001-06-11 2010-12-28 Broadcom Corporation Conditional branch instruction capable of testing a plurality of indicators in a predicate register
US20100274988A1 (en) * 2002-02-04 2010-10-28 Mimar Tibet Flexible vector modes of operation for SIMD processor
US6957321B2 (en) * 2002-06-19 2005-10-18 Intel Corporation Instruction set extension using operand bearing NOP instructions
US7793084B1 (en) * 2002-07-22 2010-09-07 Mimar Tibet Efficient handling of vector high-level language conditional constructs in a SIMD processor
US7002595B2 (en) 2002-10-04 2006-02-21 Broadcom Corporation Processing of color graphics data
US7043518B2 (en) * 2003-07-31 2006-05-09 Cradle Technologies, Inc. Method and system for performing parallel integer multiply accumulate operations on packed data
GB2409066B (en) * 2003-12-09 2006-09-27 Advanced Risc Mach Ltd A data processing apparatus and method for moving data between registers and memory
US7302627B1 (en) * 2004-04-05 2007-11-27 Mimar Tibet Apparatus for efficient LFSR calculation in a SIMD processor
US7873812B1 (en) 2004-04-05 2011-01-18 Tibet MIMAR Method and system for efficient matrix multiplication in a SIMD processor architecture
US7725691B2 (en) * 2005-01-28 2010-05-25 Analog Devices, Inc. Method and apparatus for accelerating processing of a non-sequential instruction stream on a processor with multiple compute units
US7447873B1 (en) * 2005-11-29 2008-11-04 Nvidia Corporation Multithreaded SIMD parallel processor with loading of groups of threads
US10360039B2 (en) * 2009-09-28 2019-07-23 Nvidia Corporation Predicted instruction execution in parallel processors with reduced per-thread state information including choosing a minimum or maximum of two operands based on a predicate value
SE536099C2 (sv) * 2011-12-20 2013-05-07 Mediatek Sweden Ab Digital signalprocessor och basbandskommunikationsanordning
US9395988B2 (en) 2013-03-08 2016-07-19 Samsung Electronics Co., Ltd. Micro-ops including packed source and destination fields
FR3021432B1 (fr) 2014-05-20 2017-11-10 Bull Sas Processeur a instructions conditionnelles
EP3001307B1 (de) 2014-09-25 2019-11-13 Intel Corporation Bit-Shuffle-Prozessoren, Verfahren, Systeme und Anweisungen

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3699526A (en) * 1971-03-26 1972-10-17 Ibm Program selection based upon intrinsic characteristics of an instruction stream
US4907148A (en) * 1985-11-13 1990-03-06 Alcatel U.S.A. Corp. Cellular array processor with individual cell-level data-dependent cell control and multiport input memory
US4792894A (en) * 1987-03-17 1988-12-20 Unisys Corporation Arithmetic computation modifier based upon data dependent operations for SIMD architectures
US5125092A (en) * 1989-01-09 1992-06-23 International Business Machines Corporation Method and apparatus for providing multiple condition code fields to to allow pipelined instructions contention free access to separate condition codes
US5001662A (en) 1989-04-28 1991-03-19 Apple Computer, Inc. Method and apparatus for multi-gauge computation
US5471593A (en) * 1989-12-11 1995-11-28 Branigin; Michael H. Computer processor with an efficient means of executing many instructions simultaneously
US5649142A (en) * 1991-10-24 1997-07-15 Intel Corporation Method and apparatus for translating addresses using mask and replacement value registers and for accessing a service routine in response to a page fault
AU2902092A (en) * 1991-10-24 1993-05-21 Intel Corporation Data processing system
GB2273377A (en) * 1992-12-11 1994-06-15 Hughes Aircraft Co Multiple masks for array processors
JP2832899B2 (ja) 1993-05-31 1998-12-09 松下電器産業株式会社 データ処理装置およびデータ処理方法
US5509129A (en) * 1993-11-30 1996-04-16 Guttag; Karl M. Long instruction word controlling plural independent processor operations
US5659722A (en) * 1994-04-28 1997-08-19 International Business Machines Corporation Multiple condition code branching system in a multi-processor environment
US5974240A (en) * 1995-06-07 1999-10-26 International Business Machines Corporation Method and system for buffering condition code data in a data processing system having out-of-order and speculative instruction execution
US5901318A (en) * 1996-05-06 1999-05-04 Hewlett-Packard Company Method and system for optimizing code
JP3442225B2 (ja) * 1996-07-11 2003-09-02 株式会社日立製作所 演算処理装置
GB2317466B (en) 1996-09-23 2000-11-08 Advanced Risc Mach Ltd Data processing condition code flags
US5996066A (en) * 1996-10-10 1999-11-30 Sun Microsystems, Inc. Partitioned multiply and add/subtract instruction for CPU with integrated graphics functions
JPH10124315A (ja) * 1996-10-18 1998-05-15 Hitachi Ltd 分岐処理方法およびそのための情報処理装置
US6374346B1 (en) * 1997-01-24 2002-04-16 Texas Instruments Incorporated Processor with conditional execution of every instruction
US5898853A (en) * 1997-06-25 1999-04-27 Sun Microsystems, Inc. Apparatus for enforcing true dependencies in an out-of-order processor
US6272514B1 (en) * 1997-11-18 2001-08-07 Intrinsity, Inc. Method and apparatus for interruption of carry propagation on partition boundaries
US6366999B1 (en) 1998-01-28 2002-04-02 Bops, Inc. Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution
US6173393B1 (en) * 1998-03-31 2001-01-09 Intel Corporation System for writing select non-contiguous bytes of data with single instruction having operand identifying byte mask corresponding to respective blocks of packed data
US6115812A (en) * 1998-04-01 2000-09-05 Intel Corporation Method and apparatus for efficient vertical SIMD computations
US6317820B1 (en) * 1998-06-05 2001-11-13 Texas Instruments Incorporated Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism
GB2352308B (en) * 1999-07-21 2004-06-30 Element 14 Ltd Accessing a test condition
GB2352536A (en) * 1999-07-21 2001-01-31 Element 14 Ltd Conditional instruction execution

Also Published As

Publication number Publication date
EP1204918A1 (de) 2002-05-15
AU5552000A (en) 2001-02-05
EP1204918B1 (de) 2003-12-03
DE60006971T2 (de) 2004-10-28
US7191317B1 (en) 2007-03-13
GB9917127D0 (en) 1999-09-22
GB2352536A (en) 2001-01-31
DE60006971D1 (de) 2004-01-15
WO2001006353A1 (en) 2001-01-25
US7979679B2 (en) 2011-07-12
US20060168426A1 (en) 2006-07-27

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