ATE235083T1 - Verfahren und vorrichtung zur effizienten bearbeitung von daten-intensiven anwendungen - Google Patents

Verfahren und vorrichtung zur effizienten bearbeitung von daten-intensiven anwendungen

Info

Publication number
ATE235083T1
ATE235083T1 AT99948420T AT99948420T ATE235083T1 AT E235083 T1 ATE235083 T1 AT E235083T1 AT 99948420 T AT99948420 T AT 99948420T AT 99948420 T AT99948420 T AT 99948420T AT E235083 T1 ATE235083 T1 AT E235083T1
Authority
AT
Austria
Prior art keywords
algorithm
input data
parallel
data
execution units
Prior art date
Application number
AT99948420T
Other languages
English (en)
Inventor
Brian L Drummond
Original Assignee
Rahman Turhan F
Brian L Drummond
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rahman Turhan F, Brian L Drummond filed Critical Rahman Turhan F
Application granted granted Critical
Publication of ATE235083T1 publication Critical patent/ATE235083T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Communication Control (AREA)
  • Geophysics And Detection Of Objects (AREA)
  • Holo Graphy (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
AT99948420T 1998-09-25 1999-09-23 Verfahren und vorrichtung zur effizienten bearbeitung von daten-intensiven anwendungen ATE235083T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/161,168 US6237021B1 (en) 1998-09-25 1998-09-25 Method and apparatus for the efficient processing of data-intensive applications
PCT/US1999/022095 WO2000019331A2 (en) 1998-09-25 1999-09-23 A method and apparatus for the efficient processing of data-intensitive applications

Publications (1)

Publication Number Publication Date
ATE235083T1 true ATE235083T1 (de) 2003-04-15

Family

ID=22580104

Family Applications (1)

Application Number Title Priority Date Filing Date
AT99948420T ATE235083T1 (de) 1998-09-25 1999-09-23 Verfahren und vorrichtung zur effizienten bearbeitung von daten-intensiven anwendungen

Country Status (7)

Country Link
US (1) US6237021B1 (de)
EP (1) EP1116131B1 (de)
AT (1) ATE235083T1 (de)
AU (1) AU6160199A (de)
CA (1) CA2356287C (de)
DE (1) DE69906106T2 (de)
WO (1) WO2000019331A2 (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1527948A (zh) * 2001-03-20 2004-09-08 尼佩泰斯特公司 测试系统使用的低抖动时钟
US6807651B2 (en) 2001-06-15 2004-10-19 Cadence Design Systems, Inc. Procedure for optimizing mergeability and datapath widths of data flow graphs
US6545501B1 (en) 2001-12-10 2003-04-08 International Business Machines Corporation Method and system for use of a field programmable function within a standard cell chip for repair of logic circuits
US6754881B2 (en) 2001-12-10 2004-06-22 International Business Machines Corporation Field programmable network processor and method for customizing a network processor
US7047464B2 (en) * 2001-12-10 2006-05-16 International Business Machines Corporation Method and system for use of a field programmable function within an application specific integrated circuit (ASIC) to access internal signals for external observation and control
US6668361B2 (en) 2001-12-10 2003-12-23 International Business Machines Corporation Method and system for use of a field programmable function within a chip to enable configurable I/O signal timing characteristics
US8015303B2 (en) * 2002-08-02 2011-09-06 Astute Networks Inc. High data rate stateful protocol processing
US7814218B1 (en) * 2002-10-17 2010-10-12 Astute Networks, Inc. Multi-protocol and multi-format stateful processing
US7596621B1 (en) * 2002-10-17 2009-09-29 Astute Networks, Inc. System and method for managing shared state using multiple programmed processors
US8151278B1 (en) 2002-10-17 2012-04-03 Astute Networks, Inc. System and method for timer management in a stateful protocol processing system
ES2217959B1 (es) * 2003-02-14 2006-02-01 Consejo Sup. Investig. Cientificas Procedimiento y dispositivo de encriptacion mediante un criptosistema tipo rsa.
US20060250352A1 (en) * 2005-05-05 2006-11-09 Mice Technoligies, Inc. System and method for improved cursor functionality
US7880913B2 (en) * 2005-12-13 2011-02-01 Infoprint Solutions Company, Llc Methods and systems for segmenting logical pages into work units for processing on multiple compute systems
EP1821254A1 (de) * 2006-02-17 2007-08-22 Deutsche Börse Ag Parallelisierungsbefehlsgesteuerte Datenverwaltung
US7844959B2 (en) * 2006-09-29 2010-11-30 Microsoft Corporation Runtime optimization of distributed execution graph
US20080082644A1 (en) * 2006-09-29 2008-04-03 Microsoft Corporation Distributed parallel computing
US8201142B2 (en) * 2006-09-29 2012-06-12 Microsoft Corporation Description language for structured graphs
DE102010026273B4 (de) 2009-07-07 2018-05-30 GPI Ges. f. Prüfstanduntersuchungen und Ingenieurdienstleistungen mbH Verfahren zum Betrieb von Datenverarbeitungseinheiten und Datenverarbeitungssystemen
US20110055445A1 (en) * 2009-09-03 2011-03-03 Azuray Technologies, Inc. Digital Signal Processing Systems
CN103004170B (zh) * 2010-06-28 2016-03-30 松下知识产权经营株式会社 响应装置及其集成电路、响应方法及响应系统
CN108701257B (zh) 2016-08-22 2023-01-06 甲骨文国际公司 用于实时可视模拟内的动态、增量推荐的系统和方法
US10385717B2 (en) * 2016-10-12 2019-08-20 United Technologies Corporation Multi-ply seal
US10956084B2 (en) 2018-05-04 2021-03-23 International Business Machines Corporation Drive utilization in multi-tiered systems with read-intensive flash
US10691357B2 (en) 2018-08-08 2020-06-23 International Business Machines Corporation Consideration of configuration-based input/output predictions in multi-tiered data storage system management
US10809941B2 (en) 2019-03-11 2020-10-20 International Business Machines Corporation Multi-tiered storage
US11467735B2 (en) 2020-12-01 2022-10-11 International Business Machines Corporation I/O operations in log structured arrays
US11726692B2 (en) 2020-12-02 2023-08-15 International Business Machines Corporation Enhanced application performance using storage system optimization
US11620079B2 (en) 2021-04-28 2023-04-04 International Business Machines Corporation Log structured array offloaded data transfer migrations
US11782641B2 (en) * 2021-06-09 2023-10-10 International Business Machines Corporation Backend aware virtualized storage

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4367524A (en) * 1980-02-07 1983-01-04 Intel Corporation Microinstruction execution unit for use in a microprocessor
US5752070A (en) * 1990-03-19 1998-05-12 California Institute Of Technology Asynchronous processors
US5581773A (en) * 1992-05-12 1996-12-03 Glover; Michael A. Massively parallel SIMD processor which selectively transfers individual contiguously disposed serial memory elements

Also Published As

Publication number Publication date
CA2356287A1 (en) 2000-04-06
WO2000019331A2 (en) 2000-04-06
EP1116131B1 (de) 2003-03-19
US6237021B1 (en) 2001-05-22
WO2000019331A3 (en) 2000-05-25
CA2356287C (en) 2010-12-07
DE69906106T2 (de) 2004-01-29
EP1116131A2 (de) 2001-07-18
DE69906106D1 (de) 2003-04-24
AU6160199A (en) 2000-04-17
WO2000019331A9 (en) 2000-10-19

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