AT393579B - CIRCUIT ARRANGEMENT FOR MAKING A CONFERENCE CONNECTION - Google Patents

Description

AT 393 579 B

The invention relates to a circuit arrangement for establishing a conference connection in a digital telecommunications exchange, with memory devices into which the speech samples of the conference participants are written, and with evaluation and selection circuits containing comparators, evaluated by the speech samples and transmitted to the individual participants on the basis of predetermined criteria a multi-5 plexer are switched through, the loudest speech sample being sent to all participants except the one who created it.

Known conference circuits essentially work according to two principles: the addition principle, in which the speech samples arriving from the individual conference participants are added up and the result is sent back to the participants, and according to the so-called instant speaker principle, in which the speech samples 10 of the moment the loudest speaking subscriber is sent to the other subscribers, while the loudest subscriber uses a different speech signal, e.g. B. receives a zero signal or the speech samples of the previous loudest participant. Such a conference call is given, for example, in EP-OS 0 021 710. This also includes circuitry that monitors the loudest party's speech samples for a predetermined period of time and prevents a supposed next loudest speaker 15 from being selected when the existing loudest speaker's speech sample is currently at a zero crossing of the speech vibration

The invention belongs to the type of instant speaker conference calls. In such a conference call, the loudest speaker receives speech samples in succession from the other conference participants (DE-OS 25 31 181) or those of the previous loudest speaker. However, many participants 20 find this disturbing.

The invention has for its object to provide a conference circuit of the known type, in which the loudest participant receives a particularly meaningful voice signal.

This object is achieved in that the inputs of the comparators of the evaluation and selection circuits are connected to the outputs of two input memories each, in which the voice samples arriving during a frame are written, that these voice samples are compared in pairs by the comparators that the outputs of the comparators are connected to a result buffer, into which the comparison results are each adopted at the end of a frame, that a number of buffers is provided corresponding to the number of possible participants, into which the speech samples are each transferred at the end of a frame, that the output signals of the comparators written in the result buffer 30 are linked in a logic circuit with selection signals by which the receiving subscribers are determined in time, that by the output signals of the logic circuit a multiplexer is controlled, which switches the individual buffers correctly to the time multiple line leading to the subscribers, whereby the loudest subscriber receives the second loudest speech sample (e.g. B. (B)) is supplied. In an advantageous manner, the acceptance clocks for the input memories and for the intermediate memories as well as for the result intermediate memory and the selection signals can be generated by a controller.

The advantages of the invention are, in particular, that the participant conducting the conversation does not have the impression that the line is dead, nor does he receive a mixture of speech samples. Rather, he can become aware of a second speaker who speaks a little quieter and this speaker also have a say. 40 The other advantages of the well-known instant speaker conference circuit remain unchanged: much less effort than with conferences based on the addition principle, no risk of exceeding the level and no need to linearize companded PCM samples and to compress them again after the addition.

An embodiment of the invention is explained below with reference to the drawing

The digital conference circuit evident from the single figure, the z. B. can be used in a PCM remote telephone exchange 45, receives the speech samples from the conference participants via an input line (EL). The embodiment is for the very common conferences between three participants, the z. B. also occur when an operator is switched on, designed Accordingly, three speech samples (A, B and C) are indicated in the drawing which come from three conference participants and arrive in multiples of time via the input line (EL). 50 As indicated in the drawing, the individual digitized speech samples consist of eight bits and the

The input line (EL) therefore has eight parallel individual lines. The same applies to the other lines shown in the drawing, via which voice samples are transmitted within the conference circuit.

As usual with PCM systems, the speech samples are transmitted on the input and output lines in 55 time multiple frames, each with 32 channels. For example, the first participant sends his speech sample (A) in the channel or time slot (5) and also receives speech samples in the time slot (5). The second and third participants send their speech samples (B and C) and receive corresponding speech samples e.g. B. in the time slots (10 and 15).

The speech samples (A, B and C) arriving during a frame are written into corresponding input 60 memories (LAI, LA2 and LA3). These input memories are designed as D flip-flops, they receive takeover clock signals (CLK1, CLK2 or CLK3) at the times mentioned above.

AT 393 579 B from a central or system controller (SC), which derive these clock signals from system clocks (ST) obtained from the main controller of the exchange.

The outputs of the input memories (LAI to LA3) are each connected by an 8-way line to the inputs of intermediate memories (LA4, LAS or LA6), which are also designed as D flip-flops. These buffers also receive their common takeover clock signal (ÜT) from the system control (SC).

The outputs of the buffer memories (LA4 to LA6) are connected to the inputs of a multiplexer (MUX), which consequently receives the speech samples (A, B and C) as input signals at points in time to be explained, and connects them to two control lines (S1 and S2) incoming signals time-controlled · connect to the output line (AL).

The outputs of the input memories (LAI to LA3) are connected in pairs to comparators (COl, C02 and C03), in which the speech samples arriving on the input lines (EL) and written into the input memories (LAI to LA3) are continuously compared with one another during a frame will. The outputs of the comparators are connected via individual lines to a result buffer (LA7), in which the comparison results are written in at the end of a frame by the takeover clock (ÜT).

Three signal outputs of the result buffer (LA7) and two signal outputs of the system control (SC) are connected via individual lines to the inputs of a logic circuit (PROM), which is advantageously designed as a programmable read-only memory, but can also be implemented with discrete components. Two outputs of this logic circuit are connected to the control inputs " Select " via the lines mentioned (S1 and S2). of the multiplexer (MUX).

The system control (SC) derives from the system clocks (ST) the clock signals (CLK1 to CLK3) with which the individual speech samples (A, B, C) are written into the assigned input memories (LAI, LA2 or LA3). At the end of each frame, the transmission clock (ÜT) which is sent out by it is used to transfer the speech samples contained in the input memories to the buffer memories (LA4 to LA6) and the comparison results from the comparators (CO1 to C03) to the result buffer memory (LA7). In addition, the system controller (SC) sends a two-bit subscriber selection signal (TLAW) to the two least significant address inputs (A0 and Al) and determines which subscriber a voice sample is to be sent to (at a given time) .

The speech samples (A, B and C) originating from the first, second and third conference participants arrive successively during a time multiple frame in the conference circuit and are each stored in the input memories (LAI, LA2 and LA3). After all speech samples have been saved, a certain bit pattern is present at the output of the three comparators (CO1 to C03), which depends on the intensities of the speech samples compared with one another. When comparing the speech samples, the sign of the samples is ignored. B the speech sample A = B, there is a " 1 " at the output of the comparator (COl) otherwise a " 0 ". The comparison conditions are indicated in the drawing and are shown in detail below using a table

To compare the volume, not all seven bits have to be used with a »speech sample: if the four most significant bits are used for the comparison, each of the comparators can consist of a single semiconductor chip.

Before a new frame begins, the speech samples are transferred to the buffer (LA4 to LA6) and are thus saved until the time of issue. The bit pattern present at the output of the comparators (CO1 to C03) is written into the result buffer (LA7) with the same transfer clock signal (ÜT). The bit pattern is thus also present at the address inputs (A2, A3 and A4) of the logic circuit (PROM) and selects a specific four-byte range in it.

In three bytes of the selected four-byte area, whereby only two bits are used per byte, there are control data corresponding to the result of the speech sample comparison for the control of the multiplexer (MUX). It is also possible to switch to the fourth byte during the time when there is no output and thus to block the multiplexer output.

The individual byte required within the four-byte range depending on the channel time slot by the two least significant address bits, i. H. by the subscriber selection signal (TLAW).

The following table shows numerical examples which characterize the intensity or volume of the individual speech samples, the comparison results resulting therefrom and the interconnections of the multiplexer (MUX) defined in the logic circuit on the basis of these comparison results. -3-

Claims (2)

AT 393 579 B Possible bit combinations of the comparator Result Numerical examples, number = sample height Output of sample x A < B, B £ C, C < A, Compl Comp2 Comp3 Sample A Sample B Sample C Largest Sample Second Gr. To sample channel time A To channel time B time C 0 0 0 0 0 1 5 logically impossible 3 2 A 0 1 0 5 2 7 C 0 1 1 5 2 3 A 1 0 0 3 7 5 B 1 0 1 3 8 1 B 1 1 0 3 4 5 C 1 1 1 logically impossible BACCABBCCBBCAACAAACBA BCB 0 = statement is incorrect 1 = statement is true Bit combinations 0 00 and 111 cannot occur because, as can be easily demonstrated, they represent a logical contradiction. All other bit combinations represent meaningful results and lead to clear handling in the logic circuit (PROM). An example is the bit combination 011, which represents the following statement about the speech samples: A > B, B < C and C < A. It follows that the speech sample (A) has the highest intensity and the speech sample (C) the second highest intensity. Due to the described links, this leads to the fact that in the time position of the participant (A) the second loudest speech sample, i.e. H. the speech sample given by the participant (C) is sent. At the times of the participants (B and C), the loudest speech sample, i.e. H. the participant's speech sample (A) transmitted. As long as only two conference participants are talking to each other, the conference circuit according to the invention leads to a completely normal two-way connection. In a conventional instant speaker conference, on the other hand, the loudest speaker hardly hears a person who speaks only as long as he speaks. If a conference call is intended for a larger number of participants, the larger number of individual memories (LA) required for this purpose is expediently combined in a RAM memory. With the aid of a comparator circuit, the incoming speech samples are immediately sorted into the RAM memory according to their size. In this way, the expenditure on components remains low. PATENT CLAIMS 1. Circuit arrangement for establishing a conference connection in a digital telecommunications exchange, with memory devices into which the voice samples of the conference participants are written, and with evaluation and selection circuits containing comparators, evaluated by the voice samples and based on predetermined criteria to the individual participants via one Multiplexers are switched through, the loudest speech sample being sent to all participants except the one who generated it, characterized in that the inputs of the comparators (COl, C02, C03) of the evaluation and selection circuits with the outputs of two input memories each ( LAI, LA2, LA3), into which speech samples arriving during a frame are written, that these speech samples (A, B, C) are compared in pairs by the comparators (COl, C02, C03), that the outputs of the comparators ( COl, C02, C03) m it is connected to a result buffer (LA7), in which the comparison results are each adopted at the end of a frame, that a number of buffers (LA4, LA5, LA6) corresponding to the number of possible participants is provided, into which the speech samples each end Framework are adopted that the output signals of the comparators (COl, C02, C03) written in the result buffer (LA7) in a logic circuit with selection signals (TLAW) by which the receiving participants are fixed in time are linked, that a multiplexer (MUX) is controlled by the output signals of the logic circuit (PROM), which switches through the individual buffers (LA4, LA5, LA6) in the correct timing to the time multiple line (AL) leading to the participants, the loudest participant the second-5 loudest speech sample (e.g. B. (B)) is supplied. 2. Circuit arrangement according to claim 1, characterized in that the takeover clocks for the input memories (LAI, LA2, LA3) and for the buffer memories (LA4, LA5, LA6) and for the result buffer (LA7) and the selection signals (TLAW) from a controller (SC) are generated. 10 For this 1 sheet drawing -5-