AT335779B - CIRCUIT ARRANGEMENT FOR CONTROLLED CYCLING TRANSMISSION OF DATA VIA ONE OR MORE MEMORIES TO A DATA PROCESSING SYSTEM - Google Patents

CIRCUIT ARRANGEMENT FOR CONTROLLED CYCLING TRANSMISSION OF DATA VIA ONE OR MORE MEMORIES TO A DATA PROCESSING SYSTEM

Info

Publication number
AT335779B
AT335779B AT802274A AT802274A AT335779B AT 335779 B AT335779 B AT 335779B AT 802274 A AT802274 A AT 802274A AT 802274 A AT802274 A AT 802274A AT 335779 B AT335779 B AT 335779B
Authority
AT
Austria
Prior art keywords
memories
processing system
circuit arrangement
data processing
data via
Prior art date
Application number
AT802274A
Other languages
German (de)
Other versions
ATA802274A (en
Inventor
Johann Schmid
Franz Dipl Ing Voggenberger
Original Assignee
Schrack Elektrizitaets Ag E
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Schrack Elektrizitaets Ag E filed Critical Schrack Elektrizitaets Ag E
Priority to AT802274A priority Critical patent/AT335779B/en
Priority to DE19752539821 priority patent/DE2539821A1/en
Priority to CH1289675A priority patent/CH599629A5/xx
Publication of ATA802274A publication Critical patent/ATA802274A/en
Application granted granted Critical
Publication of AT335779B publication Critical patent/AT335779B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bidirectional Digital Transmission (AREA)
AT802274A 1974-10-04 1974-10-04 CIRCUIT ARRANGEMENT FOR CONTROLLED CYCLING TRANSMISSION OF DATA VIA ONE OR MORE MEMORIES TO A DATA PROCESSING SYSTEM AT335779B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AT802274A AT335779B (en) 1974-10-04 1974-10-04 CIRCUIT ARRANGEMENT FOR CONTROLLED CYCLING TRANSMISSION OF DATA VIA ONE OR MORE MEMORIES TO A DATA PROCESSING SYSTEM
DE19752539821 DE2539821A1 (en) 1974-10-04 1975-09-08 Switching circuit control of data input - to process controller over memory stages with changes in input data detected by comparison with memory state to generate gating signal
CH1289675A CH599629A5 (en) 1974-10-04 1975-10-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
AT802274A AT335779B (en) 1974-10-04 1974-10-04 CIRCUIT ARRANGEMENT FOR CONTROLLED CYCLING TRANSMISSION OF DATA VIA ONE OR MORE MEMORIES TO A DATA PROCESSING SYSTEM

Publications (2)

Publication Number Publication Date
ATA802274A ATA802274A (en) 1976-07-15
AT335779B true AT335779B (en) 1977-03-25

Family

ID=3601725

Family Applications (1)

Application Number Title Priority Date Filing Date
AT802274A AT335779B (en) 1974-10-04 1974-10-04 CIRCUIT ARRANGEMENT FOR CONTROLLED CYCLING TRANSMISSION OF DATA VIA ONE OR MORE MEMORIES TO A DATA PROCESSING SYSTEM

Country Status (3)

Country Link
AT (1) AT335779B (en)
CH (1) CH599629A5 (en)
DE (1) DE2539821A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3203263A1 (en) * 1982-02-01 1983-08-11 Scheidt & Bachmann GmbH, 4050 Mönchengladbach Method for transmitting and storing system-related data
IT1193650B (en) * 1983-01-31 1988-07-21 Honeywell Inf Systems INCREASED RELIABILITY INTERRUPTION APPARATUS
FR2568035B1 (en) * 1984-07-17 1989-06-02 Sagem METHOD FOR INTERCONNECTING MICROPROCESSORS

Also Published As

Publication number Publication date
ATA802274A (en) 1976-07-15
CH599629A5 (en) 1978-05-31
DE2539821A1 (en) 1976-04-22

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