JP4266477B2 - Information processing apparatus and control method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an information processing apparatus and method applicable to, for example, a digital still camera, a portable videophone terminal device, or a camera-equipped notebook PC.
[0002]
[Prior art]
In recent years, with the progress of technologies such as miniaturization, power saving, high integration of LSI, high functionality, low power consumption of solid-state imaging devices such as CCDs, as represented by digital still cameras, batteries Driven portable imaging devices are commonly used. Furthermore, portable videophone terminals with built-in mobile phone functions, notebook PCs with built-in cameras, and the like have been developed. In such a photographing apparatus driven by a battery in particular, power reduction is required in order to extend the operation time of the battery. In addition, in an imaging device driven by an AC power source, a more effective power saving function has been demanded from the viewpoint of environmental protection and the like. Therefore, the remaining battery level has always been displayed, and when the remaining battery level is low, the user is encouraged to turn off the power frequently, or the clock supply to the non-operating part is cut off according to the operation mode selected by the user. Power saving function is realized.
[0003]
[Problems to be solved by the invention]
In general, in a photographing apparatus, the amount of image data to be processed per unit time increases as the frame rate and resolution of a photographed image increase. Therefore, an electronic circuit that handles image data requires a high operation clock frequency. In general, since the power consumption of a circuit increases in proportion to the clock frequency for driving the circuit, an increase in the frame rate and resolution of an image causes an increase in power consumption. Therefore, in order to reduce power consumption, it is desirable to reduce the frame rate and resolution as much as possible.
[0004]
However, for example, a photographing apparatus such as a digital camera has different requirements for the frame rate and resolution of an image to be captured depending on the operation mode. For example, in the electronic viewfinder mode (referred to as EVF mode), it is desirable to display a moving image that is as smooth as possible, but the display screen is often a small screen built in the device. Therefore, the higher the frame rate, the better, but the resolution is not so required. In the still image capturing mode (referred to as a shooting mode), the frame rate may be the lowest (because it is a still image), but the resolution is required to be the maximum. Further, in the reproduction mode for reproducing the recorded image, the image signal is not captured by the image sensor, and the display on the display unit is performed at the maximum resolution. In the videophone mode, both the frame rate and resolution are determined by the data transfer capability of the telephone line.
[0005]
As is clear from the above example, each functional block constituting such a photographing apparatus, such as a photographing functional block, an image processing functional block, and a display functional block, processes per unit time according to its operation mode. The amount of data to be greatly changed and it is not always necessary to operate at the maximum frequency. As long as normal operation is performed, it is possible to reduce the power consumption of the apparatus by operating at the lowest possible frequency. Nevertheless, in the conventional technique, the power consumption of the device is suppressed only by stopping the supply of the clock signal to the functional block that is completely in the non-operating state, so that effective power reduction can be performed. could not.
[0006]
  The present invention has been made in view of the above-described conventional example, and the frequency of the clock signal supplied to each of the plurality of processing means is determined byeachProcessing meansOf the amount of data stored in the memory ofInformation processing apparatus capable of suppressing the power consumption of the entire apparatus by switching according tocontrolIt aims to provide a method.
[0008]
[Means for Solving the Problems]
  In order to achieve the above object, an information processing apparatus of the present invention has the following configuration. That is,
  A clock generation source for generating clock signals of a plurality of frequencies each having a different frequency;
  Selecting means for selecting any one of a plurality of clock signals output from the clock generation source;
  Each isA memory for storing processed or processed data;A plurality of processing means operated by a clock signal from a clock generation source selected by the selection means;
  The plurality of processing meansInformation on the amount of data stored in the memory included in each processing unit is acquired, and a clock signal for each processing unit is selected according to the acquired information on the amount of data.Selection control means to control;
It is characterized by having.
[0009]
  In order to achieve the above object, the information processing of the present inventionDevice controlThe method comprises the following steps. That is,
  Each is a method of controlling an information processing apparatus having a memory for storing processed or processed data and having a plurality of processing means that operate in response to a clock signal from a clock generation source,
  In order to operate each processing means of the plurality of processing means,A selection step of selecting any one of a plurality of frequency clock signals output from a clock generation source that generates a plurality of clock signals having different frequencies.
  AboveOf multiple processing meansInformation on the amount of data stored in the memory included in each processing unit is acquired, and a clock signal for each processing unit is selected according to the acquired information on the amount of data.A selective control process to control;
It is characterized by having.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
[0011]
FIG. 1 is a block diagram showing a configuration of a portable videophone terminal device according to an embodiment of the present invention. In FIG. 1, among the lines connecting the functional blocks, the data system connection is shown by a thick solid line, the control system connection is shown by a thin solid line, and the clock system connection is shown by a dotted line. However, not all the connections are illustrated, and only representative wiring connections necessary for the description are illustrated.
[0012]
As main block configurations of this videophone terminal device, an image capturing controller 1 that executes processing relating to capturing of captured image signals, a signal processor 2 that performs image processing on image data generated from the image signals, and an image It has a display controller 3 that performs processing related to image display based on data, a memory controller 4 that performs memory control for storing image data in a memory, and a CPU 5 that controls the entire apparatus.
[0013]
First, operations will be described for each of EVF (viewfinder) mode, shooting mode, playback mode, and videophone mode as typical operation modes.
[0014]
[Description of Image Capture Controller 1]
When an image to be imaged is formed on the CCD 7 via the lens module 6, an image signal corresponding to the image is output from the CCD 7. The lens module 6 includes a lens, a drive system for auto-iris, a drive system for auto-focus, and the like. Control of these drive systems is performed by the CPU 5 by a control signal (not shown). The image signal output from the CCD 7 is input to a preprocessing module (CDS / AGC) 8. In the present embodiment, the effective number of pixels captured by the CCD 7 is 640 × 480 pixels (equivalent to VGA). The preprocessing module 8 has CDS (correlated double sampling) and AGC (automatic gain control) functions. The clock and timing signals for the CCD 7 and the preprocessing module 8 are supplied from a timing generation circuit (TG) 9. The image data that has been preprocessed by the preprocessing module 8 is converted into 10-bit digital data by an A / D converter (ADC) 10, and a pixel clock (Pixel Clock) generated by a timing generation circuit (SG) 11. ) In synchronization with the image capture controller 1.
[0015]
The image data input to the image capture controller 1 is thinned by the thinning circuit 1a, and the data resulting from the thinning is written into the FIFO 1b. The thinning method in the thinning circuit 1a is preset by the CPU 5 by a control signal (not shown).
[0016]
FIG. 2A is a timing chart showing an example of the operation of the thinning circuit 1a. The thinning circuit 1a includes a pixel counter (Pixel Count) for counting a pixel clock (Pixel Clock) input from the SG 11, and a line counter (Line Num) for counting the number of lines of an image based on a horizontal / vertical synchronization signal (not shown). Based on the thinning method preset by the CPU 5 and the count values of these counters, the digital image data input from the ADC 10 is latched and a clock (Latch Clock) for writing to the FIFO 1b is generated. .
[0017]
In the example of FIG. 2A, a case where 1/2 horizontal and vertical thinning is performed on data of horizontal 640 pixels and vertical 480 lines (320 × 240 pixels: equivalent to CIF) is illustrated. Therefore, the effective line is an odd line, and the signal for indicating this period is the Active Line signal. The effective pixels are odd pixels, and a signal indicating this is an Active Pixel signal.
[0018]
Based on these signals, the logical product of the Pixel Clock, the Active Line signal, and the Active Pixel signal is obtained as shown in FIG. 2B, and this is the Latch Clock signal for writing to the FIFO 1b. In FIG. 2A, data to be written to the FIFO 1b is Data to FIFO.
[0019]
The thinning circuit 1a can be configured to have a frame thinning function. In this case, a frame counter is further provided. For example, when one frame is captured every four frames, an Active Frame signal is generated when the frame counter is “a multiple of 4 + 1”, and the AND circuit shown in FIG. Should be added to the input.
[0020]
When the bus interface circuit (BUS IF) 1c detects that the FIFO 1b is not empty (any data is written), the bus interface circuit (BUS IF) 1c generates a data write bus transaction on the main bus (MB) and sends it to the memory controller 4. Data read from the FIFO 1b is transferred. The bus interface circuit 1c normally operates with a bus clock asynchronous with the image capture clock (Latch Clock). Accordingly, the read clock of the FIFO 1b is asynchronous with the write clock (Latch Clock) of the FIFO 1b, and the FIFO 1b is provided to buffer this asynchronous data transfer.
[0021]
Since a plurality of other bus masters that generate bus transactions are connected to the main bus MB (signal processor 2, display controller 3, CPU 5, etc.), there is a possibility that a plurality of bus transactions may occur simultaneously. is there. Therefore, the bus arbiter 12 arbitrates the bus so that only one bus master can generate a bus transaction at a time.
[0022]
[Description of Memory Controller 4]
The memory controller 4 receives the bus transaction in the bus interface circuit (BUS IF) 4a, and writes the image data to be stored and the memory address to store the image data in the temporary buffer 4b. The SDRAM interface circuit (SDRAM IF) 4c outputs various control signals to the SDRAM 13, which is an image memory, and outputs the memory address and image data stored in the buffer 4b to the SDRAM 13. The bus interface circuit 4a, the buffer 4b, the SDRAM interface circuit 4c, and the SDRAM 13 all operate in synchronization with the bus clock.
[0023]
[Description of Signal Processor 2]
The signal processor 2 generates a bus transaction for reading image data, and reads out the image data captured by the image capture controller from the image memory by a bus interface circuit (BUS IF) 2a that operates with a bus clock. The image data read out in this way is written into the bidirectional FIFO 2b in synchronization with the bus clock. The DSP (digital signal processor) 2c operates with a clock (DSP clock) different from the bus clock, accesses the data of the bidirectional FIFO 2b in synchronization with the DSP clock, and performs YC separation by color matrix processing. Subsequently, processing such as color correction, edge enhancement, white balance adjustment, and gamma correction is performed. The image data obtained in this way is used not only for display on the monitor 15 but also for image compression. When used for display on the monitor 15, the bus interface circuit 2 a is activated so that the display controller 3 can read it, a write bus transaction is generated, and data is transferred to the SDRAM 13.
[0024]
[Explanation of EVF mode]
In the EVF mode, consecutive frames are taken into the image memory 13 by repeating the above operation for each frame. The area of the image memory into which the signal processor 2 writes image data may be an operation of overwriting the same area. The display controller 3 obtains display data by reading out image data from the area of the image memory. At that time, the display controller 3 generates a bus transaction for reading out the image data, and reads out the image data to be displayed from the image memory 13 by the bus interface circuit (BUS IF) 3a operating with the bus clock. The display controller 3 further inputs the read image data to the write port of the FIFO 3b in synchronization with the bus clock. As represented by NTSC monitors and liquid crystal displays, a display device generally needs to continuously refresh the screen, and therefore must continue to operate at a certain pixel clock during the effective screen period. Therefore, the bus interface circuit 3a continues to read image data from the image memory until the FIFO 3b becomes full.
[0025]
Next, the interpolation circuit 3c reads image data from the FIFO 3b in synchronization with the display pixel clock. The interpolation circuit 3c is provided with a line memory, and the image data read from the FIFO 3b is first stored in this line memory. The image data stored in the line memory is read in order from the head when there is no interpolation, is input to the NTSC encoder 3d, and is converted into video data in the NTSC format. In this case, when the image data for one pixel is read, the interpolation circuit 3c immediately reads the image data for one pixel from the FIFO 3b. When performing line interpolation here, after sending line data for (number of lines to be interpolated-1) to the NTSC encoder 3d, the next line is sent every time image data for one pixel is sent to the NTSC encoder 3d. Image data for one pixel is read from the FIFO 3b. For example, here, when performing quadruple interpolation in the line direction, three lines are displayed as image data from the line memory, and when displaying the fourth line, from the FIFO 3b while displaying the line. The image data of the next line is read.
[0026]
The video data converted into the NTSC format by the NTSC encoder 3d is converted into an analog signal by the D / A converter (DAC) 14 and then displayed on the monitor 15 of the NTSC.
[0027]
The operation in the EVF mode is performed by performing the above operation continuously for each frame. In this EVF mode, it is necessary to read image data for each frame even if the image capture controller 1 performs frame thinning. In this case, the displayed image is dropped, but the monitor 15 needs to continue to operate at a constant frame rate.
[0028]
[Explanation of shooting mode]
Next, the operation in the shooting mode will be described. In this shooting mode, after one frame of image data is captured, this image data is JPEG compressed and recorded in an external storage such as the memory card 17.
[0029]
First, when the CPU 5 detects that the shutter button of the switch group 16 including the shutter button is pressed, the CPU 5 captures the next frame of image data to the image capture controller 1 by a control signal (not shown) and thereafter. Instructs not to capture the image data of the current frame. Similarly, the signal processor 2 is notified to compress the next one frame of image data.
[0030]
Unlike the case of the EVF mode described above, the image capture controller 1 temporarily stops its operation when it captures one frame of image and transfers the image data to the image memory 13. The signal processor 2 reads out the image data for one frame stored in the memory 13 and performs YC separation, color correction, edge enhancement, white in exactly the same way as when generating image data for display in the EVF mode. Performs image processing such as balance adjustment and gamma correction. Immediately after that, the encoded data obtained by subjecting the image data to DCT arithmetic processing, quantization processing, variable-length encoding processing, and the like are stored in an area different from the display image data area in the image memory 13. Write to.
[0031]
The CPU 5 reads the image data stored in the image memory 13, adds necessary markers and the like to JPEG data, and stores the data in the memory card 17. When the storage of the image data for one frame is thus completed, the CPU 5 notifies the image capture controller 1 to resume the capture of the image signal in the EVF mode.
[0032]
The encoded image data stored in the memory card 17 can be accessed from a PC or the like via a communication circuit 18 that implements an interface with a host computer such as a PC. In the present embodiment, the communication circuit 18 includes, for example, a serial interface, USB, IrDA, a mobile phone module, and the like.
[0033]
[Description of playback mode]
Next, the operation in the playback mode will be described. In this playback mode, the operation of the image capture controller 1 is stopped. The CPU 5 reads the encoded compressed data stored in the memory card 17 and writes it in the SDRAM 13. The signal processor 2 reads the code data written in the SDRAM 13, performs image decompression processing such as decoding, inverse quantization, and inverse DCT conversion to obtain displayable image data, and then writes the data again in the SDRAM 13. return. The display controller 3 reads this displayable data from the SDRAM 13 and performs a display operation.
[0034]
[Description of videophone mode]
Next, the operation in the videophone mode will be described. In the above-described shooting mode, the image capture controller 1 stops the temporary operation after capturing one frame of image data. However, in this videophone mode, image data of consecutive frames are captured one after another without interrupting the image data capturing process. The capture frame rate at this time is determined based on the thinning method set by the CPU 5. The image data thus captured is subjected to image processing and image compression / encoding processing by the signal processor 2 by the same processing as in the photographing mode, and is written in the SDRAM 13. The code data thus written in the SDRAM 13 is read by the CPU 5, inserted with a predetermined marker, etc., and then transmitted to the other party through the telephone line by the mobile phone module of the communication circuit 18.
[0035]
On the other hand, code data received from the other party through the telephone line is written from the communication circuit 18 to the SDRAM 13 via the CPU 5. The signal processor 2 reads the code data written in the SDRAM 13, performs image decompression processing such as decoding, inverse quantization, and inverse DCT conversion to obtain displayable image data, and then writes the data again in the SDRAM 13. return. The display controller 3 performs a display operation so that image data to be displayed is read from the SDRAM 13 and displayed on the monitor 15.
[0036]
As described above, the image picked up by the CCD 7 can be transmitted to the call partner, and the image data sent from the communication partner can be received and displayed on the monitor 15.
[0037]
[Clock Description]
Next, clocks supplied to the image capture controller 1, the signal processor 2, the display controller 3, and the memory controller 4 will be described.
[0038]
Clock generators (CG) 19, 20, 21, 22 are variable clock generators whose clock output can be turned on / off by the CPU 5. The clock generator (CG (C)) 19 generates an operation clock for the SG 11 and the image capturing unit (thinning circuit 1a, FIFO 1b) of the image capturing controller 1. The clock generator (CG (D)) 20 generates an operation clock for the DSP 2c. The clock generator (CG (B)) 21 generates an operation clock for the bus interface unit of each controller. The clock generator (CG (N)) 22 generates operation clocks for the FIFO 3b, the interpolation circuit 3c, the NTSC encoder 3d, and the D / A converter 14 of the display controller 3.
[0039]
The bus clock output from the clock generator 21 is supplied to the bus interface circuit of each controller. The clock gate circuits (G) 23, 24, 25, and 26 are provided so that the clock supply can be stopped for each controller. I have. Among them, the clock gate circuit 26 is controlled by the CPU 5, the clock gate circuit 23 is controlled by a control signal from the FIFO 1b, the clock gate circuit 24 is controlled by the FIFO 2b, and the clock gate circuit 25 is controlled by a control signal from the FIFO 3b. .
[0040]
Next, how to control the setting of the thinning circuit 1a and the interpolation circuit 3c according to the operation mode will be described.
[0041]
The operation mode is changed by operating the switch group 16 by the user. Various examples of the configuration of the switch can be considered. In this embodiment, the switch is configured by a dial and a push button. By rotating the dial, the operation mode candidates are sequentially updated and displayed, and when the candidates are displayed, the displayed operation mode is selected as the actual operation mode by pressing the push button. An interrupt is generated in the CPU 5 by this operation mode selection event, and the operation mode change processing routine is executed by the interrupt processing routine stored in the ROM 27.
[0042]
In this operation mode change processing routine, the newly selected operation mode is read, and initial values are set in the thinning circuit 1a and the interpolation circuit 3c in accordance with the read operation mode. The default values set in the thinning circuit 1a and the interpolation circuit 3c are stored in the ROM 27 at the time of factory shipment. When the user changes the set value, the correspondence of the changed part is recorded in the RAM 28 together with a flag indicating the change.
[0043]
FIG. 3 is a diagram for explaining an example of correspondence between operation modes and setting values of the thinning method and the interpolation method.
[0044]
Here, four types of operation modes are defined: EVF, shooting, playback, and videophone. The thinning method is divided into resolution (indicated as size in the figure) and frame rate (indicated as frame in the figure), and the interpolation method shows only resolution. This is because in this embodiment, the frame rate is constant because the display is NTSC output. In the resolution thinning / interpolation method, the case of vertical / horizontal thinning / interpolation is indicated as “CIF”, and the case of vertical / horizontal thinning / interpolation is indicated as “QCIF”. The frame rate is shown as 30 frames / s (frame / s) if 30 frames per second. Further, in the case of indicating a stopped state, “−” is illustrated.
[0045]
According to the example shown in FIG. 3, when the new operation mode read by the operation mode change routine is the EVF mode, the resolution thinning / interpolation method is “CIF” and the frame rate is set to 30 frames / s. To do. In the shooting mode, the display is stopped, and the image capture is set to capture only one frame of VGA. Further, in the reproduction mode, the image capturing is stopped and “VGA” is displayed as the display. In the videophone mode, the resolution thinning / interpolation method is “QCIF” and the frame rate is set to 15 frames / s. The CPU 5 reads data corresponding to the contents of FIG. 3 from the ROM 27 or RAM 28 and obtains the setting of the thinning method in the thinning circuit 1a and the interpolation method in the interpolation circuit 3c.
[0046]
Next, how the settings of the clock generators 19 to 22 and the clock gate circuits 23 to 26 are controlled will be described.
[0047]
The clock generator 19 outputs a 13.5 MHz clock signal as a pixel clock in response to an ON signal from the CPU 5. This pixel clock is normally on (output), but in the reproduction mode, it is not necessary to newly capture an image signal, and is turned off.
[0048]
The clock generator 20 can generate clocks of four kinds of frequencies by a 2-bit clock selection signal from the CPU 5. That is, when the selection signal is “00”, the generation of the clock is 0 MHz, that is, the generation of the clock is stopped. When the selection signal is “01”, the clock of 50 MHz is output. When the selection signal is “10”, the clock of 100 MHz is output. In the case of “11”, a clock of 150 MHz is output. This 2-bit selection signal is controlled by a control program stored in the ROM 27, read out by the CPU 5, and executed. That is, the amount of image data to be processed per unit time differs depending on the resolution of the operation mode and the image data to be processed. For example, in the EVF mode, the VGA operates at 100 MHz, and the CIF and QCIF operate at 50 MHz. In the telephone mode, control is performed such that the VGA is operated at 150 MHz, the CIF is operated at 100 MHz, and the QCIF is operated at 50 MHz.
[0049]
The clock generator 21 is activated / stopped by an on / off signal from the CPU 5, and the frequency of the generated clock is changed by a control signal from the FIFOs 1b, 2b, 3b even in the activated state.
[0050]
FIG. 4 is a block diagram illustrating an example of the clock generator 21.
[0051]
Reference numeral 21a denotes a clock source oscillator which constantly generates an 80 MHz clock. Reference numeral 21b denotes a clock ½ divider which receives an 80 MHz clock signal and outputs a 40 MHz clock signal. Reference numeral 21c denotes a clock ½ divider which receives a 40 MHz clock signal and outputs a 20 MHz clock signal. Reference numeral 21d denotes a clock ½ divider which receives a 20 MHz clock signal and outputs a 10 MHz clock signal. A clock selector 21e outputs one clock from the four clock inputs A, B, C, and D to the output terminal Out in response to the selection signals SelA, SelB, SelC, and SelD.
[0052]
FIG. 5 is a diagram for explaining clock signal selection processing in the clock selector 21e.
[0053]
The priority increases in the order of the selection signals SelA, SelB, SelC, and SelD. For example, when SelD is “1”, the clock signal input to the D terminal is output to the Out terminal regardless of the state of other selection signals. . Here, the clock signals having the aforementioned frequencies of 10 MHz, 20 MHz, 40 MHz, and 80 MHz are input to the inputs A, B, C, and D, respectively. The output of the AND circuit 21f is connected to the terminal SelA, the output of the OR 21g is connected to the terminal SelB, the output of the OR 21h is connected to the terminal SelC, and the output of the OR 21I is connected to the terminal SelD. The pointer status signals of the FIFOs 1b, 2b, 3b are connected to the inputs of the AND 21f, OR 21g, 21h, 21i, respectively. The meaning of each pointer status signal will be described with reference to FIG. 6, which is a configuration diagram of an example of FIFO 1b, FIG. 7, which is a configuration diagram of an example of FIFO 2b, and FIG. 8, which is a configuration diagram of an example of FIFO 3b.
[0054]
FIG. 6 is a block diagram illustrating a configuration example of the FIFO 1b according to the present embodiment.
[0055]
The FIFO 1b includes a synchronous dual port SRAM 1b0, a write control circuit 1b1, a write address generation (pointer generation) circuit 1b2, a read control circuit 1b3, a read address generation (pointer generation) image path 1b4, and a pointer status generation circuit 1b5. .
[0056]
The dual port SRAM 1b0 is, for example, a 128 (word) × 8 (bit) dual port SRAM. When a write enable signal (write en) is input from the thinning circuit 1a, the dual port SRAM 1b0 is synchronized with the CCD pixel clock (ccd clk). WRITE DATA, which is CCD data, is written to the memory address output from the write address generation (pointer generation) circuit 1b2. Thus, after one image data is written to the dual port SRAM 1b0, the write address output from the write address generation circuit 1b2 is incremented by one. The read operation starts from the address indicated by the pointer generated by the read address generation (pointer generation) circuit 1b4 in synchronization with the bus clock (bus clk) when the read enable signal (read en) is input from the bus interface circuit 1c. READ DATA is output.
[0057]
After one image data is read in this way, the read address output from the read address generation circuit 1b4 is incremented by one. The pointer status circuit 1b5 outputs the status of the FIFO 1b by calculating the absolute value of the difference between the write pointer (address) and the read pointer (address). For example, when the absolute value of the difference is “0”, it indicates that the FIFO 1b is empty, so that the “1b: Empty” signal is output. When the absolute value of this difference is 80% or more of the capacity of the FIFO 1b (128 words), it indicates that the valid data of the FIFO 1b is 20% or less of the capacity of the FIFO 1b, so that a “1b <20%” signal is output. To do. Similarly, when the valid data of the FIFO 1b is between 20% and 40%, a “1b> 20%” signal is output, and when it is between 40% and 60%, a “1b> 40%” signal is output. In the case of 60% or more, a “1b> 60%” signal is output.
[0058]
FIG. 7 is a block diagram showing the configuration of the FIFO 2b.
[0059]
The FIFO 2b is realized as a combination of the FIFO in the direction from the bus interface circuit 2a to the DSP 2c and the FIFO in the reverse direction. The FIFO from the bus interface circuit 2a to the DSP 2c includes a synchronous dual port SRAM 2b0, a write control circuit 2b1, a write address generation (pointer generation) circuit 2b2, a read control circuit 2b3, a read address generation (pointer generation) circuit 2b4, and a pointer status generation. A circuit 2b5 is provided.
[0060]
On the other hand, the FIFO from the DSP 2c to the bus interface circuit 2a includes a synchronous dual port SRAM 2b6, a write address generation (pointer generation) circuit 2b7, a read address generation (pointer generation) circuit 2b8, a write control circuit 2b9, a read control circuit 2b10, and a pointer. A status generation circuit 2b11 is provided.
[0061]
The dual port SRAM 2b0 is, for example, a 128 (word) × 8 (bit) dual port SRAM. When a write enable signal (write en) is input from the bus interface circuit 2a, the dual port SRAM 2b0 is synchronized with the bus clock (bus clk). WRITE DATA, which is bus transfer data, is written to the memory address generated by the write address generation (pointer generation) circuit 2b2. After the data is written, the write pointer (address) output from the write address generation circuit 2b2 is incremented. In the read operation, when a read enable signal (read en) is input from the DSP 2c, READ DATA is read from the address indicated by the pointer generated by the read address generation (pointer generation) circuit 2b4 in synchronization with the DSP clock (dsp clk). Since it is output, this is read out. After reading this data, the read pointer output from the read address generation circuit 2b4 is incremented. The pointer status circuit 2b5 outputs the status data of the FIFO 2b by calculating the absolute value of the difference between the write pointer and the read pointer.
[0062]
  The dual port SRAM 2b6 is, for example, a 128 (word) × 8 (bit) dual port SRAM. When a write enable signal (write en) is input from the DSP 2c, the bus transfer data is synchronized with the DSP clock (dsp clk). WRITE DATA is written to the memory address generated by the write address generation (pointer generation) circuit 2b7.ThisAfter the data is written, the write pointer output from the write address generation circuit 2b7 is incremented. In the read operation, when a read enable signal (read en) is input from the bus interface circuit 2a, the memory address indicated by the pointer generated by the read address generation (pointer generation) circuit 2b8 is synchronized with the bus clock (bus clk). Since READ DATA is output from, read this.ThisAfter reading the data, the read pointer output from the read address generation circuit 2b8 is incremented. The pointer status circuit 2b11 outputs the status of the FIFO 2b by calculating the absolute value of the difference between the write pointer and the read pointer.
[0063]
The pointer status signal of the FIFO 2b is generated by calculating the outputs of the pointer status circuits 2b5 and 2b11. For example, if the absolute values of the differences between the two FIFO pointers are both “0”, this indicates that the FIFO 2b is empty, so that the AND2b12 outputs a “2b: Empty” signal. If the absolute value of the difference between the two FIFO pointers is 80% or more of the capacity of the FIFO 2b (128 words), it indicates that the valid data of the FIFO 2b is 20% or less of the capacity of the FIFO 2b. % "Signal is output. Similarly, when the valid data of at least one FIFO is between 20% and 40%, a “2b> 20%” signal is output by OR2b14, and when at least one is between 40% and 60%, OR2b15 A “2b> 40%” signal is output, and if at least one is 60% or more, a “2b> 60%” signal is output by OR2b16.
[0064]
FIG. 8 is a block diagram showing the configuration of the FIFO 3b.
[0065]
As shown in FIG. 8, the FIFO 3b includes a synchronous dual port SRAM 3b0, a write control circuit 3b1, a write address generation (pointer generation) circuit 3b2, a read control circuit 3b3, a read address generation (pointer generation) circuit 3b4, and a pointer status generation circuit 3b5. It has.
[0066]
  Here, 3b0 is, for example, a 128 (word) × 8 (bit) dual port SRAM. When a write enable signal (write en) is input from the bus interface circuit 3a, it is synchronized with the bus clock (bus clk). WRITE DATA, which is bus transfer data, is written to the memory address generated by the write address generation (pointer generation) circuit 3b2. After this data writing, the write pointer output from the write address generation circuit 3b2 is incremented. The read operation is performed from the memory address indicated by the pointer generated by the read address generation (pointer generation) circuit 3b4 in synchronization with the display clock (disp clk) when the read enable signal (read en) is input from the interpolation circuit 3c. Read DATA because it outputs READ DATA.ThisAfter reading the data, the read pointer output from the read address generation circuit 3b4 is incremented. The pointer status circuit 3b5 outputs the status of the FIFO 3b by calculating the absolute value of the difference between the write pointer and the read pointer. For example, if the absolute value of the difference is “128”, it indicates that the FIFO 3b is full, so a “3b: full” signal is output, and the absolute value of the difference is 20% or less of the capacity of the FIFO 3b (128 words). Indicates that the valid data in the FIFO 3b is 80% or more of the FIFO capacity, so that a “3b> 80%” signal is output. Similarly, when the valid data of the FIFO 3b is between 80% and 60%, a “3b <80%” signal is output, and when it is between 60% and 40%, a “3b <60%” signal is output. In the case of 40% or less, a “3b <40%” signal is output.
[0067]
The operation of the clock generator 21 will be described with reference again to FIG.
[0068]
A pointer status signal input from each FIFO is input to AND 21f, OR 21g, 21h, and 21i. Here, the FIFOs 1b and 2b indicate that the smaller the valid data in the FIFO, the more the transfer capability of the bus.
[0069]
On the other hand, since the FIFO 3b prefetches data as long as there is free capacity, the closer the FIFO 3b is to FULL, the more the bus transfer capacity is. The AND 21f receives the “1b <20%” signal, the “2b <20%” signal, and the “3b> 80%” signal. When all the inputs are “1”, the bus transfer is performed for all the bus masters. It shows that there is enough ability. Therefore, since the clock frequency can be set to the minimum, the output of AND2f is used as the SelA input, and a clock signal having a frequency of 10 MHz is selected.
[0070]
When the amount of data to be transferred next increases and at least one of FIFO1b or FIFO2b exceeds 20% or FIFO3b falls below 80%, the output of OR21g becomes “1” and a clock signal with a frequency of 20 MHz. Is selected. When the amount of data to be transferred further increases and at least one of FIFO1b or FIFO2b exceeds 40% or FIFO3b falls below 60%, the output of OR21b becomes “1” and the clock signal with a frequency of 40 MHz is selected. Is done. If the amount of data to be transferred further increases and at least one of FIFO1b or FIFO2b exceeds 60% or FIFO3b falls below 40%, the output of OR21i becomes “1” and the clock signal with a frequency of 80 MHz is selected. Is done. That is, the frequency of the bus clock can be automatically increased by dynamically detecting that the data transfer capability of at least one bus master has been insufficient. In order to stop the bus clock of the clock generator 21, the CPU 5 sets the clock on signal to “0”. As a result, the bus clock selected by the selector 21e is gated by the AND gate 21j, and the output of the clock signal is stopped.
[0071]
On the other hand, the clock generator 22 outputs a clock signal having a frequency of 13.5 MHz as a pixel clock in response to an ON signal from the CPU 5.
[0072]
Next, operations of the clock gate circuits 23, 24, and 25 will be described with reference to a configuration diagram of an example of the clock gate circuit.
[0073]
FIG. 9 is a circuit diagram illustrating the clock gate circuit 23.
[0074]
As shown in FIG. 9, the clock gate circuit 23 gates the bus clock (bus clk) with an inverted signal of the “1b: Empty” signal (FIG. 6) which is an empty signal of the FIFO 1b. That is, when there is no captured data of the image capture controller 1, the operation clock of the bus interface circuit 1a of the image capture controller 1 and the read clock of the FIFO 1b are automatically stopped.
[0075]
FIG. 10 is a circuit diagram illustrating the clock gate circuit 24.
[0076]
As shown in FIG. 10, the clock gate circuit 24 gates the bus clock (bus clk) with an inverted signal of the “2b: Empty” signal (FIG. 7) which is the empty signal of the FIFO 2b. That is, when there is no processing data of the signal processor 2, the operation clock of the bus interface circuit 2a of the signal processor 2 and the bus side clock of the FIFO 2b are automatically stopped.
[0077]
FIG. 11 is a circuit diagram illustrating the clock gate circuit 25.
[0078]
As shown in FIG. 11, the clock gate circuit 25 gates the bus clock (bus clk) with an inverted signal of the “3b: full” signal (FIG. 8) which is a full signal of the FIFO 3b. That is, when the display data of the display controller 3 cannot be read any more, the operation clock of the bus interface circuit 3a of the display controller 2 and the write clock of the FIFO 3b are automatically stopped.
[0079]
The clock generators 19 to 22 and the clock gate circuits 23 to 26 corresponding to the frame rate are set by the CPU 5 controlling the clock generator and the clock gate circuit for each frame. For example, if the frame rate is set to 10 frames / s in the EVF mode, the image capture controller 1 and the signal processor 2 need only process 1 frame per 3 frames. During the middle two frames, the clock gate circuits 23 and 24 and the clock generator 20 stop the supply of the clock signal to the image capture controller 1 and the signal processor 2.
[0080]
According to the setting of the thinning method and interpolation method and the clock frequency control as shown in this embodiment, the resolution and frame rate desired by the user can be set flexibly in all operation modes, and the resolution and frame set by the user can be set. Since the clock frequency for normal operation at the rate is automatically set, the maximum power saving effect can be obtained in any operating situation.
[0081]
Note that the present invention can be applied to a system (for example, a copier, a facsimile machine, etc.) composed of a single device even if it is applied to a system composed of a plurality of devices (for example, a host computer, interface device, reader, printer, etc.). May be.
[0082]
Another object of the present invention is to supply a storage medium (or recording medium) in which a program code of software that implements the functions of the above-described embodiments is recorded to a system or apparatus, and the computer (or CPU) of the system or apparatus. Or MPU) can also be achieved by reading and executing the program code stored in the storage medium. In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the program code constitutes the present invention. Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an operating system (OS) running on the computer based on the instruction of the program code. A case where part or all of the actual processing is performed and the functions of the above-described embodiments are realized by the processing is also included.
[0083]
Further, after the program code read from the storage medium is written in a memory provided in a function expansion card inserted into the computer or a function expansion unit connected to the computer, the function is determined based on the instruction of the program code. This includes the case where the CPU of the expansion card or the function expansion unit performs part or all of the actual processing and the functions of the above-described embodiments are realized by the processing.
[0084]
As described above, according to the portable videophone terminal device of the present embodiment, flexible image quality control according to the user's usage mode can be realized very easily, and the maximum in any operation mode. There is an effect that power consumption can be reduced as much as possible.
[0085]
【The invention's effect】
  As described above, according to the present invention, the frequency of the clock signal supplied to each of the plurality of processing means iseachProcessing meansOf the amount of data stored in the memory ofBy switching according to the power consumption, the power consumption of the entire apparatus can be suppressed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a portable videophone terminal device according to an embodiment of the present invention.
FIGS. 2A and 2B are a timing chart (A) illustrating an example of the operation of the thinning circuit according to the present embodiment and a diagram (B) illustrating a latch clock (Latch Clock) generation circuit; FIGS.
FIG. 3 is a diagram for explaining a correspondence between an operation mode, a thinning method, and an interpolation method.
FIG. 4 is a block diagram showing a configuration of a clock generator according to the present embodiment.
FIG. 5 is a diagram for explaining clock selection in the clock selector of FIG. 4;
FIG. 6 is a block diagram showing a configuration example of a FIFO 1b according to the present embodiment.
FIG. 7 is a block diagram showing a configuration example of a FIFO 2b according to the present embodiment.
FIG. 8 is a block diagram showing a configuration example of a FIFO 3b according to the present embodiment.
FIG. 9 is a diagram showing a configuration example of a clock gate circuit 23 according to the present embodiment.
FIG. 10 is a diagram showing a configuration example of a clock gate circuit 24 according to the present embodiment.
FIG. 11 is a diagram showing a configuration example of a clock gate circuit 25 according to the present embodiment.

Claims (6)

A clock generation source for generating clock signals of a plurality of frequencies each having a different frequency;
Selecting means for selecting any one of a plurality of clock signals output from the clock generation source;
A plurality of processing means each having a memory for storing processed or processing target data and operated by a clock signal from a clock generation source selected by the selection means;
Selection for acquiring information on the amount of data stored in the memory included in each processing unit of the plurality of processing units, and controlling to select a clock signal for each processing unit in accordance with the acquired information on the amount of data Control means;
An information processing apparatus comprising: One of the plurality of processing means is:
An input means for inputting a captured image signal;
And a thinning means for thinning the image signal input by said input means,
The information processing apparatus according to claim 1, wherein the benzalkonium be stored an image signal thinned out by the thinning means in the memory. One of the plurality of processing means is:
And interpolating means for interpolating the image signals stored in said memory,
The information processing apparatus according to claim 2, further comprising display means for displaying an image based on the image signal interpolated by the interpolation means. The memory is a FIFO, information of the amount of data information processing apparatus according to any one of claims 1 to 3, characterized in that the information representative of the percentage of valid data occupying the FIFO. Each is a method of controlling an information processing apparatus having a memory for storing processed or processed data and having a plurality of processing means that operate in response to a clock signal from a clock generation source,
A selection step of selecting any one of a plurality of clock signals having a plurality of frequencies output from a clock generation source generating a clock signal having a plurality of frequencies different from each other in order to operate each processing unit of the plurality of processing units ; ,
Acquires the data amount of information stored in the memory of the respective processing means of the plurality of processing means, the acquired selection control for controlling so as to select the clock signal for each processing unit in accordance with the data amount of the information Process,
A method for controlling an information processing apparatus, comprising : A computer-readable storage medium storing a program for causing a computer to execute the control method of the information processing apparatus according to claim 5 .

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