JP2001238190A - Image processing apparatus and its control processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress power consumption of an image processing apparatus by controlling a clock signal and a power supply voltage applied to a processing circuit corresponding to each processing block in response to an operation mode for the processing apparatus. SOLUTION: In the image processing apparatus where an image processor 2 applies image processing to an image signal captured by an image capturing controller 1 and a display controller 3 displays the processed image, the image capturing controller 1 captures image data with a resolution designated in an operating mode and at a frame rate and the display controller 3 displays the image data with a resolution at a frame rate designated in response to the operation mode. A CPU 5 decides a minimum power supply voltage at which this apparatus can be operated and a frequency of a clock signal on the basis of a setting value stored in a ROM 36 and controls the voltage and the frequency of the clock signal outputted from clock generators 1-23 and regulators 28-32 supplying the clock signal and the power supply voltage to each controller.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus which can be applied to, for example, a digital still camera, a video telephone terminal, or a notebook PC with a built-in camera, and an operation control processing method in the apparatus.

[0002]

2. Description of the Related Art In recent years, digital still cameras are typified by advances in technologies such as miniaturization and power saving of solid-state imaging devices such as CCDs, and high integration, high functionality, and low power consumption of LSIs. Portable imaging devices that can be driven by such batteries have come into general use. Further, a portable videophone terminal having a built-in mobile phone function has been developed. In such a battery-driven imaging device, various devices have been devised to extend the operation time using a battery. For example, the remaining battery level is always displayed, and when the remaining level becomes low, the user is urged to frequently turn off the power. Alternatively, power supply or clock supply to a non-operating part is cut off according to the operation mode selected by the user.

Further, in the prior art, the frame rate and resolution of an image to be shot are fixed or can be set by the user at best, and are not linked to the power saving function.

In general, in a photographing apparatus, as the frame rate and the resolution of a photographed image increase, the amount of image data to be processed per unit time increases, so that an electronic circuit handling the image requires a high operation clock frequency. In addition, the power supply voltage cannot be reduced as the electronic circuit operates at a higher frequency. Since power consumption is proportional to the clock frequency and proportional to the square of the power supply voltage, an increase in the frame rate and resolution of an image results in an increase in power consumption.
Therefore, in order to reduce power consumption, it is better to reduce the frame rate and resolution as much as possible.

[0005]

However, the requirements for the frame rate and resolution of an image signal to be captured differ depending on the operation mode of the photographing apparatus. For example, in the electronic viewfinder mode (hereinafter referred to as EVF mode), it is desirable to display a moving image as smooth as possible, but the screen displaying the electronic view image is often a small screen built in the device. Therefore, the higher the frame rate, the better, but the resolution is not so required. In still image capture mode (hereinafter referred to as shooting mode), the frame rate may be the lowest (still images may be used),
The highest resolution is required. In the reproduction mode, the image signal is not taken in, and only the image is displayed at the maximum resolution. Further, in the videophone mode, both frame rate and resolution are determined by the data transfer capabilities of the telephone line.

As is clear from the above example, each of the functional blocks constituting such a photographing apparatus, such as a photographing block, an image processing block, and a display block, performs processing per unit time according to the operation mode. The amount of data to be different is different and it is not necessary to always operate at the maximum frequency.
Nevertheless, in the conventional technology, the power supply to the functional blocks that are completely inactive has only been turned off in order to save the power of the device, so that effective power consumption reduction processing can be performed. could not.

The present invention has been made in view of the above-mentioned conventional example, and controls a clock signal and a power supply voltage to be supplied to a processing circuit corresponding to each processing block in accordance with an operation mode in which the apparatus operates, thereby enabling the apparatus to operate. It is an object of the present invention to provide an image processing apparatus capable of suppressing power consumption of the image processing apparatus and a control processing method thereof.

Another object of the present invention is to provide an image processing apparatus capable of automatically realizing optimum power saving according to the operation mode of the apparatus, and a control processing method therefor.

[0009]

In order to achieve the above object, an image processing apparatus according to the present invention has the following arrangement.
That is, an image processing apparatus having a plurality of operation modes, an instruction unit for instructing any one of the plurality of operation modes, and a plurality of processing units each having an independent processing circuit and performing a different process. A clock signal supply unit for supplying a clock signal of a predetermined frequency to a processing circuit corresponding to the plurality of processing units; a power supply unit for supplying a power supply voltage to a processing circuit corresponding to the plurality of processing units; And control means for controlling the frequency of the clock signal supplied from the clock signal supply means and the power supply voltage supplied from the power supply means in accordance with the operation mode specified by (1).

To achieve the above object, a control processing method in an image processing apparatus according to the present invention includes the following steps. That is, a control processing method in an image processing apparatus having a plurality of operation modes, wherein an instruction step of instructing any one of the plurality of operation modes and a plurality of processing circuits respectively executing independent and different processes are provided. A clock signal supplying step of supplying a clock signal having a frequency of
A power supply step of supplying a power supply voltage to each of the plurality of processing circuits; and a frequency of the clock signal supplied in the clock signal supply step and the power supply step corresponding to the operation mode instructed in the instruction step. And a control step of controlling the power supply voltage supplied in the step (c).

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a configuration of a portable videophone terminal according to Embodiment 1 of the present invention. In FIG. 1, among the lines connecting the functional blocks, the connection of the data system is shown by a thick solid line, the connection of the control system is shown by a thin solid line, and the connection of the clock system is shown by a dotted line. However, not all connections are illustrated, but only typical wiring connections required for description are illustrated.

The main components of the video telephone terminal apparatus are an image capture controller 1 for executing a process relating to capture of a captured image signal, and a signal processor for executing image processing on image data generated from the image signal. 2, a display controller 3 for performing processing related to image display based on image data, a memory controller 4 for performing memory control for storing image data in a memory, and a CPU 5 for controlling the entire apparatus.

First, as a typical operation mode, EVF
The operation will be described for each of (electronic viewfinder) mode, shooting mode, playback mode, and videophone mode.

[Explanation of Image Capture Controller 1] When an image to be imaged is formed on the CCD 7 via the lens module 6, an image signal corresponding to the image is output from the CCD 7. This lens module 6
Includes a lens, a drive system for an auto iris, a drive system for an auto focus, and the like. The control of these drive systems is performed by the CPU 5 by a control signal (not shown). The image signal output from the CCD 7 is input to a preprocessing module (CDS / AGC) 8. In the first embodiment, the number of effective pixels captured by the CCD 7 is 640.
× 480 pixels (equivalent to VGA). The preprocessing module 8 has CDS (correlated double sampling) and AGC (automatic gain control) functions. Clocks and timing signals for the CCD 7 and the preprocessing module 8 are supplied from a timing generation circuit (TG) 9. The image data pre-processed by the pre-processing module 8 is A /
The data is converted into 10-bit digital data by a D converter (ADC) 10 and input to the image capture controller 1 in synchronization with a pixel clock (Pixel Clock) generated by a timing generation circuit (SG) 11.

The image data input to the image capturing controller 1 is subjected to a thinning process by a thinning circuit 1a.
Data resulting from the thinning is written to the FIFO 1b. The thinning method in the thinning circuit 1a is set in advance by the CPU 5 based on a control signal (not shown).

FIG. 2A is a timing chart showing an example of the operation of the thinning circuit 1a. Thinning circuit 1a
Is the pixel clock (Pixel C) input from SG11.
lock), and a line counter (Line Num) for counting the number of image lines based on a horizontal / vertical synchronization signal (not shown).
The digital image data input from the ADC 10 is latched based on the thinning method set in advance by the PU 5 and the count values of these counters, and a clock (Latch Clock) for writing to the FIFO 1b is generated.

In the example shown in FIG. 2A, data of 640 pixels horizontally and 480 lines vertically is 1
/ 2 thinning out (320 × 240 pixels: CIF
(Equivalent). Therefore, the active line is an odd line, and a signal indicating this period is an active line.
Signal. The effective pixels are odd pixels, and a signal indicating this is an Active Pixel signal.

Based on these signals, a logical product of a Pixel Clock, an Active Line signal, and an Active Pixel signal is obtained as shown in FIG. 2B, and this is a Latch Clock signal for writing to the FIFO 1b. In FIG. 2A, the data written to the FIFO 1b is a Data to FIFO.
It is.

It is to be noted that the thinning circuit 1a can be configured to also have a frame thinning function. In this case, an additional frame counter is provided. For example, when capturing one frame every four frames, an active frame signal is generated when the frame counter is “multiple of 4 + 1”,
What is necessary is just to add to the input of the AND circuit shown in FIG.

Bus interface circuit (BUS IF) 1c
Detects a state in which the FIFO 1b is not empty (any data is written), generates a bus transaction for writing data on the main bus (MB), and transfers the data read from the FIFO 1b to the memory controller 4. . The bus interface circuit 1c normally operates with a bus clock that is asynchronous with the image capture clock (Latch Clock). Therefore, the read clock of the FIFO 1b is the write clock (Latch
Clock), the FIFO 1b is provided to buffer this asynchronous data transfer.

A plurality of other bus masters that generate bus transactions are connected to the main bus MB (the signal processor 2, the display controller 3,
CPU5), there is a possibility that a plurality of bus transactions may occur at the same time. Therefore bus arbiter 12
Arbitrates the bus so that only one bus master can generate a bus transaction at a time.

[Description of Memory Controller 4] The memory controller 4 is a bus interface circuit (BUS IF).
At 4a, a bus transaction is received, and image data to be stored and a memory address at which the image data is to be stored are written to the temporary FIFO 4b. The SDRAM interface circuit (SDRAM IF) 4c outputs various control signals to the SDRAM 13, which is an image memory, and outputs the memory address and image data stored in the FIFO 4b to the SDRAM 13. Here, since the memory clock can be asynchronous with the bus clock,
Buffered by O4b. The SDRAM interface circuit 4c also operates in synchronization with the memory clock, and stores the memory address and data read out from the read port of the FIFO 4b in synchronization with the memory clock in the SD card.
Control for writing to the RAM 13 is performed.

[Explanation of the Signal Processor 2] The signal processor 2 generates a bus transaction for reading image data, and captures the image data by an image capture controller by a bus interface circuit (BUS IF) 2a operated by a bus clock. The read image data is read from the image memory. The read image data is written to the work memory 2b in synchronization with the bus clock. The DSP (digital signal processor) 2c
It operates with a clock (DSP clock) different from the bus clock, accesses data in the work memory 2b in synchronization with the DSP clock, performs YC separation by color matrix processing, and subsequently performs color correction, edge enhancement,
Performs processing such as white balance adjustment and gamma correction.
The image data thus obtained is used not only for display on the monitor 15 but also for image compression. When the bus interface circuit 2a is used for display on the monitor 15, the bus interface circuit 2a is activated so that the display controller 3 can read the data, and a write bus transaction is generated.
The data is transferred to the DRAM 13.

[Explanation of EVF Mode] In the EVF mode, the above-described operation is repeated for each frame, so that a continuous frame is taken into the image memory 13.
As an area of the image memory where the signal processor 2 writes image data, an operation of overwriting the same area may be used. The display controller 3 obtains display data by reading image data from the area of the image memory. that time,
The display controller 3 generates a bus transaction for reading image data, and reads image data to be displayed from the image memory 13 by a bus interface circuit (BUS IF) 3a operated by a bus clock. The display controller 3 further inputs the read image data to the write port of the FIFO 3b in synchronization with the bus clock. Generally, a display device, such as an NTSC monitor or a liquid crystal display, needs to constantly refresh the screen. Therefore, during a valid screen period, the display device must continue to operate at a certain pixel clock. Therefore, the bus interface circuit 3a keeps reading image data from the image memory until the FIFO 3b becomes full.

Next, the interpolation circuit 3c reads out image data from the FIFO 3b in synchronization with the display pixel clock.
The interpolation circuit 3c has a line memory,
The image data read from b is first stored in this line memory. The image data stored in the line memory is sequentially read from the head when no interpolation is performed.
The data is input to the TSC encoder 3d, and is converted into video data in the NTSC format. In this case, the interpolation circuit 3c
Reads the image data for one pixel from the FIFO 3b immediately after the image data for one pixel is read. Here, in the case of performing the line interpolation, the line data of (number of lines to be interpolated-1) is transmitted to the NTSC encoder 3d, and then the next line of image data of one pixel is transmitted to the NTSC encoder 3d. FIFO3b
From the image data of one pixel. For example, when performing quadruple interpolation in the line direction, three lines are displayed by the image data from the line memory, and when displaying the fourth line, F is displayed while displaying the line.
The operation of reading the image data of the next line from the IFO 3b is performed.

The NTSC encoder 3d uses NTSC
The video data converted to the format is converted to an analog signal by a D / A converter (DAC) 14 and then converted to an analog signal.
Displayed by the monitor 15 of the TSC.

By performing the above operation continuously for each frame, the operation becomes an EVF mode operation. In the EVF mode, it is necessary to read out image data of each frame even if the image capturing controller 1 performs frame thinning. In this case, the displayed image is dropped, but the monitor 15 needs to keep operating at a constant frame rate.

[Explanation of Shooting Mode] Next, the operation in the shooting mode will be described. In this shooting mode, after capturing one frame of image data, this image data is
The data is G-compressed and recorded in an external storage such as the memory card 17.

First, when the CPU 5 detects that the shutter button of the switch group 16 including the shutter button or the like has been pressed, the CPU 5 fetches the next one frame of image data to the image fetch controller 1 by a control signal (not shown). , So as not to take in the image data of the subsequent frames. Similarly, it notifies the signal processor 2 to perform a compression process on the image data of the next one frame.

The image capture controller 1 operates in the aforementioned E
Unlike the case of the VF mode, when the image of one frame is fetched and the image data is transferred to the image memory 13,
Pause the operation. The signal processor 2 reads out the image data for one frame stored in the memory 13, and performs the YC separation, the color correction, the edge enhancement, and the like in the same manner as when the image data for display is generated in the EVF mode.
Image processing such as white balance adjustment and gamma correction is performed. Thereafter, the coded data obtained by subjecting the image data to a DCT operation process, a quantization process, a variable length coding process, etc., is immediately stored in an area other than the display image data area in the image memory 13. Write to.

The CPU 5 reads out the image data stored in the image memory 13 and adds necessary markers and the like to the JP5.
After being converted into EG data, it is stored in the memory card 17.
When the storage of the image data for one frame is completed in this way, the CPU 5 instructs the image capturing controller 1 to
A notification is issued to restart the capture of the image signal in the EVF mode.

The encoded image data stored in the memory card 17 can be accessed from a PC or the like via a communication circuit 18 for realizing an interface with a host computer such as a PC. In the first embodiment, the communication circuit 18 includes, for example, a serial interface, a USB,
rDA, mobile phone module, etc.

[Explanation of Reproduction Mode] Next, the operation of the reproduction mode will be described. In this reproduction mode, the operation of the image capture controller 1 is stopped. The CPU 5 reads out the coded compressed data stored in the memory card 17 and writes it to the SDRAM 13. Signal processor 2
Reads out the code data written in the SDRAM 13 and performs image expansion processing such as decoding, inverse quantization, and inverse DCT conversion to obtain displayable image data, and then returns to SD
Write back to RAM13. The display controller 3 reads out the displayable data from the SDRAM 13 and performs a display operation.

[Explanation of Video Phone Mode] Next, the operation of the video phone mode will be described. In the above-described shooting mode, the image capturing controller 1 temporarily stops operation after capturing one frame of image data. However, in this videophone mode, the image data of successive frames is fetched without interrupting the image data fetching process. The capture frame rate at this time is
5 is determined on the basis of the thinning method set in step S5. The image data thus captured is subjected to image processing and image compression / encoding processing by the signal processor 2 by the same processing as in the shooting mode, and the SDRA
Written to M13. The code data thus written in the SDRAM 13 is read out by the CPU 5, and after a predetermined marker or the like is inserted, the code data is transmitted to the other party through the telephone line by the mobile phone module of the communication circuit 18.

On the other hand, the code data received from the other party through the telephone line
The data is written to the SDRAM 13 via the PU 5. The signal processor 2 reads out the code data written in the SDRAM 13 and decodes, dequantizes,
After performing image expansion processing such as conversion to obtain displayable image data, the image data is written back to the SDRAM 13 again. The display controller 3 performs a display operation such that image data to be displayed is read from the SDRAM 13 and displayed on the monitor 15.

As described above, the image picked up by the CCD 7 can be transmitted to the communication partner, and the image data sent from the communication partner can be received and displayed on the monitor 15.

[Description of Clock] Next, the clock supplied to each of the image capture controller 1, the signal processor 2, the display controller 3, and the memory controller 4 will be described.

Clock generators (CG) 19, 20, 21,
Reference numerals 22 and 23 denote variable clock generators that generate a clock signal having a frequency set by the CPU 5. The clock generator (CG (C)) 19 includes an SG 11 and an image capturing unit (the thinning circuits 1 a, F
An operation clock for the IFO 1b) is generated. The clock generator (CG (D)) 20 generates an operation clock of the DSP 2c. The clock generator (CG (B)) 21 generates an operation clock for the bus interface of each controller. The clock generator (CG (L)) 22 generates operation clocks for the FIFO 3b of the display controller 3, the interpolation circuit 3c, the NTSC encoder 3d, and the D / A converter 14. The clock generator 23 (CG (M)) is provided with the FIFO 4b, the SDRAM / IF 4c and the S
An operation clock for the DRAM 13 is generated.

The bus clock output from the clock generator 21 is supplied to the bus interface circuit of each controller. The clock gate circuits (G) 24 and 2 are provided so that the clock supply can be stopped for each controller.
5, 26, 27 are provided. These clock gate circuits (G) are controlled by the CPU 5 by a control signal (not shown).

[Explanation Regarding Setting of Each Controller Corresponding to Power Supply Information] Next, the power supply voltage supplied to each controller will be described.

Regulators 28, 29, 30, 31, 3
Numerals 2 denote variable voltage regulators each generating a voltage set by the CPU 5, and a regulator (REG (C)) 2
Reference numeral 8 designates a regulator (RE
G (S)) 29 to the signal processor 2, regulator (REG (D)) 30 to the display controller 3, regulator (REG (M)) 31 to the memory controller 4, and regulator (REG (CPU)) 32 Supplies a power supply voltage to the CPU 5. A battery 33 is commonly connected to these regulators 28 to 32.

Next, how to adjust the settings of the thinning circuit 1a, the interpolation circuit 3c, the clock generators 19 to 23, and the regulators 28 to 32 according to the state of the power supply voltage will be described. The operation will be described.

The operation mode is changed by the user operating the switches of the switch group 16. Although various examples of the configuration of the switches of this switch group are conceivable, in this embodiment, the switches are configured by a dial and a push button. That is, the operation mode candidates are sequentially updated and displayed by rotating the dial, and the operation mode candidates are selected by pressing the push button. An interrupt occurs in the CPU 5 due to this candidate selection event, an interrupt processing routine stored in the ROM 36 is executed, and the operation mode change processing is called.

In this operation mode change processing routine, the operation mode newly selected is read. The thinning circuit 1a and the interpolation circuit 3 corresponding to the read operation mode
The factory default value for c is stored in the ROM 36. Here, when the user changes the set value corresponding to each operation mode, the RAM 37 displays the flag indicating the change and the correspondence of the changed portion to the RAM 37.
Is stored.

FIG. 3 is a diagram for explaining each operation mode and the corresponding set values of the thinning method and the interpolation method.

In FIG. 3, EVF is set as the operation mode.
(Electronic viewfinder mode), shooting mode, playback mode, and videophone mode are defined.
Here, the thinning method is divided into a resolution (represented as size in the figure) and a frame rate (represented as frame) in the figure, and the interpolation method represents only the resolution. Because, in the present embodiment, the display is NTS
This is because the frame rate is constant since the output is at C.
Regarding the resolution thinning and interpolation method, the case of vertical / horizontal 1/2 thinning / interpolation is shown as “CIF”, and the vertical / horizontal 1/4 thinning / interpolating method is used.
The case of interpolation is shown as “QCIF”. If the frame rate is 30 frames per second, 30 frames
(frame) / s]. In addition, when indicating a stopped state, it is shown as "-".

According to FIG. 3, when the new operation mode read by the operation mode change processing routine is the "EVF mode", the resolution thinning / interpolation method is "CIF" and the frame rate is 30 [frames]. / S]. In the “shooting mode”, the display is stopped (the interpolation method is “−”), and the image is set so that only one frame of the VGA is captured. In the case of the “playback mode”, the image capturing is stopped and the display is
Display GA. Further, in the case of the "videophone mode", the resolution thinning / interpolation method is "QCIF" and the frame rate is set to 15 [frame / s].

Therefore, in the above-described interrupt processing routine, the CPU 5 transmits data corresponding to the contents shown in FIG.
Read out from the OM 36 or the RAM 37 and perform the thinning-out circuit 1
a) It is possible to obtain the set values of the thinning method and the interpolation method in the interpolation circuit 3c.

As described above, when the thinning-out method and the interpolation method corresponding to each operation mode are obtained, the CPU 5 sets the lowest clock frequency and the lowest power supply voltage that can normally operate the apparatus in the thinning-out method and the interpolation method. Is calculated. The simplest example of this calculation method is a method in which a clock frequency and a power supply voltage are stored in correspondence with each of the thinning methods and the interpolation methods with reference to a table. References shall be used.

This table is stored in the ROM 36, and examples of the contents of the information stored as this table are as shown in FIGS. 4 to 7, for example.

Each of FIGS. 4, 5, 6 and 7 shows E
It shows the frequency of each clock and the voltage value to be set in each regulator corresponding to the resolution thinning method in each of the VF mode, the shooting mode, the reproduction mode, and the videophone mode. “Bus clk” is a clock frequency set in the clock generator 21, “ccd clk” is a clock frequency set in the clock generator 19, “disp clk” is a clock frequency set in the clock generator 22, “dsp cl”
“k” is a clock frequency set in the clock generator 20,
“Mem clk” indicates a clock frequency set in the clock generator 23. Also "ccd vol"
Is a voltage value set in the regulator 28, "dsp vol" is a voltage value set in the regulator 29, "disp vol" is a voltage value set in the regulator 30, and "mem vol"
Indicates voltage values set in the regulator 31.

For example, when the operation mode is changed to the EVF mode, as shown in FIG.
Becomes In this case, referring to the column “CIF” in FIG. 4, 40 MHz is set for the clock generator 21 (bus clk), and the clock generators 19 (ccdclk) and 22 (disp clk) are set.
Is set to 13.5 MHz, and the clock generator 20 (dsp
clk) is set to 100 MHz, and the clock generator 23 (m
em clk) is set to 40 MHz, regulators 28 (ccd vol), 29 (dsp vol), 31 (mem vol) are set to 3.0 V, and regulator 30 (disp vol) is 3.3 V. It turns out that it is good to set each. These setting processes are performed by the CPU 5 reading various set values from the ROM 36 and setting them in each clock generator and regulator.

FIG. 5 is a diagram showing an example of set values in the photographing mode.

It should be noted in FIG. 5 that the clock generator 22 (disp clk) and the regulator 30 (disp vol)
Is the setting. That is, since the display controller 3 does not need to operate in the photographing mode, the supply of the clock signal and the voltage to the display controller 3 is stopped.
Further, the clock gate circuit 26 stops the clock supply to the bus interface circuit 3a of the display controller 3. When the power supply to the display controller 3 is stopped, the signal connected to the main bus MB of the bus interface circuit 3a needs to be electrically isolated. Therefore, it is simpler in terms of circuit to stop the supply of the clock signal while keeping the voltage supply to the display controller 3.

FIG. 6 is a view for explaining the set values in the reproduction mode. In this case, as in the case of the photographing mode,
Clock generator 19 (ccd clk), regulator 28 (ccd
vol), the clock gate circuit (G) 24 is stopped.

FIG. 7 is a diagram for explaining the set values in the video phone mode. In this case, the resolution VGA must not be set because the data amount is too large to process.

FIG. 8 shows the CPU 5 of the image pickup apparatus according to this embodiment.
6 is a flowchart showing an interrupt process by the CPU.

When an operation mode is instructed by operating a switch of the switch group 16, an interrupt is generated for the CPU 5, and the operation mode set by the switches of the switch group 16 is determined in step S1. Next, proceeding to step S2, the ROM 36 is accessed to read various set values corresponding to the operation mode, and the ROM 36 is accessed.
The setting values stored in the table 36 are read. That is, the resolution (siz) corresponding to the operation mode shown in FIG.
e) Read the frame rate. Next, proceeding to step S3, the circuit is set so as to correspond to the frame rate read out in step S2. For example, if the frame rate is set to 10 [frame / s] in the EVF mode, the image capture controller 1 and the signal processor 2 need only process one frame per three frames. During the period of two frames out of three frames, the clock gate circuit 24
, 25 and the clock generator 20 (dsp clk) to stop the clock supply.

Next, proceeding to step S4, various setting values corresponding to the operation mode and the resolution read out in step S2 are further read from the ROM 36 (see FIGS. 4 to 7), and the gates 24 to 27 and the clock generator 19 are read. To 23 and the regulators 28 to 31 are set.

A thinning method as shown in this embodiment,
According to the interpolation method, the clock frequency, and the setting method of the power supply voltage, the resolution and the frame rate desired by the user can be set in any operation mode. In addition, the clock frequency and the power supply voltage for normal operation at the resolution and frame rate are automatically set according to the resolution and frame rate set by the user, so that the maximum power saving can be achieved in all operating conditions. A power effect is obtained.

As another mode according to the present embodiment,
In the case where the capacity of the SDRAM 13 can be increased, a usage method of limiting the resolution according to the memory capacity of the SDRAM is also possible. That is, a memory having a minimum configuration is mounted, and this is, for example, a QCI.
If only a capacity that can store only F images is provided, the setting of the maximum resolution of the thinning-out method and the interpolation method is limited to QCIF in any operation mode. On the other hand, if the capacity for storing the VGA image can be secured by increasing the memory, the setting of the resolution is not limited. In such a usage, the resolution can be flexibly set according to the memory capacity.

Even if the present invention is applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), a device including one device (for example, a copying machine, a facsimile machine, etc.) ) May be applied.

Further, an object of the present invention is to supply a storage medium (or a recording medium) in which a program code of software for realizing the functions of the above-described embodiments is recorded to a system or an apparatus, and a computer (a computer) of the system or the apparatus Alternatively, this can be achieved by a CPU or an MPU) reading and executing the program code stored in the storage medium. In this case, the program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention. By executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an operating system (OS) running on the computer based on the instruction of the program code. This also includes a case where some or all of the actual processing is performed and the functions of the above-described embodiments are realized by the processing.

Further, after the program code read from the storage medium is written into the memory provided in the function expansion card inserted into the computer or the function expansion unit connected to the computer, the program code is read based on the instruction of the program code. This also includes the case where the CPU provided in the function expansion card or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

As described above, according to the photographing apparatus according to the present embodiment, it is possible to extremely easily realize flexible image quality control in accordance with the usage pattern of the user, and to maximize the control in any operation mode. There is an effect that power consumption can be reduced.

Another effect of the present embodiment is as follows.
Since the resolution of the image can be flexibly changed according to the capacity of the memory, there is an effect that it is possible to easily cope with the addition of the memory.

[0068]

As described above, according to the present invention, the clock signal and the power supply voltage to be supplied to the processing circuits corresponding to the respective processing blocks are controlled in accordance with the operation mode in which the device operates. Power consumption can be reduced.

Further, according to the present invention, there is an effect that optimum power saving can be automatically realized according to the operation mode of the apparatus.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a portable videophone terminal according to an embodiment of the present invention.

FIGS. 2A and 2B are a timing chart showing an operation example of a thinning circuit of the videophone terminal of the present embodiment and a diagram explaining generation of a latch clock in the thinning circuit; FIGS.
It is.

FIG. 3 is a diagram illustrating correspondence between an operation mode, a thinning method, and an interpolation method in the videophone terminal according to the present embodiment.

FIG. 4 is a diagram illustrating resolution in an EVF mode and set values of a clock generator and a regulator.

FIG. 5 is a diagram illustrating resolution in a shooting mode and set values of a clock generator and a regulator.

FIG. 6 is a diagram for explaining resolution and respective set values of a clock generator and a regulator in a reproduction mode.

FIG. 7 is a diagram for explaining a resolution in a videophone mode and set values of a clock generator and a regulator.

FIG. 8 is a flowchart showing an operation mode setting process in the portable videophone terminal according to the embodiment of the present invention.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 101: 00 G06F 1/00 332Z

Claims (13)

[Claims] 1. An image processing apparatus having a plurality of operation modes, comprising: an instruction unit for instructing one of the plurality of operation modes; and a plurality of independent processing circuits, each of which performs a different process. Processing means, clock signal supply means for supplying a clock signal of a predetermined frequency to processing circuits corresponding to the plurality of processing means, power supply means for supplying power supply voltage to the processing circuits corresponding to the plurality of processing means, According to the operation mode instructed by the instruction means,
An image processing apparatus comprising: a control unit that controls a frequency of a clock signal supplied from the clock signal supply unit and a power supply voltage supplied from the power supply unit. 2. One of the plurality of processing units includes: a conversion unit that converts a captured image signal into an electric signal; an image generation unit that generates image data from the electric signal converted by the conversion unit; 2. The image processing apparatus according to claim 1, further comprising: a thinning-out processing unit that performs a data thinning-out process on the image data in accordance with a preset thinning-out method. 3. One of the plurality of processing means includes: an interpolation means for interpolating data according to a preset interpolation method with respect to the image data; and an image based on the image data interpolated by the interpolation means. The image processing apparatus according to claim 1, further comprising: a display unit configured to display an image. 4. The operation mode according to claim 1, wherein the operation mode includes any one of an electronic viewfinder mode, a photographing mode, a reproduction mode, and a videophone mode.
The image processing device according to any one of claims 1 to 4. 5. The control unit according to claim 1, wherein the control unit controls supply of a clock signal to a processing circuit that is not used in the operation mode or control of stopping supply of a power supply voltage. The image processing apparatus according to claim 1. 6. A frequency of a clock signal supplied to each processing circuit from the clock signal supply unit and a power supply voltage supplied to each processing circuit from the power supply unit, corresponding to each of the plurality of operation modes. The image processing apparatus according to claim 1, further comprising a storage unit configured to store information, wherein the control unit performs control based on the information stored in the storage unit. apparatus. 7. A control processing method for an image processing apparatus having a plurality of operation modes, comprising: an instruction step of instructing any one of the plurality of operation modes; and a plurality of processing circuits executing independent different processes. A clock signal supply step of supplying a clock signal of a predetermined frequency to each of the plurality of processing circuits, a power supply step of supplying a power supply voltage to each of the plurality of processing circuits, and an operation mode instructed in the instructing step. A control step of controlling a frequency of a clock signal supplied in the clock signal supply step and a power supply voltage supplied in the power supply step. 8. One of the plurality of processing circuits, a conversion circuit that converts a captured image signal into an electric signal, an image generation circuit that generates image data from the electric signal converted by the conversion circuit, The control processing method according to claim 7, further comprising: a thinning processing circuit that performs a thinning process on the image data according to a thinning method set in advance. 9. One of the plurality of processing circuits includes: an interpolation circuit that interpolates data according to a preset interpolation method for image data; and an image processing unit that performs image processing based on the image data interpolated by the interpolation circuit. The control processing method according to claim 7, further comprising: a display circuit that displays the information. 10. The control process according to claim 7, wherein the operation mode includes any one of an electronic viewfinder mode, a photographing mode, a playback mode, and a videophone mode. Method. 11. The method according to claim 7, wherein in the control step, supply of a clock signal to a processing circuit not used in the operation mode or supply of a power supply voltage is stopped. 2. The control processing method according to claim 1. 12. A frequency of a clock signal supplied to each processing circuit in the clock signal supply step and a power supply voltage supplied to each processing circuit in the power supply step corresponding to each of the plurality of operation modes. The control processing method according to any one of claims 7 to 11, further comprising a memory for storing information, wherein in the control step, control is performed based on the information stored in the memory. 13. A computer-readable storage medium storing a program for executing the control processing method according to claim 7. Description: