WO2018212081A1 - Update control unit, update control device, update control system, and update control method - Google Patents

Update control unit, update control device, update control system, and update control method Download PDF

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WO2018212081A1
WO2018212081A1 PCT/JP2018/018247 JP2018018247W WO2018212081A1 WO 2018212081 A1 WO2018212081 A1 WO 2018212081A1 JP 2018018247 W JP2018018247 W JP 2018018247W WO 2018212081 A1 WO2018212081 A1 WO 2018212081A1
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update
firmware
unit
revision
cpu
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PCT/JP2018/018247
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French (fr)
Japanese (ja)
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幸治 関
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日本電気株式会社
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates

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  • the present invention relates to a technology for updating a program corresponding to a revision of a CPU in an update control unit, an update control device, an update control system, and an update control method.
  • Patent Document 1 discloses a multi-CPU system that receives firmware and identification information of the firmware and causes a CPU (Central Processing Unit) defined for the identification information to execute an upgrade operation of the defined firmware.
  • CPU Central Processing Unit
  • Patent Document 2 discloses a distribution server that receives a firmware update request from an image forming apparatus and transmits the firmware.
  • the distribution server determines the firmware to be applied from the product name, firmware information (including the current revision information), and the revision information to be distributed transmitted from the image forming apparatus. If the current revision is “Version 1.2” and the revision information to be distributed is “Version 2.2”, the distribution server determines that the latest “Version 2.2” should be applied.
  • the multi-CPU system firmware disclosed in Patent Document 1 described above only considers firmware identification information, for example, the type of firmware. Further, the distribution server disclosed in Patent Document 2 only considers the revision of firmware (not the revision of CPU). Therefore, in the technique disclosed in the above-mentioned patent document, when revisions are different among a plurality of CPUs, it is impossible to rewrite and upgrade the CPU firmware.
  • An object of the present invention is to provide an update control unit, an update control device, an update control system, and an update control method capable of updating a program corresponding to the revision of the CPU.
  • the update control unit includes a nonvolatile first storage unit that stores firmware for update in association with a revision of the CPU of the peripheral unit, and the peripheral unit connected to the non-volatile first storage unit.
  • Main control means for reading out a revision and performing update processing for reading out the update firmware corresponding to the read out revision from the nonvolatile first storage means and transmitting it to the peripheral unit.
  • the update control method reads a revision of the CPU from a peripheral unit including a CPU, and updates the update firmware corresponding to the read revision in association with the revision. Is read out from the nonvolatile first storage means for storing the data and transmitted to the peripheral unit.
  • the update control unit makes it possible to update the firmware corresponding to the revision of the CPU of the device connected to the unit.
  • FIG. 1 is a diagram illustrating a configuration of an update control system 20 according to the first embodiment.
  • FIG. 2 shows an example of information stored in the updated firmware determination table storage unit 5.
  • FIG. 3 is a flowchart of an operation in which the main control unit 4 updates the startup firmware 12 of the peripheral unit 10.
  • FIG. 4 is a diagram illustrating a configuration of the update control unit 3 according to the second embodiment.
  • FIG. 1 is a diagram illustrating a configuration of an update control system 20 according to the first embodiment.
  • the update control system 20 includes an update control device 2 that performs firmware upgrade or update (hereinafter abbreviated as update collectively), and an external device that transmits a peripheral update signal that is a signal for instructing the update control device 2 to update. 1 is included. Both are connected via a communication line.
  • the update control device 2 includes an update control unit 3 that controls update, and a peripheral unit 10 that is an update target.
  • One update control unit 3 updates one or more peripheral units 10.
  • Each peripheral unit 10 includes a CPU 11 and nonvolatile second memory means, for example, a nonvolatile second memory 13 which is a nonvolatile semiconductor memory device.
  • the nonvolatile second memory 13 stores startup firmware 12 that is used by the CPU 11 and that matches the revision of the CPU 11.
  • the update control device 2 includes a left peripheral unit 10 having a CPU 11 of revision A1 (hereinafter abbreviated as Rev. A1) and a CPU 11 of revision A2 (hereinafter abbreviated as Rev. A2).
  • Rev. A2 a CPU 11 of revision A2
  • a right peripheral unit 10 is provided.
  • the non-volatile second storage means may be other non-volatile storage means, for example, a magnetic disk device.
  • Each peripheral unit 10 may include a plurality of CPUs 11.
  • the activation firmware 12 may exist for each CPU 11, and the CPUs 11 of the same revision may share one activation firmware 12.
  • the update control unit 3 includes main control means, for example, a main control section 4 constituted by a dedicated logic circuit, and nonvolatile first storage means, for example, a nonvolatile first memory 6 which is a nonvolatile semiconductor storage device.
  • main control means for example, a main control section 4 constituted by a dedicated logic circuit
  • nonvolatile first storage means for example, a nonvolatile first memory 6 which is a nonvolatile semiconductor storage device.
  • the nonvolatile first memory 6 stores update firmware 7 for updating the startup firmware 12 of the CPU 11 of the peripheral unit 10 at a different address for each revision of the CPU 11.
  • the update firmware 7 may be transmitted by another device, for example, the external device 1, received by the main control unit 4, and stored in the nonvolatile first memory 6.
  • the update firmware 7 is written in a nonvolatile first memory 6 in which another device is a replaceable medium, for example, a USB (Universal ⁇ ⁇ ⁇ Serial Bus) memory, and the operator updates the nonvolatile first memory 6 that is the replaceable medium. 2 may be attached.
  • a replaceable medium for example, a USB (Universal ⁇ ⁇ ⁇ Serial Bus) memory
  • the nonvolatile first memory 6 stores the update firmware 7 of Rev.A1 from the address n1, and the update firmware 7 of Rev.A2 from the address n2.
  • the non-volatile first storage means may be other non-volatile storage means, for example, a magnetic disk device.
  • the update control unit 3 further includes update firmware determination table storage means, for example, an update firmware determination table storage unit 5 which is a nonvolatile semiconductor storage device.
  • FIG. 2 shows an example of information stored in the updated firmware determination table storage unit 5.
  • the update firmware determination table storage unit 5 stores an address in the nonvolatile first memory 6 in which the update firmware 7 is stored for each revision of the CPU 11.
  • the update firmware determination table storage unit 5 may be set by the main control unit 4 when the update firmware 7 is transmitted from another device in advance, or the nonvolatile first memory 6 that is a replaceable medium. May be set by the main control unit 4 when.
  • the update firmware determination table storage unit 5 stores n1 address corresponding to Rev.A1 and n2 address corresponding to Rev.A2.
  • the addresses n1 and n2 are addresses in the nonvolatile first memory 6 shown in FIG. 1, and addresses n1 and n2.
  • the updated firmware determination table storage unit may be another nonvolatile storage unit, for example, a magnetic disk device. Further, the updated firmware determination table storage unit 5 may be a part of the nonvolatile first memory 6.
  • the main control unit 4 reads the revision of the CPU 11 of the peripheral unit 10, for example, upon receipt of the peripheral update signal, reads the revision update firmware 7 from the nonvolatile first memory 6, and transmits it to the peripheral unit 10.
  • the CPU 11 updates the startup firmware 12 in the nonvolatile second memory 13 with the transmitted update firmware 7, and then starts up.
  • the main control unit 4 reads the revision Rev. A1 of the CPU 11 from the peripheral unit 10 on the left side, for example, triggered by the peripheral update signal, for example, and updates firmware 7 from the address n1 of the nonvolatile first memory 6. Is transmitted to the peripheral unit 10 on the left side. Further, for example, the main control unit 4 reads the revision Rev. A2 of the CPU 11 from the right peripheral unit 10, reads the update firmware 7 from the address n2 of the nonvolatile first memory 6, and transmits it to the right peripheral unit 10. . In each of the left and right peripheral units 10 in FIG. 1, the CPU 11 updates the startup firmware 12 in the nonvolatile second memory 13 with the transmitted update firmware 7, and then starts up.
  • the main control means may be composed of a processor and firmware for the processor.
  • the processor may be of the same architecture as the CPU 11 or of a different architecture.
  • the main control unit 4 starts the operation when receiving the peripheral update signal transmitted by the external device 1 (S101).
  • the main control unit 4 may start the operation when another trigger occurs, for example, the date and time set in advance in the timer.
  • the main control unit 4 reads the revision of the CPU 11 from the peripheral unit 10 connected to the update control unit 3 (S102). This is executed, for example, when the main control unit 4 transmits a read request signal to the CPU 11 of the peripheral unit 10, and the CPU 11 that has received the signal reads and returns a revision stored in advance.
  • the main control unit 4 selects the CPUs 11 in a predetermined order, for example, in the order of connection addresses, and proceeds with the process. Further, when a plurality of peripheral units 10 are connected to the update control unit 3, the main control unit 4 selects the peripheral units 10 in a predetermined order, for example, in the order of connection addresses, and proceeds with the process. In the example of FIG. 1, for example, the main control unit 4 first selects the left peripheral unit 10 first, and reads Rev. A1.
  • the main control unit 4 reads the read address corresponding to the revision from the update firmware determination table storage unit 5 (S103).
  • the main control unit 4 reads the address n1, which is an address corresponding to Rev. A1, for example.
  • the main control unit 4 reads the update firmware 7 from the address in the nonvolatile first memory 6 (S104). In the example of FIG. 1, for example, the main control unit 4 reads the update firmware 7 of Rev. A1 from address n1.
  • the main control unit 4 transmits the read update firmware 7 to the peripheral unit 10 that has read the revision in S102 (S105).
  • the main control unit 4 transmits, for example, the Rev. A1 update firmware 7 read from address n1 to the left peripheral unit 10.
  • the update firmware 7 transmitted from the CPU 11 is received, and the activation firmware 12 in the nonvolatile second memory 13 is replaced with the update firmware 7.
  • the CPU 11 transmits a reception completion signal to the main control unit 4.
  • the CPU 11 of the left peripheral unit 10 receives the Rev. A1 update firmware 7, replaces the Rev. A1 activation firmware 12 with the update firmware 7, and receives the reception completion signal. Send.
  • the main control unit 4 determines that the update of the CPU 11 has been completed.
  • the main control unit 4 confirms whether the processing of all the CPUs 11 of the peripheral unit 10 being processed has been completed (S106), and if not completed (No in S106), the next CPU 11 of the peripheral unit 10 To return to S102.
  • the main control unit 4 returns to S102 in order to process the peripheral unit 10 because the right peripheral unit 10 has not been processed.
  • the main control unit 4 reads Rev. A2 in S102, the address n2 in S103, the update firmware 7 of Rev.A2 in S104, and the update firmware 7 of Rev.A2 in S105 on the right side. Transmit to unit 10.
  • the CPU 11 of the right peripheral unit 10 receives the Rev. A2 update firmware 7, replaces the Rev. A2 activation firmware 12 with the update firmware 7, and transmits a reception completion signal. .
  • the main control unit 4 activates all the CPUs 11 of all the peripheral units 10 (S107). This is executed, for example, when the main control unit 4 transmits a start signal to all the CPUs 11 of all the peripheral units 10 and the CPU 11 that has received the signal reads the activation firmware 12 and starts the operation.
  • the CPU 11 of the two left and right peripheral units 10 is activated in S107.
  • the CPU 11 of the peripheral unit 10 on the left side starts the operation with the startup firmware 12 of Rev.A1 replaced with the update firmware 7 of Rev.A1.
  • the CPU 11 of the right peripheral unit 10 starts the operation with the Rev. A2 startup firmware 12 replaced with the Rev. A2 update firmware 7.
  • the update control unit 3 has the following effects.
  • the first effect is that the startup firmware 12 can be updated using the update firmware 7 corresponding to the revision of the CPU 11 of the peripheral unit 10, for example, a device connected to the update control unit 3.
  • the second effect is that the startup firmware 12 can be updated without the external device 1 being aware of the difference in revision of the CPU 11.
  • the main control means of the update control unit 3 for example, the main control unit 4 reads the revision of the CPU 11, reads the revision update firmware 7, and transmits it to the peripheral unit 10.
  • FIG. 4 is a diagram illustrating a configuration of the update control unit 3 according to the second embodiment.
  • the update control unit 3 includes main control means, for example, a main control section 4 constituted by a dedicated logic circuit, and nonvolatile first storage means, for example, a nonvolatile first memory 6 which is a nonvolatile semiconductor storage device.
  • the main control means may be composed of a processor and firmware for the processor.
  • the nonvolatile first storage means may be other nonvolatile storage means, for example, a magnetic disk device.
  • the nonvolatile first memory 6 stores the update firmware 7 in association with the revision of the CPU 11 of the peripheral unit 10.
  • the main control unit 4 reads the revision of the CPU 11 from the connected peripheral unit 10, reads the update firmware 7 corresponding to the read revision from the nonvolatile first storage unit, and transmits the update process to the peripheral unit 10. Do.
  • the first effect of the update control unit 3 of the present embodiment is that the startup firmware 12 is updated using the update firmware 7 corresponding to the revision of the CPU 11 of the peripheral unit 10, for example, a device connected to the update control unit 3. It is possible to update. This is because the main control means of the update control unit 3, for example, the main control unit 4 reads the revision of the CPU 11, reads the revision update firmware 7, and transmits it to the peripheral unit 10.

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Abstract

In order to enable the updating of firmware corresponding to a revision of a CPU, this update control unit is equipped with: a nonvolatile first storage means for storing firmware for an update in association with a revision of a CPU of a peripheral unit; and a main control means for carrying out an update process in which a CPU revision is read from a connected peripheral unit, and firmware for an update corresponding to the revision that has been read is read from the nonvolatile first storage means and is transmitted to the peripheral unit.

Description

更新制御ユニット、更新制御装置、更新制御システム、および、更新制御方法UPDATE CONTROL UNIT, UPDATE CONTROL DEVICE, UPDATE CONTROL SYSTEM, AND UPDATE CONTROL METHOD
　本発明は、更新制御ユニット、更新制御装置、更新制御システム、および、更新制御方法において、ＣＰＵのレビジョンに対応したプログラムの更新を行う技術に関する。 The present invention relates to a technology for updating a program corresponding to a revision of a CPU in an update control unit, an update control device, an update control system, and an update control method.
　特許文献１は、ファームウェアと当該ファームウェアの識別情報を受信し、識別情報に対して定義されたＣＰＵ（Central Processing Unit）に、定義されたファームウェアのアップグレード動作を実行させる、マルチＣＰＵシステムを開示する。 Patent Document 1 discloses a multi-CPU system that receives firmware and identification information of the firmware and causes a CPU (Central Processing Unit) defined for the identification information to execute an upgrade operation of the defined firmware.
　特許文献２は、画像形成装置から更新用のファームウェアのダウンロード要求を受け付けて、ファームウェアを送信する配信サーバを開示する。この配信サーバは、画像形成装置から送信された製品名、ファームウェア情報（現在のレビジョン情報を含む）、配信対象のレビジョン情報から適用すべきファームウェアを判断する。この配信サーバは、現在のレビジョンが「Version１.２」、配信対象のレビジョン情報が「Version２.２」であれば、最新の「Version２.２」を適用すべきと判断する。 Patent Document 2 discloses a distribution server that receives a firmware update request from an image forming apparatus and transmits the firmware. The distribution server determines the firmware to be applied from the product name, firmware information (including the current revision information), and the revision information to be distributed transmitted from the image forming apparatus. If the current revision is “Version 1.2” and the revision information to be distributed is “Version 2.2”, the distribution server determines that the latest “Version 2.2” should be applied.
特開２０１６-１８１１１７号公報JP 2016-181117 A 特開２００９-１４６１１９号公報JP 2009-146119 A
　複数のＣＰＵを備える装置やシステムにおいて、ＣＰＵのレビジョンが異なる場合、それぞれのＣＰＵのレビジョンに対応したファームウェアが必要となる。従って、当該装置やシステムは、ＣＰＵのレビジョンを考慮しないで、ＣＰＵのファームウェアを書き換えてアップグレードすることができない。 In a device or system having a plurality of CPUs, when the CPU revisions are different, firmware corresponding to each CPU revision is required. Therefore, the apparatus and system cannot be upgraded by rewriting the firmware of the CPU without considering the revision of the CPU.
　上述の特許文献１が開示するマルチＣＰＵシステムファームウェアは、ファームウェアの識別情報、例えば、ファームウェアの種別を考慮するのみである。また、特許文献２が開示する配信サーバは、ファームウェアのレビジョン（ＣＰＵのレビジョンではない）を考慮するのみである。従って、上述の特許文献に開示された技術では、複数のＣＰＵにおいてレビジョンが異なる場合、ＣＰＵのファームウェアを書き換えてアップグレードすることができない。 The multi-CPU system firmware disclosed in Patent Document 1 described above only considers firmware identification information, for example, the type of firmware. Further, the distribution server disclosed in Patent Document 2 only considers the revision of firmware (not the revision of CPU). Therefore, in the technique disclosed in the above-mentioned patent document, when revisions are different among a plurality of CPUs, it is impossible to rewrite and upgrade the CPU firmware.
　本発明は、ＣＰＵのレビジョンに対応したプログラムの更新を行うことを可能とする更新制御ユニット、更新制御装置、更新制御システム、および、更新制御方法を提供することを目的とする。 An object of the present invention is to provide an update control unit, an update control device, an update control system, and an update control method capable of updating a program corresponding to the revision of the CPU.
　本発明の１実施の形態の更新制御ユニットは、周辺ユニットのＣＰＵのレビジョンに対応付けて、更新用ファームウェアを格納する不揮発第一記憶手段と、接続されている前記周辺ユニットから、前記ＣＰＵの前記レビジョンを読み出して、読み出した前記レビジョンに対応する前記更新用ファームウェアを前記不揮発第一記憶手段から読み出して、前記周辺ユニットに送信する更新処理を行う主制御手段と、を備える。 The update control unit according to an embodiment of the present invention includes a nonvolatile first storage unit that stores firmware for update in association with a revision of the CPU of the peripheral unit, and the peripheral unit connected to the non-volatile first storage unit. Main control means for reading out a revision and performing update processing for reading out the update firmware corresponding to the read out revision from the nonvolatile first storage means and transmitting it to the peripheral unit.
　本発明の１実施の形態の更新制御方法は、ＣＰＵを含む周辺ユニットから、前記ＣＰＵのレビジョンを読み出して、読み出した前記レビジョンに対応する前記更新用ファームウェアを、前記レビジョンに対応付けて更新用ファームウェアを格納する不揮発第一記憶手段から読み出して、前記周辺ユニットに送信する更新処理を行う。 The update control method according to one embodiment of the present invention reads a revision of the CPU from a peripheral unit including a CPU, and updates the update firmware corresponding to the read revision in association with the revision. Is read out from the nonvolatile first storage means for storing the data and transmitted to the peripheral unit.
　本発明にかかる更新制御ユニットは、当該ユニットに接続されている装置のＣＰＵのレビジョンに対応したファームウェアの更新を可能とする。 The update control unit according to the present invention makes it possible to update the firmware corresponding to the revision of the CPU of the device connected to the unit.
図１は、第一の実施の形態にかかる更新制御システム２０の構成を示す図である。FIG. 1 is a diagram illustrating a configuration of an update control system 20 according to the first embodiment. 図２は、更新ファームウェア判定テーブル記憶部５が記憶している情報例を示す。FIG. 2 shows an example of information stored in the updated firmware determination table storage unit 5. 図３は、主制御部４が周辺ユニット１０の起動用ファームウェア１２を更新する動作のフローチャートである。FIG. 3 is a flowchart of an operation in which the main control unit 4 updates the startup firmware 12 of the peripheral unit 10. 図４は、第二の実施の形態にかかる更新制御ユニット３の構成を示す図である。FIG. 4 is a diagram illustrating a configuration of the update control unit 3 according to the second embodiment.
　＜第一の実施の形態＞
　＜構成＞
　図１は、第一の実施の形態にかかる更新制御システム２０の構成を示す図である。更新制御システム２０は、ファームウェアのアップグレードまたはアップデート（以降、まとめて更新と略記する）を行う更新制御装置２と、当該更新制御装置２に更新を指示する信号であるペリフェラル更新信号を送信する外部装置１を包含する。両者は通信回線を介して接続されている。 <First embodiment>
<Configuration>
FIG. 1 is a diagram illustrating a configuration of an update control system 20 according to the first embodiment. The update control system 20 includes an update control device 2 that performs firmware upgrade or update (hereinafter abbreviated as update collectively), and an external device that transmits a peripheral update signal that is a signal for instructing the update control device 2 to update. 1 is included. Both are connected via a communication line.
　更新制御装置２は、更新の制御を行う更新制御ユニット３と、更新の対象となる周辺ユニット１０を備えている。一台の更新制御ユニット３は、１台以上の周辺ユニット１０の更新を実行する。 The update control device 2 includes an update control unit 3 that controls update, and a peripheral unit 10 that is an update target. One update control unit 3 updates one or more peripheral units 10.
　各周辺ユニット１０は、ＣＰＵ１１と、不揮発第二記憶手段、例えば不揮発性の半導体記憶装置である不揮発第二メモリ１３を備えている。不揮発第二メモリ１３には、当該ＣＰＵ１１が使用する、当該ＣＰＵ１１のレビジョンに合った起動用ファームウェア１２が格納されている。図１の例において、更新制御装置２は、レビジョンＡ１（以降、Rev.A1と略記する）のＣＰＵ１１を備える左側の周辺ユニット１０と、レビジョンＡ２（以降、Rev.A2と略記する）のＣＰＵ１１を備える右側の周辺ユニット１０を備えている。なお、不揮発第二記憶手段は、他の不揮発性の記憶手段、例えば、磁気ディスク装置であっても良い。 Each peripheral unit 10 includes a CPU 11 and nonvolatile second memory means, for example, a nonvolatile second memory 13 which is a nonvolatile semiconductor memory device. The nonvolatile second memory 13 stores startup firmware 12 that is used by the CPU 11 and that matches the revision of the CPU 11. In the example of FIG. 1, the update control device 2 includes a left peripheral unit 10 having a CPU 11 of revision A1 (hereinafter abbreviated as Rev. A1) and a CPU 11 of revision A2 (hereinafter abbreviated as Rev. A2). A right peripheral unit 10 is provided. The non-volatile second storage means may be other non-volatile storage means, for example, a magnetic disk device.
　各周辺ユニット１０は、複数のＣＰＵ１１を備えていても良い。この場合、起動用ファームウェア１２は各ＣＰＵ１１対応に存在しても良いし、同一レビジョンのＣＰＵ１１は、一つの起動用ファームウェア１２を共有しても良い。 Each peripheral unit 10 may include a plurality of CPUs 11. In this case, the activation firmware 12 may exist for each CPU 11, and the CPUs 11 of the same revision may share one activation firmware 12.
　更新制御ユニット３は、主制御手段、例えば専用の論理回路で構成される主制御部４と、不揮発第一記憶手段、例えば不揮発性の半導体記憶装置である不揮発第一メモリ６を備えている。 The update control unit 3 includes main control means, for example, a main control section 4 constituted by a dedicated logic circuit, and nonvolatile first storage means, for example, a nonvolatile first memory 6 which is a nonvolatile semiconductor storage device.
　不揮発第一メモリ６には、周辺ユニット１０のＣＰＵ１１の起動用ファームウェア１２を更新する為の更新用ファームウェア７が、ＣＰＵ１１のレビジョンごとに異なるアドレスに格納されている。 The nonvolatile first memory 6 stores update firmware 7 for updating the startup firmware 12 of the CPU 11 of the peripheral unit 10 at a different address for each revision of the CPU 11.
　更新用ファームウェア７は他の装置、例えば外部装置１が送信し、それを主制御部４が受信して不揮発第一メモリ６に格納すれば良い。更新用ファームウェア７は他の装置が可換媒体である不揮発第一メモリ６、例えばＵＳＢ（Universal Serial Bus）メモリに書き込んでおき、オペレータがその可換媒体である不揮発第一メモリ６を更新制御装置２に装着しても良い。 The update firmware 7 may be transmitted by another device, for example, the external device 1, received by the main control unit 4, and stored in the nonvolatile first memory 6. The update firmware 7 is written in a nonvolatile first memory 6 in which another device is a replaceable medium, for example, a USB (Universal メ モ リ Serial Bus) memory, and the operator updates the nonvolatile first memory 6 that is the replaceable medium. 2 may be attached.
　図１の例において、不揮発第一メモリ６は、Rev.A1の更新用ファームウェア７をｎ１番地から格納し、Rev.A2の更新用ファームウェア７をｎ２番地から格納している。なお、不揮発第一記憶手段は、他の不揮発性の記憶手段、例えば、磁気ディスク装置であっても良い。 In the example of FIG. 1, the nonvolatile first memory 6 stores the update firmware 7 of Rev.A1 from the address n1, and the update firmware 7 of Rev.A2 from the address n2. The non-volatile first storage means may be other non-volatile storage means, for example, a magnetic disk device.
　更新制御ユニット３は、さらに、更新ファームウェア判定テーブル記憶手段、例えば不揮発性の半導体記憶装置である更新ファームウェア判定テーブル記憶部５を備えている。図２は、更新ファームウェア判定テーブル記憶部５が記憶している情報例を示す。更新ファームウェア判定テーブル記憶部５は、ＣＰＵ１１のレビジョンごとに、更新用ファームウェア７が格納されている不揮発第一メモリ６内のアドレスを格納している。更新ファームウェア判定テーブル記憶部５は、更新用ファームウェア７が、予め、他の装置から送信されて来たときに主制御部４により設定されても良いし、可換媒体である不揮発第一メモリ６が挿入されたときに、主制御部４により設定されても良い。 The update control unit 3 further includes update firmware determination table storage means, for example, an update firmware determination table storage unit 5 which is a nonvolatile semiconductor storage device. FIG. 2 shows an example of information stored in the updated firmware determination table storage unit 5. The update firmware determination table storage unit 5 stores an address in the nonvolatile first memory 6 in which the update firmware 7 is stored for each revision of the CPU 11. The update firmware determination table storage unit 5 may be set by the main control unit 4 when the update firmware 7 is transmitted from another device in advance, or the nonvolatile first memory 6 that is a replaceable medium. May be set by the main control unit 4 when.
　図２の例において、更新ファームウェア判定テーブル記憶部５は、Rev.A1に対応してｎ１番地を、Rev.A2に対応してｎ２番地を格納している。この、ｎ１番地とｎ２番地は、図１の不揮発第一メモリ６におけるアドレス、ｎ１番地とｎ２番地である。なお、更新ファームウェア判定テーブル記憶手段は、他の不揮発性の記憶手段、例えば、磁気ディスク装置であっても良い。さらに、更新ファームウェア判定テーブル記憶部５は、不揮発第一メモリ６の一部であっても良い。 In the example of FIG. 2, the update firmware determination table storage unit 5 stores n1 address corresponding to Rev.A1 and n2 address corresponding to Rev.A2. The addresses n1 and n2 are addresses in the nonvolatile first memory 6 shown in FIG. 1, and addresses n1 and n2. The updated firmware determination table storage unit may be another nonvolatile storage unit, for example, a magnetic disk device. Further, the updated firmware determination table storage unit 5 may be a part of the nonvolatile first memory 6.
　主制御部４は、例えばペリフェラル更新信号の受信を契機に、周辺ユニット１０のＣＰＵ１１のレビジョンを読み出し、当該レビジョンの更新用ファームウェア７を不揮発第一メモリ６から読み出して周辺ユニット１０に送信する。周辺ユニット１０において、ＣＰＵ１１は送信された更新用ファームウェア７で、不揮発第二メモリ１３内の起動用ファームウェア１２を更新し、その後、起動する。 The main control unit 4 reads the revision of the CPU 11 of the peripheral unit 10, for example, upon receipt of the peripheral update signal, reads the revision update firmware 7 from the nonvolatile first memory 6, and transmits it to the peripheral unit 10. In the peripheral unit 10, the CPU 11 updates the startup firmware 12 in the nonvolatile second memory 13 with the transmitted update firmware 7, and then starts up.
　図１の例において、主制御部４は、例えばペリフェラル更新信号を契機に、例えば左側の周辺ユニット１０からＣＰＵ１１のレビジョンRev.A1を読み出して、不揮発第一メモリ６のｎ１番地から更新用ファームウェア７を読み出して、左側の周辺ユニット１０に送信する。さらに、主制御部４は、例えば右側の周辺ユニット１０からＣＰＵ１１のレビジョンRev.A2を読み出して、不揮発第一メモリ６のｎ２番地から更新用ファームウェア７を読み出して、右側の周辺ユニット１０に送信する。図１における左右２つの周辺ユニット１０の各々において、ＣＰＵ１１は送信された更新用ファームウェア７で、不揮発第二メモリ１３内の起動用ファームウェア１２を更新し、その後、起動する。 In the example of FIG. 1, the main control unit 4 reads the revision Rev. A1 of the CPU 11 from the peripheral unit 10 on the left side, for example, triggered by the peripheral update signal, for example, and updates firmware 7 from the address n1 of the nonvolatile first memory 6. Is transmitted to the peripheral unit 10 on the left side. Further, for example, the main control unit 4 reads the revision Rev. A2 of the CPU 11 from the right peripheral unit 10, reads the update firmware 7 from the address n2 of the nonvolatile first memory 6, and transmits it to the right peripheral unit 10. . In each of the left and right peripheral units 10 in FIG. 1, the CPU 11 updates the startup firmware 12 in the nonvolatile second memory 13 with the transmitted update firmware 7, and then starts up.
　なお、主制御手段は、プロセッサ、および、当該プロセッサ用のファームウェアから構成されても良い。プロセッサは、ＣＰＵ１１と同一アーキテクチャのものであっても、異なるアーキテクチャのものであっても良い。 The main control means may be composed of a processor and firmware for the processor. The processor may be of the same architecture as the CPU 11 or of a different architecture.
　＜動作＞
　図１の主制御部４が周辺ユニット１０の起動用ファームウェア１２を更新する動作について、図３のフローチャートを使用して説明する。 <Operation>
The operation in which the main control unit 4 in FIG. 1 updates the activation firmware 12 of the peripheral unit 10 will be described with reference to the flowchart in FIG.
　主制御部４は、外部装置１が送信したペリフェラル更新信号を受信すると動作を開始する（Ｓ１０１）。主制御部４は、他の契機、例えば予めタイマーに設定された日時になったときに動作を開始しても良い。 The main control unit 4 starts the operation when receiving the peripheral update signal transmitted by the external device 1 (S101). The main control unit 4 may start the operation when another trigger occurs, for example, the date and time set in advance in the timer.
　次いで主制御部４は、更新制御ユニット３に接続されている周辺ユニット１０からＣＰＵ１１のレビジョンを読み出す（Ｓ１０２）。これは、例えば、主制御部４が周辺ユニット１０のＣＰＵ１１に読み出し要求信号を送信し、当該信号を受信したＣＰＵ１１が予め記憶しているレビジョンを読み出して返信することで実行される。 Next, the main control unit 4 reads the revision of the CPU 11 from the peripheral unit 10 connected to the update control unit 3 (S102). This is executed, for example, when the main control unit 4 transmits a read request signal to the CPU 11 of the peripheral unit 10, and the CPU 11 that has received the signal reads and returns a revision stored in advance.
　主制御部４は、一つの周辺ユニット１０に複数のＣＰＵ１１が接続されている場合、所定の順序で、例えば接続アドレス順にＣＰＵ１１を選択して処理を進める。さらに主制御部４は、更新制御ユニット３に複数の周辺ユニット１０が接続されている場合、所定の順序で、例えば接続アドレス順に周辺ユニット１０を選択して処理を進める。主制御部４は、図１の例において、例えば、最初に左の周辺ユニット１０を最初に選択しRev.A1を読み出す。 When a plurality of CPUs 11 are connected to one peripheral unit 10, the main control unit 4 selects the CPUs 11 in a predetermined order, for example, in the order of connection addresses, and proceeds with the process. Further, when a plurality of peripheral units 10 are connected to the update control unit 3, the main control unit 4 selects the peripheral units 10 in a predetermined order, for example, in the order of connection addresses, and proceeds with the process. In the example of FIG. 1, for example, the main control unit 4 first selects the left peripheral unit 10 first, and reads Rev. A1.
　次いで、主制御部４は、更新ファームウェア判定テーブル記憶部５から当該レビジョンに対応する読み出し用のアドレスを読み出す（Ｓ１０３）。主制御部４は、図１及び図２の例において、例えば、Rev.A1に対応するアドレスである、ｎ１番地を読み出す。 Next, the main control unit 4 reads the read address corresponding to the revision from the update firmware determination table storage unit 5 (S103). In the example of FIGS. 1 and 2, the main control unit 4 reads the address n1, which is an address corresponding to Rev. A1, for example.
　さらに、主制御部４は、不揮発第一メモリ６内の当該アドレスから更新用ファームウェア７を読み出す（Ｓ１０４）。主制御部４は、図１の例において、例えば、ｎ１番地からRev.A1の更新用ファームウェア７を読み出す。 Further, the main control unit 4 reads the update firmware 7 from the address in the nonvolatile first memory 6 (S104). In the example of FIG. 1, for example, the main control unit 4 reads the update firmware 7 of Rev. A1 from address n1.
　続けて、主制御部４は、読み出した更新用ファームウェア７を、Ｓ１０２でレビジョンを読み出した周辺ユニット１０に送信する（Ｓ１０５）。主制御部４は、図１の例において、例えば、ｎ１番地から読み出したRev.A1の更新用ファームウェア７を、左の周辺ユニット１０に送信する。 Subsequently, the main control unit 4 transmits the read update firmware 7 to the peripheral unit 10 that has read the revision in S102 (S105). In the example of FIG. 1, the main control unit 4 transmits, for example, the Rev. A1 update firmware 7 read from address n1 to the left peripheral unit 10.
　このとき、周辺ユニット１０においては、例えば、ＣＰＵ１１が送信された更新用ファームウェア７を受信して、当該更新用ファームウェア７で不揮発第二メモリ１３内の起動用ファームウェア１２を置換する。置換後、ＣＰＵ１１は、主制御部４に受信完了信号を送信する。図１の例において、左の周辺ユニット１０のＣＰＵ１１は、Rev.A1の更新用ファームウェア７を受信して、当該更新用ファームウェア７で、Rev.A1の起動用ファームウェア１２を置換し、受信完了信号を送信する。主制御部４は、ＣＰＵ１１から当該受信完了信号を受信すると、当該ＣＰＵ１１の更新が完了したと判定する。 At this time, in the peripheral unit 10, for example, the update firmware 7 transmitted from the CPU 11 is received, and the activation firmware 12 in the nonvolatile second memory 13 is replaced with the update firmware 7. After the replacement, the CPU 11 transmits a reception completion signal to the main control unit 4. In the example of FIG. 1, the CPU 11 of the left peripheral unit 10 receives the Rev. A1 update firmware 7, replaces the Rev. A1 activation firmware 12 with the update firmware 7, and receives the reception completion signal. Send. When receiving the reception completion signal from the CPU 11, the main control unit 4 determines that the update of the CPU 11 has been completed.
　次いで、主制御部４は、処理中の周辺ユニット１０の全てのＣＰＵ１１の処理が終了したかを確認し（Ｓ１０６）、終了していなければ（Ｓ１０６でＮｏ）、当該周辺ユニット１０の次のＣＰＵ１１を処理するためＳ１０２に戻る。図１の例において、主制御部４は、右側の周辺ユニット１０が未処理であるため、当該周辺ユニット１０を処理するため、Ｓ１０２に戻る。 Next, the main control unit 4 confirms whether the processing of all the CPUs 11 of the peripheral unit 10 being processed has been completed (S106), and if not completed (No in S106), the next CPU 11 of the peripheral unit 10 To return to S102. In the example of FIG. 1, the main control unit 4 returns to S102 in order to process the peripheral unit 10 because the right peripheral unit 10 has not been processed.
　今度は、主制御部４は、Ｓ１０２でRev.A2を、Ｓ１０３でｎ２番地を、Ｓ１０４でRev.A2の更新用ファームウェア７を読み出し、そしてＳ１０５でRev.A2の更新用ファームウェア７を右側の周辺ユニット１０に送信する。このとき、右の周辺ユニット１０のＣＰＵ１１は、Rev.A2の更新用ファームウェア７を受信して、当該更新用ファームウェア７で、Rev.A2の起動用ファームウェア１２を置換し、受信完了信号を送信する。 Next, the main control unit 4 reads Rev. A2 in S102, the address n2 in S103, the update firmware 7 of Rev.A2 in S104, and the update firmware 7 of Rev.A2 in S105 on the right side. Transmit to unit 10. At this time, the CPU 11 of the right peripheral unit 10 receives the Rev. A2 update firmware 7, replaces the Rev. A2 activation firmware 12 with the update firmware 7, and transmits a reception completion signal. .
　全ての周辺ユニット１０の全てのＣＰＵ１１の処理が終了した場合（Ｓ１０６でＹｅｓ）、主制御部４は、全ての周辺ユニット１０の全てのＣＰＵ１１を起動する（Ｓ１０７）。これは、例えば、主制御部４が全周辺ユニット１０の全ＣＰＵ１１にスタート信号を送信し、当該信号を受信したＣＰＵ１１が起動用ファームウェア１２を読み出して動作を開始することで実行される。 When the processing of all the CPUs 11 of all the peripheral units 10 is completed (Yes in S106), the main control unit 4 activates all the CPUs 11 of all the peripheral units 10 (S107). This is executed, for example, when the main control unit 4 transmits a start signal to all the CPUs 11 of all the peripheral units 10 and the CPU 11 that has received the signal reads the activation firmware 12 and starts the operation.
　図１の例において、主制御部４は、Ｓ１０６で、左右の２つの周辺ユニット１０の処理が終了したことを確認すると、Ｓ１０７で左右の２つの周辺ユニット１０のＣＰＵ１１を起動する。この結果、図１の例において、左側の周辺ユニット１０のＣＰＵ１１は、Rev.A1の更新用ファームウェア７で置換されたRev.A1の起動用ファームウェア１２で動作を開始する。また、右側の周辺ユニット１０のＣＰＵ１１は、Rev.A2の更新用ファームウェア７で置換されたRev.A2の起動用ファームウェア１２で動作を開始する。 In the example of FIG. 1, when the main control unit 4 confirms that the processing of the two left and right peripheral units 10 is completed in S106, the CPU 11 of the two left and right peripheral units 10 is activated in S107. As a result, in the example of FIG. 1, the CPU 11 of the peripheral unit 10 on the left side starts the operation with the startup firmware 12 of Rev.A1 replaced with the update firmware 7 of Rev.A1. Further, the CPU 11 of the right peripheral unit 10 starts the operation with the Rev. A2 startup firmware 12 replaced with the Rev. A2 update firmware 7.
　＜効果＞
　本実施の形態の更新制御ユニット３は、以下に記載するような効果を奏する。 <Effect>
The update control unit 3 according to the present embodiment has the following effects.
　第１の効果は、更新制御ユニット３に接続されている装置、例えば周辺ユニット１０のＣＰＵ１１のレビジョンに対応する更新用ファームウェア７を用いて、起動用ファームウェア１２の更新が出来ることである。第２の効果は、ＣＰＵ１１のレビジョンの違いを外部装置１が意識することなく、起動用ファームウェア１２を更新することができることである。 The first effect is that the startup firmware 12 can be updated using the update firmware 7 corresponding to the revision of the CPU 11 of the peripheral unit 10, for example, a device connected to the update control unit 3. The second effect is that the startup firmware 12 can be updated without the external device 1 being aware of the difference in revision of the CPU 11.
　その理由は、更新制御ユニット３の主制御手段、例えば、主制御部４が、ＣＰＵ１１のレビジョンを読み出して、そのレビジョンの更新用ファームウェア７を読み出して、周辺ユニット１０に送信するからである。 This is because the main control means of the update control unit 3, for example, the main control unit 4 reads the revision of the CPU 11, reads the revision update firmware 7, and transmits it to the peripheral unit 10.
　＜第二の実施形態＞
　図４は、第二の実施の形態にかかる更新制御ユニット３の構成を示す図である。 <Second Embodiment>
FIG. 4 is a diagram illustrating a configuration of the update control unit 3 according to the second embodiment.
　更新制御ユニット３は、主制御手段、例えば専用の論理回路で構成される主制御部４と、不揮発第一記憶手段、例えば不揮発性の半導体記憶装置である不揮発第一メモリ６を備えている。主制御手段は、プロセッサ、および、当該プロセッサ用のファームウェアから構成されても良い。不揮発第一記憶手段は、他の不揮発性の記憶手段、例えば、磁気ディスク装置であっても良い。 The update control unit 3 includes main control means, for example, a main control section 4 constituted by a dedicated logic circuit, and nonvolatile first storage means, for example, a nonvolatile first memory 6 which is a nonvolatile semiconductor storage device. The main control means may be composed of a processor and firmware for the processor. The nonvolatile first storage means may be other nonvolatile storage means, for example, a magnetic disk device.
　不揮発第一メモリ６は、周辺ユニット１０のＣＰＵ１１のレビジョンに対応付けて更新用ファームウェア７を格納する。主制御部４は、接続されている周辺ユニット１０からＣＰＵ１１のレビジョンを読み出して、読み出したレビジョンに対応する更新用ファームウェア７を不揮発第一記憶手段から読み出して、周辺ユニット１０に送信する更新処理を行う。 The nonvolatile first memory 6 stores the update firmware 7 in association with the revision of the CPU 11 of the peripheral unit 10. The main control unit 4 reads the revision of the CPU 11 from the connected peripheral unit 10, reads the update firmware 7 corresponding to the read revision from the nonvolatile first storage unit, and transmits the update process to the peripheral unit 10. Do.
　本実施の形態の更新制御ユニット３の第１の効果は、更新制御ユニット３に接続されている装置、例えば周辺ユニット１０のＣＰＵ１１のレビジョンに対応する更新用ファームウェア７を用いて、起動用ファームウェア１２の更新が出来ることである。その理由は、更新制御ユニット３の主制御手段、例えば、主制御部４が、ＣＰＵ１１のレビジョンを読み出して、そのレビジョンの更新用ファームウェア７を読み出して、周辺ユニット１０に送信するからである。 The first effect of the update control unit 3 of the present embodiment is that the startup firmware 12 is updated using the update firmware 7 corresponding to the revision of the CPU 11 of the peripheral unit 10, for example, a device connected to the update control unit 3. It is possible to update. This is because the main control means of the update control unit 3, for example, the main control unit 4 reads the revision of the CPU 11, reads the revision update firmware 7, and transmits it to the peripheral unit 10.
　以上、実施形態を参照して本発明を説明したが、本発明は上記実施形態に限定されるものではない。本発明の構成や詳細には、本発明のスコープ内で当業者が理解し得る様々な変更をすることができる。
　この出願は２０１７年５月１５日に出願された日本出願特願２０１７－０９６５０８を基礎とする優先権を主張し、その開示の全てをここに取り込む。 The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.
This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2017-096508 for which it applied on May 15, 2017, and takes in those the indications of all here.
　１　　外部装置
　２　　更新制御装置
　３　　更新制御ユニット
　４　　主制御部
　５　　更新ファームウェア判定テーブル記憶部
　６　　不揮発第一メモリ
　７　　更新用ファームウェア
　１０　　周辺ユニット
　１１　　ＣＰＵ
　１２　　起動用ファームウェア
　１３　　不揮発第二メモリ
　２０　　更新制御システム DESCRIPTION OF SYMBOLS 1 External apparatus 2 Update control apparatus 3 Update control unit 4 Main control part 5 Update firmware determination table storage part 6 Nonvolatile first memory 7 Firmware for update 10 Peripheral unit 11 CPU
12 Start-up firmware 13 Non-volatile second memory 20 Update control system

Claims (8)

  1. 　周辺ユニットのＣＰＵのレビジョンに対応付けて、更新用ファームウェアを格納する不揮発第一記憶手段と、
    　接続されている前記周辺ユニットから、前記ＣＰＵの前記レビジョンを読み出して、読み出した前記レビジョンに対応する前記更新用ファームウェアを前記不揮発第一記憶手段から読み出して、前記周辺ユニットに送信する更新処理を行う主制御手段と、を備える更新制御ユニット。     Non-volatile first storage means for storing firmware for update in association with the revision of the CPU of the peripheral unit;
    The revision of the CPU is read from the connected peripheral unit, the update firmware corresponding to the read revision is read from the nonvolatile first storage means, and an update process is performed to transmit to the peripheral unit An update control unit comprising main control means.
  2. 　前記周辺ユニットに前記更新用ファームウェアの送信が完了すると、前記周辺ユニットの前記ＣＰＵを起動する前記主制御手段を備える請求項１の更新制御ユニットと、
    　起動用ファームウェアを格納する不揮発第二記憶手段と、１）前記主制御手段から前記更新用ファームウェアを受信して前記不揮発第二記憶手段内の前記起動用ファームウェアを置換して更新し、２）前記主制御手段から起動されると、前記不揮発第二記憶手段に格納されている前記起動用ファームウェアを用いて動作を開始する前記ＣＰＵとを備える周辺ユニットとを、備える更新制御装置。     The update control unit according to claim 1, further comprising the main control unit that activates the CPU of the peripheral unit when transmission of the update firmware to the peripheral unit is completed.
    Non-volatile second storage means for storing startup firmware, 1) receiving the update firmware from the main control means, replacing the startup firmware in the non-volatile second storage means, and updating 2) An update control device comprising: a peripheral unit including the CPU that starts operation using the activation firmware stored in the nonvolatile second storage unit when activated from the main control unit.
  3. 　前記レビジョンに対応付けて前記更新用ファームウェアを格納する、前記不揮発第一記憶手段内のアドレスを格納する更新ファームウェア判定テーブル記憶手段を備え、前記主制御手段は、前記周辺ユニットから読み出した前記レビジョンに対応する前記更新用ファームウェアを、前記更新ファームウェア判定テーブル記憶手段を参照して得た前記アドレスから読み出す、前記更新制御ユニットを備える、請求項２の更新制御装置。 Update firmware determination table storage means for storing an address in the nonvolatile first storage means for storing the update firmware in association with the revision, and the main control means for the revision read from the peripheral unit The update control device according to claim 2, further comprising: the update control unit that reads the corresponding update firmware from the address obtained by referring to the update firmware determination table storage unit.
  4. 　ペリフェラル更新信号を受信すると前記更新処理を開始する前記主制御手段を備える、請求項２乃至請求項３の何れか１項の更新制御装置と、
    　前記ペリフェラル更新信号を前記更新制御装置に送信する外部装置と、を包含する更新制御システム。     The update control device according to any one of claims 2 to 3, comprising the main control unit that starts the update process when a peripheral update signal is received;
    And an external device that transmits the peripheral update signal to the update control device.
  5. 　前記主制御手段は、前記外部装置から前記更新用ファームウェアを受信して、前記不揮発第一記憶手段に格納する、請求項４の更新制御システム。 The update control system according to claim 4, wherein the main control means receives the update firmware from the external device and stores it in the nonvolatile first storage means.
  6. 　ＣＰＵを含む周辺ユニットから、前記ＣＰＵのレビジョンを読み出して、読み出した前記レビジョンに対応する更新用ファームウェアを、前記レビジョンに対応付けて前記更新用ファームウェアを格納する不揮発第一記憶手段から読み出して、前記周辺ユニットに送信する更新処理を行う、更新制御方法。 The revision of the CPU is read from the peripheral unit including the CPU, the update firmware corresponding to the read revision is read from the nonvolatile first storage unit that stores the update firmware in association with the revision, and An update control method for performing an update process to be transmitted to a peripheral unit.
  7. 　前記更新用ファームウェアを受信して、不揮発第二記憶手段内の起動用ファームウェアを置換して更新し、前記起動用ファームウェアを用いて動作を開始する、請求項６の更新制御方法。 The update control method according to claim 6, wherein the update firmware is received, updated by replacing the startup firmware in the nonvolatile second storage means, and the operation is started using the startup firmware.
  8. 　前記周辺ユニットから読み出した前記レビジョンに対応する前記更新用ファームウェアを、前記不揮発第一記憶手段内のアドレスを格納する記憶手段を参照して得た前記アドレスから読み出す、請求項６乃至７の何れか一項に記載の更新制御方法。 8. The update firmware corresponding to the revision read from the peripheral unit is read from the address obtained by referring to a storage unit that stores an address in the nonvolatile first storage unit. The update control method according to one item.
PCT/JP2018/018247 2017-05-15 2018-05-11 Update control unit, update control device, update control system, and update control method WO2018212081A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09265391A (en) * 1996-03-27 1997-10-07 Victor Co Of Japan Ltd Controller with program rom correction function, electronic equipment provided with the controller and correction method for program
JP2001216167A (en) * 2000-02-04 2001-08-10 Minolta Co Ltd System consisting of main body and peripheral device
JP2004234056A (en) * 2003-01-28 2004-08-19 Ricoh Co Ltd Software updating method, management server program, software updating program, and printer utility program

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09265391A (en) * 1996-03-27 1997-10-07 Victor Co Of Japan Ltd Controller with program rom correction function, electronic equipment provided with the controller and correction method for program
JP2001216167A (en) * 2000-02-04 2001-08-10 Minolta Co Ltd System consisting of main body and peripheral device
JP2004234056A (en) * 2003-01-28 2004-08-19 Ricoh Co Ltd Software updating method, management server program, software updating program, and printer utility program

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