WO2018142103A1

WO2018142103A1 - Microcontroller peripheral configuration

Info

Publication number: WO2018142103A1
Application number: PCT/GB2018/050127
Authority: WO
Inventors: Joar RUSTEN; Vemund Bakken; Anders NORE
Original assignee: Nordic Semiconductor Asa; Wilson, Timothy James
Priority date: 2017-01-31
Filing date: 2018-01-17
Publication date: 2018-08-09
Also published as: GB2559340A; TW201830260A; GB201701544D0

Abstract

A microcontroller (1) includes a processor (7), a peripheral (15a-15c), a non-volatile memory (13) and a peripheral initialisation system. The peripheral (15a-15c) is arranged to read peripheral configuration data from an addressable volatile-memory peripheral register (21a-21c). The non-volatile memory has a configuration region for storing peripheral initialisation data, which represents the address of the peripheral register and peripheral configuration data. The peripheral initialisation system is arranged to read the peripheral configuration data and the address of the peripheral register from the configuration region, and to write the peripheral configuration data to the address of the peripheral register.

Description

Microcontroller Peripheral Configuration

This invention relates to apparatus and methods for initialising a microcontroller. More specifically, but not exclusively, it relates to using a hardware or software peripheral initialisation system to configure peripherals in a microcontroller after the

microcontroller is reset.

Microcontrollers typically comprise a processor, memory, and peripherals. In some cases, the peripherals have associated volatile-memory peripheral registers that store chip-specific configuration data (e.g. trim values). This configuration data will typically be written to a region of non-volatile (e.g., flash) memory during the last stages of the manufacturing process, based on calibration tests that are performed on each individual chip. Then, when the microcontroller is in normal use, the volatile peripheral registers are loaded with the configuration data every time the microcontroller is reset. The peripherals can then use these values to ensure that they operate optimally.

For example, a temperature-sensor peripheral may be calibrated at the factory, with one or more calibration values being stored in a configuration region of flash memory. Then, each time the chip is reset, these values are copied to one or more peripheral registers associated with the temperature sensor, so that the temperature sensor can then subsequently send accurate temperature measurements to the processor of the microcontroller.

This approach is acceptable for simple microcontrollers, but presents difficulties as the number of peripherals grows. This is because it can be difficult to ensure that the association between the non-volatile memory addresses and the peripheral registers is maintained correctly, without errors, particularly when the chip design is changed between successive versions, e.g., when the number and type of peripherals is changed. Indeed, failing to copy the right configuration data to the right peripheral registers may potentially cause the microcontroller to fail catastrophically.

The present invention seeks to provide an improved approach. From a first aspect, the invention provides a microcontroller comprising:

a processor;

a peripheral arranged to read peripheral configuration data from an

addressable volatile-memory peripheral register;

non-volatile memory having a configuration region for storing peripheral initialisation data, the peripheral initialisation data representing the address of the peripheral register and representing peripheral configuration data; and

a peripheral initialisation system arranged to perform one or more data-read operations to read the peripheral configuration data and the address of the peripheral register from the configuration region, and arranged to write the peripheral

configuration data to the address of the peripheral register.

From a second aspect, the invention provides a method of initialising a microcontroller, the microcontroller comprising:

a processor;

a peripheral arranged to read peripheral configuration data from an

addressable volatile-memory peripheral register;

a peripheral initialisation system; and

non-volatile memory,

the method comprising the peripheral initialisation system:

performing one or more data-read operations to retrieve (i) an address of a peripheral register, and (ii) peripheral configuration data, from a configuration region of the non-volatile memory; and

writing the peripheral configuration data to the address of the peripheral register.

Thus it will be seen by those skilled in the art that, in accordance with the invention, the address of a peripheral register can be stored, as data, in a configuration region of the non-volatile memory, along with configuration data to be written to that peripheral register. In this way, a particular location within the configuration region does not need to be permanently mapped, by the hardware or software of the microcontroller, to a particular peripheral register. Instead, the addresses of one or more peripheral registers can be stored in memory as data, independently of the microcontroller's hardware and software. The microcontroller may comprise a plurality of peripherals, each associated with one or more respective addressable volatile-memory peripheral registers. The peripheral initialisation data may represent addresses of a plurality of peripheral registers, and may represent respective peripheral configuration data for these peripheral registers.

In preferred embodiments, the peripheral initialisation data is stored as structured data in the configuration region. The peripheral initialisation system is preferably arranged to parse peripheral initialisation data stored in the configuration region. In this way it is not necessary for the peripheral initialisation system to know, in advance, the location of any particular peripheral-register address value or peripheral configuration data within the configuration region. It is also not necessary for the peripheral initialisation system to know, in advance of reading the configuration region, the address of a peripheral register to which any given configuration data should be copied, because this address can be read from the configuration region, along with the configuration data, when parsing the structured data.

The initial writing of the register addresses to the non-volatile memory may, in some cases, be performed as a step during the manufacture of the microcontroller.

However, it may be done at a later date. Preferably, the peripheral configuration data is written at the same time as the register address or addresses. The writing of one or both of an address of a peripheral register and respective peripheral configuration data to the non-volatile memory may be done over an external interface to the

microcontroller, such as a serial interface or a debug port— for example, an SPI, JTAG, SWD or USB interface, or any other interface that allows external write access to the configuration region of the non-volatile memory. This may be done as part of a chip test or calibration process, which may, for example, be carried out at a semiconductor fabrication plant.

The configuration region is preferably associated with a fixed address— e.g., a fixed start address. This fixed address is preferably known to the peripheral initialisation system. It may, for example, be a constant value, stored as data, or in a processor instruction, or in hardware, which is accessible to the peripheral initialisation system. This allows the peripheral initialisation system to locate the initialisation data. This fixed address is preferably also known to a party, such as a manufacturer, who may use it when writing the peripheral initialisation data to the configuration region. In some embodiments, the peripheral initialisation system stores or knows no other nonvolatile memory address.

The processor may be the only or main processor or CPU of the microcontroller, or it may be one of a plurality of processors. The processor may be an ARM™ Cortex-M™

In one set of embodiments, the peripheral initialisation system comprises dedicated hardware and, preferably, operates independently of the processor (or processors, if the microcontroller has more than one). For example, the peripheral initialisation system may comprise distinct logic gates, separate from the processor, for performing the one or more data-read operations and/or for writing the peripheral configuration data. In this case, the peripheral initialisation system preferably does not itself comprise a general-purpose processor or CPU and/or is not programmable. In this way, the microcontroller may initialise the peripheral independently of the main processor, and without necessarily requiring the processor to have started. This can enable faster initialisation of the peripherals after the microcontroller is reset. The peripheral initialisation system may be arranged to read some or all of the peripheral initialisation data before the processor is ready to execute software instructions after the microcontroller is reset. The peripheral initialisation system may also be arranged to write some or all of the peripheral configuration data before the processor is ready to execute instructions after the microcontroller is reset.

It will be appreciated that the peripheral initialisation system is not limited to any particular physical shape or location on the microcontroller, and may comprise any number of separate logical components.

The microcontroller may comprise a memory bus. The peripheral initialisation system may be connected to the memory bus— preferably as a bus master. The non-volatile memory and the peripheral register are preferably accessible over the memory bus. The peripheral initialisation system may access the non-volatile memory and peripheral register via the memory bus, or via different respective buses.

In another set of embodiments, the peripheral initialisation system comprises the processor. The peripheral initialisation system preferably then also comprises a software peripheral initialisation routine. In this case, the processor may be seen as a component of the peripheral initialisation system, although it will also typically be used to perform other functions on the microcontroller also.

In these software-based embodiments, the non-volatile memory preferably stores the peripheral initialisation routine, preferably in a program region of the non-volatile memory. This program region is preferably separate from— i.e., does not overlap— the configuration region. The program region may consist of a single contiguous block of memory. Similarly, the configuration region may consist of a single contiguous block of memory.

The peripheral initialisation routine preferably comprises instructions that instruct the processor to perform one or more data-read operations to retrieve the address of the peripheral register and the peripheral configuration data from the configuration region. It preferably comprises instructions to write the peripheral configuration data to the address of the peripheral register. Such arrangements may be more flexible than a hardware-based peripheral initialisation system, since the peripheral initialisation routine, executed by a particular device, may be amended, if required, for example, by updating the software on the device. In a set of embodiments wherein the peripheral initialisation system comprises, or uses, a processor of the microcontroller, methods of the invention may comprise the processor performing the one or more data-read operations and/or writing the peripheral configuration data. In any embodiments, the microcontroller may be arranged to cause the peripheral initialisation system to perform the one or more data-read operations, and to write the peripheral configuration data to the address of the peripheral register, in response to the microcontroller being reset— preferably every time the microcontroller is reset. It may be arranged to start or finish writing the peripheral configuration data to one or more, or to all, peripheral registers within a constant, predetermined maximum time after each reset. Preferably, the peripheral initialisation system writes the peripheral configuration data for a peripheral before any software is executed that uses that peripheral. The peripheral initialisation system may write the peripheral configuration data before any application software is run by the microcontroller (i.e., software that is not part of a bootloader or reset routine). The execution of the peripheral initialisation system may form part a device initialisation routine, or reset routine, that the processor is configured to execute immediately after each reset. The peripheral initialisation system may be configured to execute before any other process starts. The

microcontroller may be configured to not start another process until the peripheral initialisation system completes its data-read and data-write operations.

The peripheral initialisation system may write peripheral configuration data to a first, non-empty set of peripheral registers in response to the microcontroller being reset. However, it may also be arranged to defer writing peripheral configuration data to a second, non-empty set of peripheral registers until a further condition is met— for example, until an associated peripheral is about to be activated or used. The second set is preferably different from the first set. In this way, initialisation of the

microcontroller after a reset may be made more efficient, by reducing the number of peripheral register writes that are required as part of the initialisation process. This may be especially beneficial when the peripheral initialisation system uses the main processor of the microcontroller, and so delays the execution of other software. The peripheral initialisation system may be caused to perform the deferred write or writes based on a software instruction— e.g., a branch to a relevant part of a peripheral initialisation routine— or on detecting a hardware signal or interrupt. In one set of embodiments, the microcontroller comprises a radio and the peripheral initialisation system is arranged to write peripheral configuration data to the address of a peripheral register associated with the radio only when the radio is first required, after a reset.

In one set of embodiments, the peripheral initialisation system may comprise both dedicated hardware— e.g., as described above— and a software peripheral

initialisation routine. The dedicated hardware may be arranged to write peripheral configuration data to a first set of peripheral registers, preferably in response to the microcontroller being reset. The peripheral initialisation system may be arranged to use the processor to write configuration data to a second set of peripheral registers. The second set is preferably different from the first set; they may be non-overlapping. The peripheral initialisation system may defer writing configuration data to the second set of peripheral registers until a further condition is met— for example, until a peripheral, such as a temperature sensor or radio, requires a value from the second set of peripheral registers. Preferably, peripheral configuration data is written to a second set of peripheral registers when a condition is met - e.g. when one or more peripherals associated with a second set of peripheral registers needs to be activated.

It will be appreciated, that whilst peripheral configuration data is preferably written to the first set of peripheral registers before the second set of peripheral registers, this is not essential and, in other embodiments, the peripheral configuration data may be written to the second set of peripheral registers before, or simultaneously with, peripheral configuration data is written to the first set of peripheral registers. Preferably, the first set of peripheral registers is associated with one or more peripherals that are required for initialising or running the processor - e.g. the first set of peripheral registers may be associated with a regulator, an oscillator, and/or any other peripheral or peripherals that need to be initialised in order for the processor to start following a reset. The second set of peripheral registers may be associated with one or more peripherals that are not required for initialising or running the processor - e.g. the second set of peripheral registers may be associated with a radio, temperature sensor, and/or other peripheral or peripherals that do not need to be initialised in order for the processor to run. Using hardware (and not the processor) to write peripheral configuration data to a first set of peripheral registers, and using the processor to write peripheral configuration data to a second, different set of peripheral registers, can be advantageous because the task of writing configuration data is split between the dedicated hardware and the processor. For example, the dedicated hardware may initialise the processor more quickly and efficiently by only having to write peripheral configuration data necessary to initialise the processor. Once the processor is initialised, the processor can then take over the task of writing peripheral configuration data, preferably based on when an associated peripheral is about to be activated or used. Basing the writing of configuration data on when an associated peripheral is about to be used is a complex task that may require coordination between multiple elements of the microcontroller hardware and/or software. It can be more efficient to use the processor to determine when a condition is met for writing the configuration data to the second set of peripherals, than configuring this in hardware. This approach also allows the conditions to be revised in future firmware upgrades. It will be appreciated that a microcontroller reset may inherently clear the peripheral registers, or may clear them by a hardware reset mechanism (e.g., by temporarily removing power to RAM). Thus, the peripheral initialisation system may be configured to start once the peripheral registers are cleared.

The address of the peripheral register may take any appropriate form. In some embodiments, the microcontroller may use a common address space including the non-volatile memory and the peripheral register— e.g., supporting memory-mapped I/O access. Other embodiments may use a different form of addressing for peripheral registers from the non-volatile memory— e.g., port-mapped I/O. In general, the address of the peripheral register can be any value or values that enable the peripheral initialisation system to write to the peripheral register. It could, for instance, comprise a peripheral identifier and a register identifier (where the register identifier is not necessarily unique without the peripheral identifier). In one set of embodiments, the address could be a value that is mapped to a physical address by the peripheral initialisation system— e.g., an index into an address look-up table stored within the peripheral initialisation system. However, more preferably, the peripheral initialisation system does not itself store any data relating to the address of the peripheral register. This avoids the need to update the peripheral initialisation system when a new peripheral register is added to the design— instead, the initialisation data in the configuration region can be updated to store the address of the new peripheral register.

In some embodiments, the configuration region is suitable for storing peripheral initialisation data, but the configuration region may be blank. This would typically be the case for a microcontroller before any calibration has been carried out on the microcontroller. In other embodiments, the configuration region has peripheral initialisation data stored in it— e.g., after calibration or configuration of the

microcontroller.

The peripheral initialisation data may be stored in the configuration region as structured data according to a predetermined structure. This structure is preferably known to a party, such as a manufacturer, who preferably writes the peripheral initialisation data to the configuration region according to the structure. This may be regarded as an optional step of the method of initialising the microcontroller. For example, the configuration region may store the peripheral initialisation data across a predefined sequence of addresses in the configuration data. The sequence of addresses may be adjacent addresses or memory locations (e.g., adjacent word- aligned addresses, or adjacent addresses when stepping by the length of address data or configuration data that is stored at each address if this is greater than a single word), or they may be non-adjacent addresses. It is preferred that the peripheral initialisation data be stored in a contiguous block, as this represents an efficient use of memory— however, this is not essential.

Preferably, the peripheral initialisation system is configured to parse, or step through, the configuration region. The reading, or parsing, may start from a fixed start address, stored by the peripheral initialisation system. The peripheral initialisation system may be configured to read the peripheral initialisation data according to a predetermined sequence.

In one set of embodiments, the configuration region stores the peripheral initialisation data across a predefined sequence of addresses in the configuration region. The peripheral initialisation system may be configured to step through a predefined sequence of addresses when performing the one or more data-read operations. The sequence is preferably generated by an algorithm in the peripheral initialisation system— e.g., an algorithm that reads data from successive addresses, in a loop that ends when a condition is met. The peripheral initialisation system may be configured to read from in a sequence of adjacent addresses or locations when performing the one or more data-read operations.

The peripheral initialisation system may be arranged to step through the configuration region until it reaches the end of the configuration region or the end of the peripheral initialisation data. It may be arranged to keep reading the peripheral initialisation data until it reaches an address storing a predetermined stop value. Or it may be arranged to read for a number of read operations determined by a count value stored in the configuration region.

The peripheral initialisation data representing the addresses of one or more peripheral registers, and representing respective peripheral configuration data, may be stored as one or more respective tuples in the configuration region. Each tuple comprises at least two elements. One element may represent peripheral configuration data, and a second element may represent an address of a peripheral register to which that configuration data should be copied. The elements of the tuples may be located at separate addresses in the configuration region. Preferably, however, the elements of each tuple are located in successive memory addresses or locations (allowing for the appropriate size of each data element). Where there are multiple tuples, the peripheral initialisation system is preferably arranged to read both or all the elements of a first tuple, and subsequently to read both or all the elements of a second tuple.

The initialisation data may represent an address or configuration data in any appropriate way. It may simply store a binary representation of the address or configuration data, or it may store an encoded or compressed version of the address or configuration data.

As mentioned, in some embodiments the elements in each tuple may be arranged in the configuration region such that, when the peripheral initialisation system reads the peripheral initialisation data from the configuration region, the elements of each tuple are read one after another. In this case, an element comprising the configuration data may be read immediately after an element comprising the address of a peripheral register to which the configuration data should be copied to (or vice versa). The peripheral initialisation system may be configured to read a set of tuples in succession. The peripheral initialisation system may be configured to write the respective peripheral configuration data to the address of the respective peripheral register after reading each tuple, before reading a next tuple in the succession.

In some embodiments, the peripheral initialisation system may be arranged to read metadata from the configuration region. This metadata may control or determine how the peripheral initialisation system reads, or parses (e.g. steps through), the configuration region. The metadata may, for example, indicate a number of bytes of peripheral configuration data that should be written to a particular peripheral register address. It may indicate which peripheral registers should be written to immediately after a reset, and which should be deferred until a further condition is met. It may indicate how many tuples are stored in the peripheral region. Thus, the metadata may— directly or indirectly— determine the read address of at least one of the data- read operations.

In some embodiments, a software peripheral initialisation routine may branch to an address in the configuration region. The configuration region may store executable code for reading or parsing the peripheral initialisation data and/or for writing the configuration data to the peripheral register(s). This executable code could be written to the configuration region at the same time as the initialisation data is written. In this way, the initialisation data may be self-interpreting.

It will be appreciated that the peripheral register(s) is addressable by the peripheral initialisation system, e.g. over the memory bus, or over a dedicated peripheral bus. Each peripheral register may occupy a single memory address, or a contiguous region of memory, or it may be split across a plurality of locations. A peripheral register, as referred to herein, may be only a single bit long (possibly within a larger bit field), or it may comprise a plurality of bits (e.g. a 32-bit word). It will be appreciated that what is here referred to as a single peripheral register may, from the perspective of the associated peripheral, comprise a plurality of values, and the peripheral may read one of these values independently of another, and may use the values for different purposes.

The non-volatile memory on the microcontroller may comprise flash memory. Further, it may store one or more software components, such as a bootloader and/or a firmware module and/or a user application. Preferably, the software components are stored in a program region, separate from the configuration region.

The processor may be any suitable processor. In some embodiments it is a processor from ARM™, such as a processor from ARM™'s Cortex™ range. The memory bus may be separate from an instruction bus, or it may carry both instructions and data.

The microcontroller is preferably an integrated device— e.g., integrated on silicon. In some embodiments, it may comprise a radio transmitter or receiver— e.g., a so-called radio-on-a-chip device. From another aspect, the invention provides an integrated radio device comprising a microcontroller as disclosed herein.

Features of any aspect or embodiment described herein may, wherever appropriate, be applied to any other aspect or embodiment described herein. Where reference is made to different embodiments or sets of embodiments, it should be understood that these are not necessarily distinct but may overlap.

Certain preferred embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

Figure 1 is a schematic drawing of a microcontroller embodying the invention; Figure 2 illustrates structured data in a configuration region of memory for storing configuration data, together with an associated peripheral address;

Figure 3 is a flow diagram illustrating a peripheral initialisation sequence of the microcontroller of Figure 1 ; and

Figure 4 a schematic drawing of an alternative embodiment of a microcontroller according to the invention.

Figure 1 shows an integrated-circuit microcontroller 1 , or radio-on-a-chip. The microcontroller 1 comprises clock logic 3, which may include a resistor-capacitor oscillator and/or may receive an input from an off-chip crystal oscillator (not shown), power management circuitry 5, a processor 7 (e.g. an ARM™ Cortex-M™), memory protection logic 9, RAM 1 1 , a flash memory controller 20, flash memory 13, radio communication logic 17, three peripherals 15a-15c, and input/output circuitry 19. The components of the microcontroller 1 are interconnected using suitable lines and/or buses (not shown). The microcontroller 1 may use a Harvard architecture or a von Neumann architecture.

The microcontroller 1 may be connected to a number of external components such as a power supply, radio antenna, crystal oscillator, sensors, output devices, etc.

The microcontroller 1 also has a debugging interface 18 (e.g., an ARM™ Serial Wire Debug (SWD) interface) which may be used for loading data into the flash memory 13 and for debugging the processor 7. For example, the debugging interface 18 may be used to load data into a configuration region of the flash memory 13. The configuration region (also referred to herein as configuration memory) starts at a predefined flash- memory address— e.g., 0x0000 0000.

The peripherals 15a-15c are each arranged to read configuration data (e.g. a configuration value such as a trim value) for controlling their behaviour from a respective addressable volatile-memory peripheral register 21 a-21c. Specifically, peripheral 15a is arranged to read configuration data from addressable volatile- memory peripheral register 21 a, which has an address of ADDRO. Similarly, peripheral 15b is arranged to read configuration data from addressable volatile-memory peripheral register 21 b at address ADDR1. Peripheral 15c is arranged to read configuration data from addressable volatile-memory peripheral register 21c at address ADDR2. While the present embodiment assumes a memory-mapped I/O architecture, it will be appreciated that the same principles can be applied to other architectures, such as port-mapped I/O based devices. The concept of a register address, as used herein, therefore includes combinations of a peripheral identifier and a register identifier, or any other appropriate way of specifying a particular peripheral register.

Peripheral 15a may be, for example, a temperature sensor, and it may read a calibration value from its associated peripheral register 21a to calibrate its temperature readings. Such calibration values are usually determined during production of the microcontroller 1 by the manufacturer, and are designed to account for one or more variations in the microcontroller— e.g., due to variations in the fabrication of the microcontroller 1. Without the calibration value, the microcontroller 1 and/or peripheral 15a may not function optimally, or may not function at all.

It is expected that the manufacturer will typically store the calibration value(s) in the configuration region of flash memory 13 while testing the microcontroller 1 during production. However, the calibration value(s) may, in some cases, be modified at a later stage— for example, by an integrator who is integrating the microcontroller 1 into a complex product (for example, by setting one or more parameters relating to the power supply), or during the operating lifetime of the microcontroller 1 , after the microcontroller has been acquired by an end user. For instance, the manufacturer or another party may reconfigure the calibration values as part of a firmware update process. Whoever writes the configuration data into the configuration region should typically also know the addresses of the respective peripheral registers 21 a-21c, and write these addresses into the configuration region alongside the configuration data, for reasons explained below. The register address and configuration data are together referred to below as initialisation data.

The volatile peripheral registers 21a-21 c may be located anywhere on the

microcontroller 1 ; for instance, they may be physically located with their respective peripherals, or they may be part of a larger RAM block 1 1 , as shown in Figure 1. The microcontroller 1 has a peripheral initialisation system based around the processor 7 executing an initialisation routine. The initialisation routine is stored as executable code in a program region of the flash memory 13, possibly together with other types of executable code such as firmware, third party software, and a bootloader. The initialisation routine is executed following a microcontroller 1 reset, although it will be appreciated that in some other embodiments the initialisation routine may be executed at any time during the operation of the microcontroller 1 - e.g., a program running on the microcontroller 1 may instruct the processor 1 to execute the initialisation routine without a reset. The steps of the initialisation routine instruct the processor 7 to write the configuration data to the peripheral registers 21 a-21 c, as described in more detail below with reference to Figures 2 and 3. The initialisation routine does this by reading the addresses of the peripheral registers 21 a-21c and the configuration data from the configuration region.

When stepping through the configuration region, the initialisation routine is configured to step through and read data from a sequence of addresses in the configuration region. In the present embodiment, the initialisation routine steps through, and reads data from, adjacent addresses of the configuration region, starting at address 0x0000 0000 (see Figure 2). However, in other embodiments the initialisation routine may step through and read data from non-adjacent addresses of the configuration region. The routine of stepping through and reading data from the configuration region continues until the initialisation routine reaches an address storing a predefined data value that indicates the end of the peripheral initialisation data— referred to here as the "END MARKER". However, in other embodiments the initialisation routine may continue stepping through the configuration region (and reading data therefrom) until it reaches the end of the configuration region, or until some other condition is met. It will be appreciated that having the processor 7 read peripheral addresses, as data, from this configuration region is quite different from the processor 7' fetching instructions from a code region of memory (such as fetching executable instructions from the program region of the flash memory 13).

This initialisation mechanism makes it relatively easy for the manufacturer or integrator to add, remove or modify peripheral configuration data, because the location of each item of data in the configuration region is not fixed by the hardware of the

microcontroller 1 , and so a new peripheral register can be supported simply by adding another tuple to the end of the existing tuple array, and moving the END MARKED along. In this way, it is easier to reconfigure the peripherals, and to add and remove peripherals, between successive versions of the microcontroller 1 design.

In the present example, the configuration region stores tuples 201-203. Each tuple 201-203 comprises data to be written to a peripheral register 21 a-21 c (e.g. X, Y or Z), together with the address of that peripheral register (e.g. ADDRO, ADDR1 or ADDR2). The elements of each tuple 201-203 are stored at adjacent addresses of the configuration region and are organised such that, when the initialisation routine steps through the configuration region, the configuration data to be written to a peripheral register (e.g. 21 a) is read immediately after reading the address of the peripheral register (e.g. 21 a). In this way, the initialisation routine reads each element of each tuple when stepping through adjacent addresses of the configuration region. Storing the elements of each tuple at adjacent addresses provides even more efficient use of memory, and enables a faster initialisation routine.

The specific arrangement of the tuples is best seen in Figure 2. As shown, the elements of tuple 201 are at address 0x0000 0000 and 0x0000 0004 of the

configuration region. Stored at these addresses are, respectively, the address (i.e. ADDR1) of peripheral register 21 b, and a value (i.e. "X") to be written to peripheral register 21 b. Similarly, the elements of tuple 202 are at address 0x0000 0008 and 0x0000 000C of the configuration region, and stored at these addresses are, respectively, the address (i.e. ADDRO) of peripheral register 21 a, and a value (i.e. "Y") to be written to peripheral register 21 a. The elements of tuple 202 are at address 0x0000 0010 and 0x0000 0014 of the configuration region, and stored at these addresses is, respectively, the address (i.e. ADDR2) of peripheral register 21c, and a value (i.e. "Z") to be written to peripheral register 21 c.

Stored at configuration region address 0x0000 0018 is the "END MARKER". When read by the initialisation routine, the END MARKER causes the processor 7 to end the initialisation routine. At this point, the microcontroller 1 may proceed to execute other processes (e.g. a firmware process). It will be appreciated that the END MARKER enables the initialisation routine to be stopped before it reaches the end of the configuration region. This beneficially allows a manufacturer and end user to select which tuples in the configuration region are read, and accordingly which tuples in the configuration region are not read. For example, when not all of the tuples in the configuration region contain values to be copied into a peripheral register 21 a-21 c, the designer may save processing time by using the "END MARKER" to stop the initialisation routine from reading those tuples.

In other embodiments, alternative data structures are used. For example, instead of an END MARKER, the configuration region may store a length field, indicating how many tuples the processor 7 should read. In some embodiments, the configuration region contains metadata relating to the structure of the initialisation data. The initialisation routine may use this metadata to determine how to parse the initialisation data. The initialisation data could be stored using XML, for example. The metadata could comprise executable code which the initialisation routine invokes. This executable code could include instructions for parsing the initialisation data and/or for writing the configuration data to the peripheral registers 21 a-21c.

Figure 3 provides a more details flowchart of the steps of the initialisation routine following a reset.

When the microcontroller 1 resets, the processor 1 executes code in the program region of the flash memory 13 to start the initialisation routine. At step 301 , the initialisation routine obtains the address of the peripheral register that it should access (i.e. ADDR1) by reading "ADDR1" from address 0x0000 0000 of the configuration region. It will be appreciated that before this step, the initialisation routine does not know which peripheral register to access. At step 302, the initialisation routine obtains the information that it should write to the peripheral address (i.e. ADDR1) that it obtained at step 301 by reading "X" from address 0x0000 0004 of the configuration region. At step 303, the initialisation routine proceeds to write "X" to peripheral address "ADDR1". Once "X" has been written to "ADDR1 ", peripheral register 21 b will be loaded with the value "X".

At step 304, the initialisation routine steps through the configuration region to obtain the address of the next peripheral register that it should access (i.e. ADDR0) by reading "ADDR0" from address 0x0000 0008 of the configuration region. At step 305, the initialisation routine obtains the information that it should copy to the address that it obtained at step 304 by reading "Y" from address 0x0000 000C of the configuration region. At step 306, the initialisation routine proceeds to write Ύ" to peripheral address "ADDR0". Once "Y" has been written to "ADDR0", peripheral register 21 a will be loaded with the value Ύ". At step 307, the initialisation routine steps through the configuration region again to obtain the address of the next peripheral register that it should access (i.e. ADDR2) by reading "ADDR2" from address 0x0000 0010 of the configuration region. At step 308, the initialisation routine obtains the information that it should write to the address that it obtained at step 307 by reading "Z" from address 0x0000 0014 of the configuration region. At step 309, the initialisation routine proceeds to write "Z" to peripheral address "ADDR2". Once "Z" has been written to "ADDR2", peripheral register 21 C will be loaded with the value "Z".

At step 310, the initialisation routine reads the "END MARKER" from configuration address 0x0000 0018. At this point, the processor ends the initialisation routine, and preferably proceeds to execute another process stored in the microprocessor 1.

In another embodiment, the initialisation routine may instruct the processor 7 to postpone writing configuration data into one or more peripheral registers (e.g.

peripheral register 21 b). For example, the writing may be postponed to a time when a peripheral is first called upon for use following a reset. The call may come from a process other than an initialisation routine (e.g. a third-party software process or firmware process). ln a further embodiment, one or more peripheral registers may be loaded with configuration data during an initialisation routine following a reset, but the loading of configuration data into one or more other peripheral registers may be postponed. For example, the initialisation routine may instruct the processor 7 to write configuration data into the relevant peripheral registers (21a and 21 c) of peripherals 15a and 15c immediately after the microcontroller 1 is reset, but the loading of configuration data into the relevant peripheral register (i.e. 21 b) of peripheral 15b may be postponed to a time when peripheral 21 b is first used after a reset. This late loading of configuration data may be carried out by firmware or by other software running on the

microprocessor 1.

Figure 4 shows an alternative embodiment in which a microcontroller 1 ' comprises a peripheral initialisation unit 22. Features that correspond with those of the

microcontroller 1 of Figure 1 are labelled with the same numbers, with a prime mark. The peripheral initialisation unit 22 forms part of the microcontroller's peripheral initialisation system, and has hardwired logic gates that operate independently of the processor 7'. The hardwired logic gates are arranged to load the peripheral registers 21 a'-21 c' with configuration data (by writing the configuration data to the respective registers), in the same way as the initialisation routine (described above with reference to Figures 1-3) would instruct the processor 7' to load the peripheral registers 21 a'-21 c' with configuration data. However, whilst the steps of loading the peripheral registers 21 a'-21 c' with configuration data are the same as those carried out by the processor 7' when executing the initialisation routine (e.g. the same as the stepping, reading and writing steps of Figure 3), it will be understood that the steps carried out by the peripheral initialisation unit 22 may occur independently of the processor 7'. In this way, the peripheral registers 21a'-21 c' can be loaded without waiting for the processor 7' to start following a reset. This, of course, can lead to faster initialisation of the peripheral registers 21 a'-21 c'. Generally, therefore, in this embodiment it will be understood that the peripheral initialisation unit 22 steps through and reads data from each element of each tuple in the configuration region of the flash memory 13', in the same way as the processor 7' would do when executing the initialisation routine in the microcontroller 1 of Figure 1. This process enables the peripheral initialisation unit 22 to obtain the configuration data from the configuration region, together with a peripheral register address specifying the location of where to write the configuration data. Using this information, the peripheral initialisation unit 22 is arranged to write the configuration data to the specified peripheral register address. The peripheral initialisation unit 22 is preferably hardwired to load configuration data into the peripheral registers 21 a'-21 c'. In this case, it is not essential for the configuration region of flash memory 13' to store an initialisation routine that accesses these peripheral registers 21a'-21c'. Alternatively, the peripheral initialisation unit 22 could comprise its own processor, separate from the main processor 7', and be arranged to execute an initialisation routine— e.g., an initialisation routine stored in the configuration region— so as to load configuration data into the peripheral registers 21 a'-21 c'.

The peripheral initialisation unit 22 preferably loads configuration data into the peripheral registers 21 a'-21 c' immediately following a microcontroller 1 ' reset.

Although, it will be appreciated that in some other embodiments the peripheral initialisation unit 22 may be operated at any time during the operation of the microcontroller T. For instance, a program running on the processor 7' may instruct the peripheral initialisation unit 22 to load configuration data into the peripheral registers 21 a'-21 c', in the absence of a reset.

In some arrangements, the peripheral initialisation unit 22 loads configuration data to a subset of the peripheral registers, while the processor 7' is used to load configuration data to a second subset of the peripheral registers, at a later point in time.

Claims

1. A microcontroller comprising:

a processor,

a peripheral arranged to read peripheral configuration data from an addressable volatile-memory peripheral register;

a peripheral initialisation system, arranged to perform one or more data-read operations to read the peripheral configuration data and the address of the peripheral register from the configuration region, and arranged to write the peripheral configuration data to the address of the peripheral register.

2. A microcontroller as claimed in claim 1 , wherein the peripheral initialisation system comprises dedicated hardware logic gates, separate from the processor, for performing the one or more data-read operations and for writing the peripheral configuration data.

3. A microcontroller as claimed in claim 1 , wherein the peripheral initialisation system comprises the processor and a software peripheral initialisation routine, for execution by the processor, wherein the peripheral initialisation routine is stored in a program region of the non-volatile memory, and wherein the peripheral initialisation routine comprises instructions for performing the one or more data-read operations and for writing the peripheral configuration data to the address of the peripheral register.

4. A microcontroller as claimed in any preceding claim, having peripheral initialisation data, representing the address of the peripheral register and representing peripheral configuration data, stored in said configuration region.

5. A microcontroller as claimed in any preceding claim, wherein the peripheral initialisation system is configured to read the peripheral configuration data and the address of the peripheral register from adjacent memory locations.

6. A microcontroller as claimed in any preceding claim, wherein the peripheral initialisation system stores a fixed start address for the configuration region, and is arranged to read the peripheral initialisation data starting from the fixed start address.

7. A microcontroller as claimed in any preceding claim, wherein the peripheral initialisation system is arranged to read the peripheral initialisation data in a sequence of data-read operations determined by a loop that continues until a condition is met.

8. A microcontroller as claimed in any preceding claim, further comprising a plurality of peripherals, each associated with a respective addressable volatile-memory peripheral register, wherein the peripheral initialisation system is arranged to read a set of tuples in succession from the configuration region, each tuple comprising a first element representing the address of a peripheral register or the plurality of peripheral registers and a second element representing respective peripheral configuration data, and to write the respective peripheral configuration data to the address of the respective peripheral register after reading each tuple, before reading a next tuple in the succession.

9. A microcontroller as claimed in any preceding claim, wherein the peripheral initialisation system is arranged to read metadata from the configuration region, and to use the metadata to control at least one of said data-read operations.

10. A microcontroller as claimed in any preceding claim, wherein the

microcontroller is arranged to cause the peripheral initialisation system to perform said one or more data-read operations, and to write the peripheral configuration data to the address of the peripheral register, in response to the microcontroller being reset.

11. A microcontroller as claimed in any preceding claim comprising a plurality of peripherals, each associated with a respective addressable volatile-memory peripheral register, wherein the peripheral initialisation system is arranged to:

write peripheral configuration data to a first non-empty set of the peripheral registers in response to the microcontroller being reset; and

defer writing peripheral configuration data to a second non-empty set of the peripheral registers until a further condition is met.

12. A method of initialising a microcontroller, the microcontroller comprising:

a processor;

a peripheral arranged to read peripheral configuration data from an

addressable volatile-memory peripheral register;

a peripheral initialisation system; and

non-volatile memory,

the method comprising the peripheral initialisation system:

13. A method as claimed in claim 12, further comprising using an external interface to the microcontroller to write one or both of (i) the address of the peripheral register, and (ii) the peripheral configuration data, to the non-volatile memory.

14. A method as claimed in claim 12 or 13, wherein the peripheral initialisation system comprises dedicated hardware logic gates, separate from the processor.

15. A method as claimed in claim 12 or 13, wherein the peripheral initialisation system comprises the processor and a software peripheral initialisation routine, and wherein the processor:

performs the one or more data-read operations; and

writes the peripheral configuration data to the address of the peripheral register.