KR20020029921A - Method and apparatus for modifying microinstructions in a static memory device - Google Patents

Abstract

Method and apparatus for modifying the program flow of microinstructions residing in static storage. If you need to modify the microinstructions in static storage, use the jump point register to hold the jump point address that triggers the interrupt event. If the address currently held by the program counter matches the jump point address and the jump point register is enabled, an interrupt event occurs that transfers the program flow from the static memory to the programmable memory. Instead of using interrupts to indicate the occurrence of external events, they are used to bypass some of the microinstructions that reside in static memory.

Description

METHOD AND APPARATUS FOR MODIFYING MICROINSTRUCTIONS IN A STATIC MEMORY DEVICE}

The control memory contains executable micro instructions that control the data path of the microprocessor. Depending on the machine, the control storage device is composed of RAM or ROM. The contents of the RAM can be easily rewritten with new information. RAM is volatile, however, and retains its contents only while the circuit is powered up. On the other hand, the contents of the ROM are written at the time of manufacture of the ROM, and are not changed or deleted even if the power is cut off.

In mass production, ROM is much cheaper than RAM. Because of the cost of RAM and ROM, microcode programmers typically design circuits with RAM that can easily correct programming errors and minimize production costs by replacing RAM with ROM at the end of the design. However, no matter how strict your design checks, you can overlook programming errors that will remain permanently in static ROM.

If a programming error is found in the microinstruction set stored in ROM, programmers create a patch to fix it. "Patch" is a technical term that refers to new code created to modify or add functionality to conventional code. Micro-instructions are collectively called "codes" and are designed in a modular fashion that consists of the entire code in divided subroutines. Thus, if there is an error in part of the code, it can be modified separately without the need to rewrite the entire code. If an error subroutine is found, the programmer makes a copy of the error free subroutine, and the program flow calls the copy of the subroutine in lieu of the error subroutine. This technique can be implemented in systems that use both RAM and ROM to store microinstruction sets. Typically, the subroutine is stored in ROM, while the main program code that calls the subroutine is stored in RAM. When the program flow processes the microinstruction set in RAM, it encounters the exit point of the main code and executes the microinstruction of the subroutine stored in ROM. When the execution of the subroutine completes, the program flow exits the subroutine and returns to the main code of RAM. However, if there is an error in the subroutine, the programmer must disable the exit point corresponding to the subroutine in error and patch the error with the new subroutine. Since the ROM is static, the new subroutine must be stored in RAM.

This method is inflexible, because you can't enter an erroneous subroutine unless at a predetermined point in the main code. Also, no matter how minor the error, in order to correct the programming error of the subroutine, the entire subroutine must be copied to RAM, which wastes the RAM space. There is a need for a technology that allows more flexible setting of entry points between ROM and RAM in the program flow. In addition, there is a need to minimize the RAM size required to correct ROM programming errors.

The present invention relates to the field of control storage for microprocessors. More specifically, the present invention relates to the modification of a control storage device using both read only memory (ROM) and random access memory (RAM).

1 is a diagram illustrating a conventional program flow between a RAM and a ROM.

2 is a diagram illustrating a program flow between a RAM and a ROM in an embodiment of the present invention.

3 is a block diagram of circuitry for implementing a program flow between a RAM and a ROM.

4 is a block diagram of a data processing system.

The present invention relates to a method and apparatus for modifying the program flow of microinstructions residing in a ROM so that programmers have more direct access and control over the microinstructions of the ROM. Because microinstructions in ROM cannot be changed, changes to the microinstruction set must be made in RAM. The present invention allows the programmer to directly access programming errors in ROM without having to copy all of the subroutines into RAM. The present invention also allows the programmer to add functionality to a conventional ROM without replacing the conventional ROM with a newly designed ROM.

An embodiment of the present invention is a method of modifying a program flow in a static memory device comprising generating an interrupt that triggers a jump from the static memory device to the programmable memory device.

In one embodiment of the present invention, a jump point register is used to hold a jump point address. The jump point address may trigger an interrupt event in the program flow. The program counter stores an address for the current micro instruction of the program flow. If the program counter has the same address as the jump point address in the jump point register, an interrupt event occurs. The interrupt event initiates a change in the program flow from the static memory element to the programmable memory element.

In another embodiment of the present invention, the interrupt event may be used to correct programming errors of the static memory device. Programmers can develop patches for defective code residing in static storage. The programmer can then store the exit address in a register or other storage device, which corresponds to the address pre-determined for the microinstruction in the defective code portion. The exit address is compared with all micro instructions executing in the program flow. When the predetermined micro instruction occurs in the program flow, the micro instruction of the patch is executed.

In another embodiment of the present invention, the program flow may be changed by the interrupt event to add a function to the static memory device. Such modifications may be in the form of added code, stored in a programmable memory device and executed during the execution of microcode from a static memory device.

In another embodiment of the present invention, a plurality of jump point registers may be coupled to the interrupt port, and the comparator may individually enable or disable each jump point register. Each jump point register can be associated with a separate interrupt event. By using multiple jump point registers, programmers have the flexibility to assign jump points as needed in the future.

This modification reduces the RAM size needed to correct ROM firmware errors and improves ROM functionality.

Hereinafter, another object and advantages of the present invention will be described in detail.

1 is a block diagram illustrating a prior art that implements an error correction method, i.e., a "debugging" method, for a microinstruction of a data processing system such as a computer system or a general purpose microcomputer. For illustrative purposes, embodiments of the present invention will be described using ROM and RAM. However, as will be apparent from the following detailed description, the present invention can be applied to any static memory and volatile memory. In FIG. 1, the RAM 100 is programmed with code that calls a subroutine of the ROM 110. The RAM stack is processed until a program counter (not shown) that holds the address of the microinstruction to be executed next encounters the address of the microinstruction of the ROM stack. At point 101, the program flow exits the microinstruction set of RAM 100 and enters the microinstruction set of ROM 110. The program counter processes the ROM 110 until it encounters an address of a micro instruction of the RAM 100. At point 102, the program flow exits the microinstruction set of ROM 110 and reenters the microinstruction set of RAM 100. This process itself is repeated for the various subroutines stored in ROM 110. However, if the programming error of ROM 110 needs to be corrected or other functionality needs to be added, the programmer can bypass the subroutine stored in ROM 110 by reprogramming RAM 100. Those skilled in the art will copy the entire subroutine from which programming errors have been eliminated to RAM 100, and the program flow will be executed to execute the subroutine copied to RAM 100 rather than the faulty subroutine stored in ROM 110. Reprogram and debug 100).

As shown in FIG. 1, if a programming error 106 is found in the subroutine 105, the programmer disables the data path 103 from the RAM 100 to the ROM 110 and the RAM 100. The new data path 104 must be designed with an alternate subroutine 107 that resides in. Once the subroutine 107 is complete, the data path 108 returns to the indicated microinstruction of the RAM 100, located next to the disabled data path 103.

This can be a huge waste of RAM resources when the size of programming errors is small. Since the ROM is static, even if only a small portion of the subroutine needs to be rewritten, the microinstruction of the ROM cannot be changed so that the program flow is redirected back to RAM at another point in the ROM.

FIG. 2 is a diagram illustrating a program flow between RAM 200 and ROM 210 that can debug an error subroutine stored in ROM 210 without having to copy the entire subroutine to RAM 200. A block diagram that is an embodiment of the invention. In addition, subroutines stored in ROM 210 may be programmed to include additional features and functionality. In the part where there is no error in the microcode, the program flow exits the RAM 200 and enters the ROM 210 as shown in FIG. 1. However, if a bug is found in the ROM 210, the program flow of FIG. 2 allows to program a patch for the bug without wasting much of the RAM 200 to fix the bug.

The RAM stack is processed until the program counter (not shown) is the address of the microinstruction of the ROM stack. At point 201, the program flow exits the microinstruction set of RAM 200 and enters the microinstruction set of ROM 210. The ROM 210 is processed until the program counter becomes the address of the micro instruction of the RAM 200. At point 202, the program flow exits the microinstruction set of ROM 210 and enters the microinstruction set of RAM 200. This process itself is repeated for the various subroutines stored in ROM 210.

Program flow 203 continues until subroutine 208 contains a programming error 205. Error-free instructions of this subroutine are executed, and at point 204 the program flow returns to RAM 200 for patching. When the patch is complete at point 206, the program flow returns to ROM 210. When the subroutine is completed, data path 207 returns to RAM 200.

In an embodiment of the present invention, an interrupt circuit is applied to a conventional data processing system. FIG. 3 is a block diagram of an interrupt circuit that may implement the program flow shown in FIG. 2.

The interrupt circuit of FIG. 3 is composed of a plurality of registers or other storage devices capable of storing addresses of microinstructions, generally called jump point registers. The jump point register holds a jump point address that triggers an interrupt event. As is known, an interrupt temporarily suspends a process when an external event occurs outside the process. When the interrupt signal indicates the occurrence of an interrupt event, the processor suspends the current process and performs the task requested by the interrupt signal. By the way, in the embodiment of the present invention, the interrupt signal is used in a very different way. Rather than using interrupts to indicate the occurrence of external events, the interrupt circuit of FIG. 3 uses interrupts to bypass portions of the microcode residing in ROM.

The interrupt circuit implemented in FIG. 3 includes three jump point registers 300, 310, 320. By the way, the number of jump point registers can be changed according to the preference of the circuit designer regardless of the scope of the present invention. Each of the three jump point registers is connected to three comparators 308, 318, 328 via lines 303, 313, 323, respectively. A comparator is a device that compares two input words, usually consisting of an exclusive OR gate, but any device can be used as long as it can perform the comparison function. However, for illustrative purposes, the term "comparator" will be used. Each comparator 308, 318, 328 is connected to the processor 320 via control lines 304, 305.

Each of the jump point registers 300, 310, and 320 is set to an address corresponding to an interrupt event. Line 301 loads its address from processor 320 into each jump point register.

Control line 304 communicates the contents of the program counter to comparators 308, 318, and 328. The program counter is a register holding the address of the microinstruction to be executed next. In some data processing systems, program counters are designed to hold the microinstructions that are currently being executed. In order to implement an embodiment of the present invention, it is not necessary to limit the contents of the program counter to the predictive state or the current state.

To achieve the desired function associated with each jump point register, control line 305 carries control signals from processor 320 to enable or disable each of comparators 308, 318, and 328.

Control line 306 transfers a status signal from comparators 308, 318, and 328 to a status register (not shown) of processor 320 indicating which of the jump point registers has the same address as the program counter. Placement of a status register in processor 320 is only a matter of design choice and does not affect the scope of the present invention. As another embodiment of the present invention, the program counter may be used to identify a jump point register having the same address as the program counter. If a program counter is used, all bits of the address must be examined to identify the jump point register in question. If the status register is used, only one bit needs to be examined. Using the program counter or status registers to determine which jump point register holds the jump point address associated with the current interrupt is only a matter of design choice.

When the address of the program counter is the same as one of the addresses of the jump point registers 300, 310, and 320, and a control signal for enabling the comparator corresponding to the jump point register is transmitted, the status signal is transmitted to the processor 320. A signal is passed to an interrupt controller (not shown) to generate an interrupt.

In this case, the interrupt event is an interrupt event that is directed to the program counter by a micro-instruction stored in RAM, rather than an external event that calls to hold the program flow. The program flow continues in RAM until it is directed back to ROM. Because RAM is dynamic, program counters and the resulting program flow can be redirected to any microinstruction stored in ROM.

To debug the program code, the programmer checks the bug in the microinstruction subroutine section of the ROM and stores the bug address in the jump point register. If the bug is a minor one that can be fixed in a few lines of code, you can easily store a patch for the bug in RAM. When the program counter encounters the bug address stored in the jump point register, a signal is sent from the comparator to the interrupt controller, thereby generating an interrupt that directs the program flow back to the patch stored in RAM. Once all of the microinstructions of the patch have been executed, the microinstructions of the RAM following this patch can redirect the program flow back to the microinstructions of the ROM following the error portion of the subroutine. In this way, you can modify subroutines that contain minor errors without having to copy all of the subroutines into RAM.

For the purpose of adding functionality to program code stored in ROM, the programmer can use the jump point register to add subroutines within existing ROM subroutine structures. In one embodiment of the invention, the programmer can insert the address of the microinstruction into the jump point register, which becomes part of the program subroutine residing in the ROM. If the program counter holds the address of the microinstruction, the program flow will jump to the microinstruction corresponding set stored in RAM. The last instruction in the microinstruction corresponding set allows the programmer to direct the program flow back to the desired subroutine. In this way, a programmer can add new functionality to a ROM without replacing the conventional ROM that is programmed. Thus, the ROM can be updated without replacing the reprogrammed ROM.

The interrupt circuit of FIG. 3 is an embodiment of the present invention in which comparators corresponding to the three jump point registers are connected to the interrupt request (IRQ) pin of the processor, that is, the interrupt controller, through the OR gate 330. In another embodiment of the present invention, multiple interrupt circuits within the data processing system can be used to minimize the amount of check for new code that will be generated each time an interrupt is triggered. If multiple jump point registers are used in one interrupt circuit, a large amount of MIPS is consumed to determine what new code corresponds to the interrupt just triggered. However, if each interrupt circuit has three or fewer jump point registers and is connected to separate IRQ pins, then MIPS is less expensive to implement the code corresponding to the triggered interrupt event. Using multiple interrupt circuits or a single interrupt circuit is a matter for the circuit board designer to choose as needed. However, any variation of the interrupt circuit as described herein is within the scope of the present invention.

4 is a block diagram illustrating a data processing system. Those skilled in the art can implement the present invention without detailed description of well-known circuits and control logic, and therefore, detailed descriptions thereof are omitted in FIG. 4 for clarity. 4 is a representative form of a system in which control logic is separated from an operation core. The system may be a digital signal processor or an application specific integrated circuit (ASIC). However, the present invention can also be used for other architecture types of data processing systems, such as control logic combined with an operation core.

The program flow control device 400 is connected to the control storage device RAM 430, the control storage device ROM 440, the interrupt circuit 450, and the instruction decoder 410. Interrupt circuit 450 may be the interrupt circuit of FIG. 3. The program flow control device 400 generates the contents of the program counter, generates a flag indicating whether the current instruction has been executed or canceled, and processes external events such as direct memory access (DMA) and interrupts. The instruction decoder 410 may be integrated into the operation core 420 and is connected to the program flow control apparatus 400 via the line 405. The command decoder device 410 is also connected to the control memory RAM 430 and the control memory ROM 440 via a line 404. The interrupt circuit 450 is connected to the program flow control device 400, the control storage device RAM 430, the control storage device ROM 440, and the operation core 420. The program flow control device 400 generates a program counter based on an input from the control storage device RAM 430, the control storage device ROM 440, or the interrupt circuit 450. The program flow control apparatus 400 enables the inputs from the control storage RAM 430, the control storage ROM 440, or the interrupt circuit 450 to enable the RAM_CS 401, the ROM_CS 403, and the EXEC 412. ) Lines. Line 422 loads a jump point address into a jump point register (not shown) of interrupt circuit 450. Line 402 delivers the contents of the program counter to control memory RAM 430, control memory ROM 440, and interrupt circuit 450. Interrupt circuit 450 allows the program counter to display the current jump point register ( If it is shown that it has the same address as the jump point address held in (not shown), an interrupt is generated by an interrupt controller (not shown) which may be integrated in the program flow control apparatus 400. When the interrupt circuit 450 generates an interrupt, the program flow control device 400 resets the program counter to hold the address of the subsequent microinstruction specified by the interrupt event.

The data processing system of FIG. 4 is just one embodiment showing how the present invention can be utilized. The present invention is not limited to specific hardware and software configurations, and can be implemented using various computer programming languages and hardware. For example, the functionality of the program flow control apparatus 400, the instruction decoder 410, and the operation core 420 may be implemented using a general purpose processor, as shown by block 490. The present invention can be used anywhere as long as it has a code stored in a static memory device such as a ROM, a magnetic tape storage device, a compact disk or a floppy disk.

Other embodiments may be modified and various aspects may be modified without departing from the scope of the present invention. Accordingly, the drawings and description are to be regarded in an illustrative rather than a restrictive sense.

Claims (15)

As a method of modifying the program flow of static storage, Generating an interrupt that triggers a jump from the static memory device to a programmable memory device. The method of claim 1, Generating the interrupt, Storing an address copy of a first microinstruction, wherein the first microinstruction is part of a first microinstruction set, wherein the first microinstruction set is a subset of the subroutine residing in the static memory device. ; Storing an alternate micro instruction set in the programmable storage device; During a program flow, comparing an address of each micro-instruction of the subroutine with the stored copy; And If the result of the comparing step matches, replacing the first microinstruction set with the replacement microinstruction set, generating a jump in the program flow from the static memory device to the programmable memory device. Method comprising a. The method of claim 2, Wherein said static memory device comprises a read-only memory device (ROM) and said programmable memory device comprises a random access memory device (RAM). The method of claim 3, wherein Wherein said alternative microinstruction set includes a patch for programming errors present in said subroutine. The method of claim 1, Generating the interrupt, Storing an address copy of a first microinstruction, wherein the first microinstruction is part of a first set of microinstructions included in a first subroutine, wherein the first subroutine resides in the static memory device; ; Storing a micro-instruction set added to the programmable storage device; During a program flow, comparing an address of each micro-instruction of the subroutine with the stored copy; And Adding the added microinstruction set if the results of the comparing step match, generating a jump of the program flow from the static memory device to the programmable memory device. . The method of claim 5, And said added microinstruction set is a second subroutine with added functionality. The method of claim 1, Generating the interrupt, Using a jump point register to hold a jump point address that triggers an interrupt event; Sequentially executing a first microinstruction set residing in the static memory, wherein each microinstruction of the sequentially executed first microinstruction set has a corresponding address stored separately in a program counter during the sequential execution; step; And Interrupting the program flow with the interrupt event when the program counter has the same address as the jump point address of the jump point register. The method of claim 7, wherein Interrupting the program flow, Setting a control signal for enabling a comparator that compares an address of the program counter with an address held in the jump point register according to a condition; And Executing a second microinstruction set corresponding to the jump point address when the comparator receives an enable control signal, wherein the second microinstruction set resides in a programmable storage device. How to. 10. The method of claim 8, wherein the programmable memory device is random access memory (RAM). The method of claim 1, Generating the interrupt, Storing a plurality of jump point addresses, each jump point address stored in a corresponding jump point register, each jump point address triggering a corresponding interrupt event; Determining which jump point address of the plurality of jump point addresses to enable; Sequentially executing a first set of micro instructions residing in the static memory device, wherein the program counter sequentially holds an address for each micro instruction being executed; And And executing the corresponding interrupt event when the program counter has the same address as one of the plurality of jump point addresses and the jump point address is enabled. The method of claim 10, Executing the interrupt event, Predetermining a plurality of micro instruction sets corresponding to each of the plurality of jump point addresses; Setting a control signal for enabling each of a plurality of comparators connected to a corresponding jump point register and the program counter according to a condition; When one of the plurality of comparators receives an enable control signal, executing a corresponding microinstruction set associated with the jump point address, wherein the jump point address is identical to the address of the program counter, and the corresponding microinstruction Wherein the set resides in a programmable storage device. The method of claim 11, Executing the corresponding microinstruction set includes executing a subsequent microinstruction from the first microinstruction set. A device for processing programmable machine command signals, A jump point register including one or more predetermined jump points; A static memory device coupled to the jump point register and including a first microinstruction set; A random access memory device coupled to the jump point register and the static memory device, the random access memory device comprising a second micro-instruction set; A program control unit coupled to the jump point register, the static memory and the random access memory, for transmitting a plurality of control signals to the jump point register, the static memory and the random access memory; And A comparator coupled to the jump point register and the program control unit, comprising: a comparator for comparing one or more of the plurality of control signals with the predetermined jump point and generating an interrupt signal according to the comparison result . The method of claim 13, A plurality of jump point registers each storing one or more predetermined jump points, wherein the program control unit transmits a plurality of control signals to each of the plurality of jump point registers, the static memory, and the random access memory, The plurality of jump point registers; And A plurality of comparators coupled to one of the plurality of jump point registers and the program control unit, each of the comparators comparing one or more of the corresponding jump point addresses and the plurality of control signals to generate an interrupt signal according to the comparison result; Generating a plurality of comparators. A device for modifying the program flow of microinstructions residing in static storage, Storage means for storing a predetermined microinstruction address, separate from the static storage device; Volatile storage means for storing a first micro-instruction address set; Means for comparing the predetermined microinstruction address with each address in the first microinstruction address set; And A plurality of control signal generating means connected to said predetermined microinstruction address storage means, said volatile memory means and said comparing means, and enabling a modification of said program flow from said static memory device to said volatile memory device; Device characterized in that.