WO2018082455A1 - 功率器件及其制造方法 - Google Patents

功率器件及其制造方法 Download PDF

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Publication number
WO2018082455A1
WO2018082455A1 PCT/CN2017/107010 CN2017107010W WO2018082455A1 WO 2018082455 A1 WO2018082455 A1 WO 2018082455A1 CN 2017107010 W CN2017107010 W CN 2017107010W WO 2018082455 A1 WO2018082455 A1 WO 2018082455A1
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region
doping
doped
power device
regions
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PCT/CN2017/107010
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English (en)
French (fr)
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张邵华
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杭州士兰微电子股份有限公司
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Application filed by 杭州士兰微电子股份有限公司 filed Critical 杭州士兰微电子股份有限公司
Priority to US16/306,333 priority Critical patent/US10937859B2/en
Priority to JP2019516049A priority patent/JP6705944B2/ja
Priority to EP17866656.6A priority patent/EP3506365A4/en
Publication of WO2018082455A1 publication Critical patent/WO2018082455A1/zh
Priority to US16/206,568 priority patent/US10923563B2/en

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Definitions

  • the present invention relates to a power device, and more particularly to a power device including a charge compensation structure.
  • Power devices are mainly used in high-power power supply circuits and control circuits, for example as switching elements or rectifying elements.
  • doped regions of different doping types form a PN junction, thereby implementing the function of a diode or transistor.
  • Power devices typically require large currents to be carried at high voltages in applications.
  • power devices need to have high breakdown voltages in order to meet the needs of high voltage applications and to improve device reliability and lifetime.
  • the power device needs to have a low on-resistance.
  • a power device of the charge compensation type is disclosed in US Pat. No. 5,216,275 and US Pat. No. 4,754,310, in which a plurality of P-type doped regions and a plurality of N-type doped regions are alternately laterally arranged or vertically stacked.
  • one of the P-doped region and the N-type doped region provides a low impedance conductive path.
  • the charges of the P-type doped region and the N-type doped region adjacent to each other may be depleted by each other.
  • a power compensation type power device can significantly reduce the on-resistance, thereby reducing power consumption.
  • Another improved power device includes a loop region and a cell region surrounded by a loop region.
  • a P-type doped region and an N-type doped region of the power device are formed in the cell region, and additional P-type doped regions and N-type doped regions are formed in the ring region.
  • the ring zone is critical to the high voltage and reliability characteristics of power devices. When the device is turned off, the ring region acts to alleviate the electric field at the edge of the device, especially at high temperatures and high voltages, reducing the impact of the electric field on the oxide layer on the surface of the device and reducing the leakage current of the device at high temperatures.
  • the withstand voltage of the ring region is higher than the withstand voltage of the cell region, and thus, when the device is broken down, most of the current can flow out from the cell region.
  • the area of the cell area is much larger than the area of the ring area, which is conducive to improving the avalanche capability of the device.
  • a power device comprising: a semiconductor substrate; a first doped region on the semiconductor substrate; and a plurality of first regions in the first region of the first doped region a second doped region; and a plurality of third doped regions in the second region of the first doped region, wherein the semiconductor substrate and the first doped region are respectively a first doping type
  • the plurality of second doped regions and the plurality of third doped regions are respectively a second doping type, and the second doping type is opposite to the first doping type, the plurality of second doping regions Separating from the first predetermined spacing from each other, forming a first charge compensation structure with the first doped region, the first charge compensation structure and the semiconductor substrate being located on a current channel, the plurality of third doped regions Separating from each other by a second predetermined spacing, a second charge compensation structure is formed with the first doped region, the second charge compensation structure for dispersing a continuous surface electric field of the power device.
  • the first charge compensation structure is located in a cell region of the power device
  • the second charge compensation structure is located in a ring region of the power device, and the ring region surrounds the cell region.
  • the plurality of second doped regions and the plurality of third doped regions respectively extend in the longitudinal direction toward the semiconductor substrate in the first doped region, and the doping concentration is nonlinear Reduced.
  • the average doping concentration of the plurality of second doping regions and the plurality of third doping regions are respectively smaller than the average doping concentration of the first doping region.
  • an average doping concentration of the plurality of second doping regions is greater than an average doping concentration of the plurality of third doping regions, thereby reducing the cell region by using a difference in the average doping concentration
  • the on-resistance and the breakdown voltage of the cell region are increased.
  • the average doping concentration of the plurality of second doping regions is 10% or more greater than the average doping concentration of the plurality of third doping regions.
  • the plurality of second doped regions respectively include a first sub-region and a second sub-region, wherein an average doping concentration of the first sub-region is smaller than a doping concentration of the first doped region, The average doping concentration of the second sub-region is equal to the doping concentration of the first doped region.
  • the average doping concentration of the first sub-region is 20% or more smaller than the average doping concentration of the first doped region.
  • the plurality of second doped regions have a first lateral dimension
  • the plurality of third doped regions have a second lateral dimension
  • the first lateral dimension is greater than the second lateral dimension
  • the ratio of the first lateral dimension to the first predetermined spacing is equal to the ratio of the second lateral dimension to the second predetermined spacing.
  • the sum of the first lateral dimension and the first predetermined spacing is equal to an integral multiple of the sum of the second lateral dimension and the second predetermined spacing.
  • the plurality of second doping regions adopt a first ion implantation dose during ion implantation
  • the plurality of third doping regions adopt a second ion implantation dose during ion implantation
  • the second ion implantation dose ranges from 2E12 to 2E13 cm-2.
  • the first ion implantation dose is the same as the second ion implantation dose.
  • the first ion implantation dose is 20% or more higher than the second ion implantation dose.
  • the plurality of second doped regions and the plurality of third doped regions are respectively formed in deep trenches, the deep trenches in the first doped region in a longitudinal direction toward the semiconductor The substrate extends and the lateral dimension decreases.
  • the deep trenches are formed by etching and a different lateral etch angle is used to obtain a laterally reduced shape.
  • the lower portion of the deep trench is etched at an etching angle of 85° to 87°, and the upper portion is etched at an etching angle of 88° to 89°.
  • the cell region further includes: a plurality of fourth doped regions respectively located above the plurality of second doped regions; and a plurality of fifth doped regions respectively located in the plurality of fourth doped regions In the miscellaneous area.
  • the cell region further includes: a plurality of sixth doping regions respectively located in the plurality of fourth doping regions and serving as the terminals of the plurality of fourth doping regions.
  • the cell region further includes: a plurality of gate stacks respectively including a gate dielectric and a gate conductor, at least a portion being located between the plurality of fifth doped regions and the first doped region,
  • the plurality of fourth doped regions and the plurality of fifth doped regions are respectively a second doping type and a first doping type
  • the power device is a MOSFET
  • the semiconductor substrate the a plurality of fourth doping regions, the plurality of fifth doping regions respectively serving as a drain region, a well region and a source region of the MOSFET, wherein the plurality of fourth doping regions are located in the plurality of fifth doping regions
  • a channel is formed between the region and the first doped region.
  • the plurality of fourth doping regions and the plurality of fifth doping regions are respectively a second doping type, wherein the power device is a diode, the plurality of fourth doping regions,
  • the semiconductor substrate serves as the anode and cathode of the diode, respectively.
  • the ring region further includes: a seventh doping region, the seventh doping region is a second doping type, the seventh doping region is located in the first doping region; and the eighth a doped region, the eighth doped region is a second doping type, the eighth doped region is located in the first doped region, and the plurality of third doped regions and the first The seven doped regions are spaced apart, wherein the seventh doped region extends laterally to at least one of the plurality of fourth doped regions in the cell region to form a main junction, and The surface of the first doped region extends longitudinally from the surface to a predetermined depth, in contact with at least some of the plurality of third doped regions, such that at least some of the plurality of third doped regions are doped The doped region is coupled to at least some of the plurality of second doped regions via the main junction, the eighth doped region defining a perimeter of the power device and acting as a turn-off ring.
  • the method further includes: an interlayer dielectric layer; a first electrode, the first electrode is electrically connected to the plurality of fifth doped regions through the interlayer dielectric layer; and a second electrode, the second electrode Electrically connecting to the eighth doped region through the interlayer dielectric layer; and a third electrode electrically connected to the semiconductor substrate.
  • the first doping type is one of an N type and a P type
  • the second doping type is the other of an N type and a P type.
  • the power device is one selected from the group consisting of a metal oxide semiconductor field effect transistor, an insulated gate bipolar transistor, and a diode.
  • a method of fabricating a power device includes: forming a first doped region on a semiconductor substrate; forming a plurality of second doped regions in a first region of the first doped region a plurality of third doped regions are formed in the second region of the first doped region, wherein the semiconductor substrate and the first doped region are respectively a first doping type
  • the plurality of second doping regions and the plurality of third doping regions are respectively a second doping type, the second doping type is opposite to the first doping type, and the plurality of second doping regions are separated from each other Opening a first predetermined pitch, forming a first charge compensation structure with the first doped region, the first charge compensation structure and the semiconductor substrate are located on a current channel, and the plurality of third doped regions are separated from each other Opening a second predetermined spacing, forming a second charge compensation structure with the first doped region, the second charge compensation structure for dispersing a continuous surface electric field of the power device.
  • an average doping concentration of the plurality of second doping regions is greater than an average doping concentration of the plurality of third doping regions, thereby reducing the cell region by using a difference in the average doping concentration
  • the on-resistance and the breakdown voltage of the cell region are increased.
  • forming a plurality of second doped regions in the first region of the first doped region comprises performing first ion implantation via a first mask, forming in a second region of the first doped region The plurality of third doped regions includes a second ion implantation via the second mask.
  • the opening of the first mask has a first lateral dimension
  • the opening of the second mask has a second lateral dimension
  • the first lateral dimension is greater than the second lateral dimension
  • a first ion implantation dose is used in the first ion implantation, and a second ion implantation dose is used in the second ion implantation, the first ion implantation dose and the second ion implantation dose range It is 2E12 to 2E13cm-2.
  • the first ion implantation dose is the same as the second ion implantation dose.
  • the first ion implantation dose is 20% or more higher than the second ion implantation dose.
  • forming a plurality of second doped regions in the first region of the first doped region comprises filling a plurality of first epitaxial layers in the first deep trench, and second in the first doped region Forming the plurality of third doped regions in the region includes filling a plurality of second epitaxial layers in the first deep trench.
  • the first deep trench and the second deep trench extend in the longitudinal direction toward the semiconductor substrate in the first doped region, and the lateral dimension is reduced.
  • the deep trenches are formed by etching and a different lateral etch angle is used to obtain a laterally reduced shape.
  • the lower portion of the deep trench is etched at an etching angle of 85° to 87°, and the upper portion is etched at an etching angle of 88° to 89°.
  • a first charge compensation structure and a second charge compensation structure are formed in the cell region and the ring region of the power device, respectively. Since the first charge compensation structure and the second charge compensation structure can be simultaneously formed using the same process, the power device of this embodiment does not increase process complexity and cost.
  • the first charge compensation structure includes P-type doped regions and N-type doped regions adjacent to each other, the charges of the two can be depleted by each other, so that the on-resistance of the power device can be significantly reduced and Reduce power consumption.
  • the depletion layer in the edge region of the cell is expanded, which is advantageous for alleviating the reverse electric field formed in the edge region of the cell region, thereby improving the breakdown voltage of the power device.
  • the on-resistance and the increase in the cell region are simultaneously reduced by the difference in the average doping concentration of the P-type doped regions in the first charge compensation structure and the second charge compensation structure.
  • the breakdown voltage of the cell region is simultaneously reduced.
  • different ion implantation steps may be employed in forming the first charge compensation structure and the second charge compensation structure to obtain doping of the P-type doping region in the first charge compensation structure and the second charge compensation structure.
  • Concentration difference may be employed in forming the first charge compensation structure and the second charge compensation structure to obtain doping of the P-type doping region in the first charge compensation structure and the second charge compensation structure.
  • Concentration difference may be employed in forming the first charge compensation structure and the second charge compensation structure to obtain doping of the P-type doping region in the first charge compensation structure and the second charge compensation structure.
  • Concentration difference may be employed in forming the first charge compensation structure and the second charge compensation structure to obtain doping of the P-type doping region in the first charge compensation structure and the second charge compensation structure.
  • the present invention improves the power by adjusting the doping concentration of the P-type doping region in the first charge compensation structure and the second charge compensation structure without adding any process complexity and cost.
  • the on-resistance and breakdown voltage requirements of the device are compared with the prior art, the present invention improves the power by adjusting the doping concentration of the P-type doping region in the first charge compensation structure and the second charge compensation structure without adding any process complexity and cost.
  • FIG. 1 and 2 respectively show a cross-sectional view and a plan view of a power device in accordance with a first embodiment of the present invention.
  • FIG 3 shows a doping concentration profile of each doped region in a power device in accordance with a first embodiment of the present invention.
  • 4 and 5 respectively show an on-resistance profile and a breakdown voltage profile of a power device according to a first embodiment of the present invention.
  • Figures 6a to 6h show cross-sectional views of different stages of a method of fabricating a power device in accordance with a second embodiment of the present invention.
  • Figure 7 shows a cross-sectional view of a power device in accordance with a third embodiment of the present invention.
  • Figure 8 shows a cross-sectional view of a power device in accordance with a fourth embodiment of the present invention.
  • the present invention can be embodied in various forms, some of which are described below.
  • FIG. 1 and 2 respectively show a cross-sectional view and a plan view of a power device according to a first embodiment of the present invention, wherein Fig. 1 is a cross-sectional view taken along line AA' in the plan view shown in Fig. 2.
  • power device 100 is a metal oxide semiconductor field effect transistor (MOSFET).
  • MOSFET metal oxide semiconductor field effect transistor
  • N-type MOSFET will be described as an example, however, the present invention is not limited thereto.
  • power device 100 includes a cell region 110 and a ring region 120 surrounding cell region 110.
  • the loop region 120 is a closed shape surrounding the cell region 110.
  • the cell region 110 and the ring region 120 each include a plurality of first doped regions 102 and a plurality of P-type doped regions.
  • the first doped region 102 and the P-doped region in the cell region 110 provide a source region, a drain region, a channel, and a compensation region, thereby forming a current path when the power device is turned on.
  • the first doped region 102 and the third doped region 121 in the ring region 120 serve to disperse the surface electric field at the edge of the power device.
  • cell region 110 and the ring region 120 are shown.
  • the cell region 110 in the figure only contains a schematic diagram of the longitudinal structure of two cells, and in the actual product, the number of cells is more than two, and the ring region 110 contains only five third doping regions 121. In actual products, there may be less than or more than this amount.
  • cell region 110 and ring region 120 include a common semiconductor substrate 101 and a first doped region 102 on semiconductor substrate 101.
  • the semiconductor substrate 101 is, for example, a silicon substrate, and the doping type is N++ type, and the first doping region 102 is, for example, an in-situ doped epitaxial semiconductor layer, and the doping type is N-type.
  • the semiconductor substrate 101 serves as a drain region of the MOSFET.
  • a plurality of second doping regions 111 of a doping type P-type are formed in the first doping region 102.
  • the first doping region 102 is opposite to the doping type of the plurality of second doping regions 111, and the plurality of second doping regions 111 are alternately distributed in the first doping region 102 to form the first charge compensation structure 110a.
  • a plurality of third doping regions 121 of a doping type P-type are formed in the first doping region 102.
  • the first doping region 102 is opposite to the doping type of the plurality of third doping regions 121, and the plurality of third doping regions 121 are alternately distributed in the first doping region 102 to form a second charge compensation structure 120a.
  • the plurality of second doping regions 111 and the plurality of third doping regions 121 respectively have a doping concentration distribution reduced from a top end to a bottom end, and each doped region may be composed of a plurality of stacked epitaxial layers .
  • a plurality of fourth doping regions 112 are formed over the plurality of second doping regions 111, and A fifth doping region 113 is formed in the fourth doping region 112.
  • the fourth doping region 112 and the fifth doping region 113 are, for example, doped regions formed by ion implantation, and the doping types are P-type and N+-type, respectively.
  • the fourth doping region 112 serves as a body well region of the MOSFET, and the fifth doping region 113 serves as a source region of the MOSFET.
  • the bottom of the fourth doping region 112 is in contact with a corresponding one of the second doping regions 111.
  • a sixth doping region 114 may also be formed in the fourth doping region 112.
  • the sixth doping region 114 is, for example, a doping region formed by ion implantation, and the doping type is respectively P+ type.
  • the sixth doping region 114 extends into the fourth doping region 112 and is adjacent to the fifth doping region 113.
  • the sixth doped region 114 serves as the terminal for the body well region.
  • a gate stack including a gate dielectric 115 and a gate conductor 116 is formed on the surfaces of the first doping region 102 and the fourth doping region 112. At least a portion of the gate conductor 116 extends laterally from above the first doped region 102 to above the fifth doped region 113. The portion of the fourth doped region 112 between the first doped region 102 and the fifth doped region 113 below the gate conductor 116 forms a channel region of the MOSFET.
  • a seventh doping region 104 is formed in the first doping region 102.
  • the seventh doping region 104 is, for example, a doping region formed by ion implantation, and the doping type is P-type.
  • the seventh doped region 104 extends laterally to the fourth doped region 112 to form a main junction.
  • the seventh doping region 104 extends longitudinally from the surface to a predetermined depth, and is in contact with a portion of the third doping region 121 such that a portion of the fourth doping region 112 is connected to a portion of the third doping region 121 via the main junction.
  • an eighth doping region 122 is formed in the first doping region 102.
  • the eighth doped region 122 defines the perimeter of the MOSFET and acts as a turn-off ring.
  • the eighth doping region 122 is, for example, a doping region formed by ion implantation, and the doping type is a P+ type.
  • the eighth doping region 122 may be formed together with the fourth doping region 112, the doping type and the extension depth of the two being the same.
  • the interlayer dielectric layer 105 covers the device structure described above.
  • a through hole is formed in the interlayer dielectric layer 105.
  • the first electrode 118 contacts the fifth doping region 113 via the through hole, thereby providing an electrical connection to the source region.
  • the first electrode 118 also shorts the fifth doping region 113 and the sixth doping region 114 to each other.
  • the second electrode 128 contacts the eighth doping region 122 via the through hole, thereby providing an electrical connection to the cutoff ring.
  • a third electrode 108 is formed on a surface of the semiconductor substrate 101 opposite the first doped region 102 to provide an electrical connection to the drain region.
  • the first electrode 118 and the third electrode 108 serve as source and drain electrodes, respectively, of the MOSFET.
  • the horizontal X direction is a direction extending laterally along the ring region 120 to the cell region 110.
  • the vertical Y direction is a direction extending longitudinally along the semiconductor substrate 101 to the fifth doping region 113.
  • W1 is the width of the second doping region 111
  • S1 is the spacing between the second doping regions 111 adjacent to each other
  • W2 is the width of the third doping region 121
  • S2 is adjacent to each other
  • the spacing between the third doping regions 121, S3 is the spacing between the third doping region 121 and the second doping region 111 adjacent to each other.
  • the doping concentrations of the second doping region 111 and the third doping region 121 are non-linear.
  • the top ends of the second doping region 111 and the third doping region 121 are close to the source region of the power device, that is, the fifth doping region 113, and the bottom end is close to the drain region of the power device, that is, the semiconductor substrate 101.
  • the second doping region 111 and the third doping region 121 respectively have a doping concentration distribution that decreases from the top end to the bottom end.
  • a gate voltage is applied across gate conductor 116.
  • the power device is in an off state and a high voltage is applied to the drain.
  • the charge compensation structure forms a depletion layer that carries the voltage.
  • the first charge compensation structure can withstand a relatively high voltage under the mutual compensation of the second doping region 111 and the first doping region 102.
  • the size ratios of the second doping region 111 and the third doping region 121 are the same, since the size of the third doping region 121 of the second charge compensation structure is smaller than the size of the second doping region 111, in subsequent fabrication During the high temperature process, the impurity diffusion of the second doping region 111 and the diffusion of the third doping region 121 are different, so that the impurity of the third doping region 121 is more easily first by the same drain electrode voltage.
  • the impurity of the doped region 102 is compensated for depletion, that is, the absolute value of the compensation degree of the second charge compensation structure is smaller.
  • the withstand voltage of the ring region 110 of the present embodiment is higher than the withstand voltage of the cell region 110 by about 60V, which can fully meet the reliability requirements of the power device.
  • this processing method also reduces the size of the first doping region 102. That is to say, if the same processing method is used in the cell region 110, the current path is narrowed, and the on-resistance is significantly increased, which is not the result desired.
  • the second doping region 111 is divided into an II region and an I region, wherein the I region is a region near the vicinity of the drain.
  • the II area is the area near the source.
  • the doping concentration of the second doping region 111 is lower than the doping concentration of the first doping region 102; in the II region, the doping concentration of the second doping region 111 is equal to the doping of the first doping region 102 Miscellaneous concentration.
  • the second doping region 111 is divided into different sub-regions, and in the vertical Y direction, the compensation matching degree of the sub-region is changed from -20% to 0% from the region near the vicinity of the drain; In the area near the source, the compensation match of the sub-area remains unchanged at 0%.
  • the charge matching concentration is 0%, that is, the doping concentration of the second doping region 111 is equal to the doping concentration of the first doping region 102, and it is necessary to deliberately make two doping concentration mismatches in the sub-region near the drain.
  • the power device When the gate voltage of the power device is above a threshold voltage, the power device conducts and current flows from the drain electrode through the first doped region 102 to the source electrode. When the gate voltage of the power device is below the threshold voltage, the power device is turned off and the drain electrode will apply a high voltage.
  • the function of the ring region 120 is to mitigate the reverse electric field formed between the cell region 110 and the first doped region 102 of the edge region of the power device, thereby withstanding the drain voltage.
  • the ideal planar PN junction breakdown voltage is determined only by the concentration and thickness of the epitaxy.
  • the edge region of the actual device cell region exhibits a junction termination effect, that is, the depletion layer profile of the PN junction between the cell region 110 and the first doping region 102 near the edge of the power device is curved, and there is a PN.
  • the curvature effect of the knot PN junction curvature when voltage is applied in the reverse direction The strongest electric field appears at the largest position, and the early breakdown or the reverse leakage current of the PN junction increases, reducing the withstand voltage and reliability.
  • the ring region 120 surrounds the cell region 110, and the second charge compensation structure 120a is formed in the ring region 120. Due to the design of the doping concentration distribution of the third doping region 121 in the second charge compensation structure 120a, the depletion of the third doping region 121 and the first doping region 102 is more sufficient when a reverse voltage is applied, The depletion layer of the edge region of the cell is connected, thereby effectively extending the depletion layer at the edge of the cell region, reducing the curvature of the terminal and increasing the withstand voltage. At the same time, the movable carriers in the depletion layer in the ring region 120 are greatly reduced to form a high resistance region, which effectively reduces the reverse leakage current and improves the reliability.
  • the curve P1 is a doping concentration distribution curve of the second doping region 111 from the top end to the bottom end
  • the curve P2 is a doping concentration distribution curve of the third doping region 121 from the top end to the bottom end
  • the curve N is the first doping region 102 from Doping concentration profile from top to bottom.
  • the doping concentration of the second doping region 111 and the third doping region 121 is non-linear, decreasing from the top end to the bottom end, compared to the prior art power device.
  • the average doping concentration of the second doping region 111 and the third doping region 121 is lower than the average doping concentration of the first doping region 102. Further, the average doping concentration of the third doping region 121 is lower than the average doping concentration of the second doping region 111.
  • 4 and 5 respectively show an on-resistance profile and a breakdown voltage profile of a power device according to a first embodiment of the present invention.
  • FIG. 4 compares the on-resistance distribution comparison of the 600V power device manufactured by the prior art method and the method of the present embodiment, wherein the power device of the prior art is indicated by the mark A, and the symbol B is used.
  • the on-resistance of the power device fabricated in this embodiment is lower than that in the prior art, which benefits from reducing the doping concentration of the second doping region 111 near the source, and lowering the junction resistance.
  • the second charge compensation structure of the ring region 110 compensates for the absolute value of the matching degree, the withstand voltage of the ring region 110 is still higher than the withstand voltage of the cell region 110, ensuring reliability of the power device. Sex.
  • Figures 6a to 6h show cross-sectional views of different stages of a method of fabricating a power device in accordance with a second embodiment of the present invention.
  • a first epitaxial layer 1021 is epitaxially grown on the semiconductor substrate 101 as shown in FIG. 6a.
  • the semiconductor substrate 101 is, for example, a silicon substrate, and the doping type is N++ type.
  • the semiconductor substrate 101 has a specific resistance of 0.01 to 0.03 ohms*cm and a thickness of about 600 ⁇ m in a ⁇ 100> crystal orientation single crystal silicon substrate.
  • the first epitaxial layer 1021 is, for example, an epitaxial semiconductor layer doped in-situ at a temperature of 1050 to 1150 ° C by a method of decompression epitaxy, and the doping type is N-type.
  • the semiconductor substrate 101 will serve as a drain region of the MOSFET.
  • the thickness and resistivity of the first epitaxial layer 1021 vary greatly depending on the different withstand voltage specifications of the power device.
  • the first epitaxial layer 1021 has a thickness of, for example, 14 to 24 ⁇ m and a specific resistance of 0.8 to 3 ohms*cm.
  • the entire implantation of the N-type impurity is performed on the surface of the first epitaxial layer 1021, and phosphorus is usually used as the implant impurity, and the dose to be implanted is generally selected from 7E11 to 7E12 cm -2 .
  • a photoresist is applied on the surface of the first epitaxial layer 1021, and a photolithography step such as exposure, development, or the like is performed to form a photoresist mask PR1.
  • the photoresist mask PR1 includes a pattern of an implantation window, wherein a surface of the first epitaxial layer 1021 is exposed at a position corresponding to the second doped region and the third doped region. Impurity implantation is performed using a photoresist mask PR1 as shown in FIG. 6b.
  • boron can be used as a dopant for ion implantation, and the injected energy is generally selected from 60 to 180 KeV, and the dose is generally selected from 2E12 to 2E13 cm -2 .
  • the photoresist mask PR1 is removed by solvent dissolution or ashing.
  • the ion implantation forms a doped region 1111 at an implantation window position of the second doped region, and a doped region 1211 is formed at an implantation window position of the third doped region.
  • the doped regions 1111 and 1211 extend downward from the first epitaxial layer 1021 by a predetermined depth. Due to the difference in size of the implantation window, the doping concentration of the doping region 1211 is 10% smaller than that of the doping region 1111 even if the same implantation conditions are employed.
  • a second epitaxial layer 1022 is formed on the first epitaxial layer 1021, and doped regions 1112 and 1212 are formed in the second epitaxial layer 1022.
  • the thickness of the second epitaxial layer 1022 is usually 5 to 8 um, and the specific resistance is 0.8 to 3 ohms*cm.
  • the doped regions 1112 and 1212 extend downward from the second epitaxial layer 1022 by a predetermined depth.
  • the implantation window of the doping region 1112 is aligned with the previously formed doping region 1111 and the impurity implantation dose is the same, the implantation window of the doping region 1212 is aligned with the previously formed doping region 1211 and the impurity implantation dose is the same.
  • the doping concentration of the doping region 1212 is 10% smaller than that of the doping region 1112 even if the same implantation conditions are employed.
  • a stacked structure of a plurality of epitaxial layers is formed, and doped regions in the epitaxial layers are aligned.
  • the above steps are generally repeated 4 to 10 times, and in this embodiment, 4 times.
  • the thickness and resistivity of each of the growth epitaxes are the same as those of the second epitaxial layer 1022.
  • the impurity implantation dose of the doping regions 1111 to 1113 is nonlinearly changed, and the impurity implantation dose near the vicinity of the drain is 20% smaller than the impurity implantation dose near the source, and the doping regions 1211 to 1213
  • the impurity implantation dose is non-linearly variable, and the impurity implantation dose near the vicinity of the drain is 20% smaller than the impurity implantation dose near the source.
  • the impurity implantation dose of the doped region in the ring region is 10% smaller than the impurity implantation dose of the doped region in the cell region.
  • a fourth epitaxial layer 1024 is epitaxially grown on the third epitaxial layer 1023 as shown in FIG. 6d.
  • the thickness and resistivity of the fourth epitaxial layer 1024 may be slightly different from the previous epitaxy according to the parameter characteristics of the power device.
  • the fourth epitaxial layer 1024 has a thickness of 4 to 7 um and a resistivity of 1 to 4 ohms*cm.
  • thermal annealing is performed, and a silicon oxide layer 1025 having a thickness of 3000 to 6000 A is grown through a high temperature process of 1000 to 1150 °C.
  • a photoresist is applied on the surface of the silicon oxide layer 1025, and subjected to a photolithography step such as exposure, development, or the like to form a photoresist mask PR2.
  • the photoresist mask PR2 includes a pattern of an implantation window in which a surface of the silicon oxide layer 1025 is exposed at a position corresponding to the seventh doping region. Impurity implantation is performed using the photoresist mask PR2 to form a seventh doping region 104 as shown in FIG. 6e.
  • the surface silicon dioxide can be removed by etching before ion implantation. Then implant the impurity boron.
  • the energy of ion implantation is 40 to 100 KeV, and the dose is 3E12 to 3E13 cm -2 .
  • the photoresist mask PR1 is removed by solvent dissolution or ashing.
  • This step involves heat treatment at a temperature of 1100 to 1200 ° C for a period of about 60 to 300 minutes.
  • the doped regions 1111 to 1113 and 1211 to 1213 in the epitaxial layers 1021 to 1023 diffuse to the periphery.
  • the doped regions 1111 to 1113 are connected to each other to form a second doping region 111
  • the doping regions 1211 to 1213 are connected to each other to form a second doping region 121.
  • a silicon oxide layer 105 having a thickness of 1.6 to 0.8 um is grown on the surface of the fourth epitaxial layer 1024, as shown in FIG. 6f.
  • a photoresist is applied on the surface of the silicon oxide layer 105, and subjected to a photolithography step such as exposure, development, or the like to form a photoresist mask.
  • the photoresist mask includes a pattern of etched windows, wherein the etched window exposes a surface of the first doped region 102 over the entire area of the cell region and at a location where the ring region corresponds to the turn-off ring.
  • the wet etching is used to remove the entire region of the cell region as well as the ring region and the silicon oxide layer 105 on the cut-off ring. After etching, the photoresist mask is removed by solvent dissolution or ashing.
  • a thin oxide layer having a thickness of 200 to 600 A is thermally grown as a barrier layer for ion implantation.
  • An overall implantation of the N-type impurity is performed to increase the N-type doping concentration on the surface of the cell region 110.
  • Phosphorus is usually used as an impurity to be implanted, and the amount of the agent to be injected is generally selected from 7E11 to 7E12 cm -2 .
  • a temperature of 1100 to 1150 ° C is usually selected to diffuse the impurities to a depth of 1 to 3 um.
  • silicon oxide is thermally grown under a temperature of 900 to 1000 ° C to form a gate dielectric 115.
  • the thickness of the gate dielectric 115 is generally 800 to 1200 ⁇ .
  • the deposition of polycrystalline silicon is carried out by the LPCVD method, and the thickness of the deposited polycrystalline silicon is 3,000 to 5,000 ⁇ .
  • the polysilicon is doped with impurities, and the impurity doping may be performed by diffusion or implantation. After doping polysilicon, the general sheet resistance is distributed at 5 to 30 ohm/cm.
  • a photoresist is applied, and a photolithography step such as exposure, development, or the like is performed to form a photoresist mask.
  • the photoresist mask includes a pattern of etched windows, wherein the etched window exposes a surface of the polysilicon at a location other than the gate conductor of the cell region.
  • the exposed portion of the polysilicon is removed by wet etching to form the gate conductor 116 as shown in Figure 6g. After etching, the photoresist mask is removed by solvent dissolution or ashing.
  • the fourth doped region 112 serves as a body well region of the power device 100.
  • the dose injected into the body well region is selected based on the power device threshold requirements.
  • a typical 3V threshold is used at a dose of 2E13 to 5E13 cm -2 .
  • the fourth doping region 112 After driving at a high temperature of 1100 ° C to 1150 ° C, the fourth doping region 112 reaches a junction depth of 2 to 4 ⁇ m and is in contact with the second doping region 111.
  • ion implantation is performed through the photoresist mask to form a sixth doping region 114 in the fourth doping region 112.
  • the sixth doping region 114 serves as an extraction terminal of the body well region.
  • the dose of the ion implantation is, for example, a dose of 1E15 to 5E15 cm -2 using boron impurities as a dopant.
  • the sixth doping region 114 After the formation of the sixth doping region 114, a thermal process of 900 to 1000 ° C for 30 to 90 minutes forms a junction depth of 0.5 to 1.5 um.
  • the sixth doped region 114 is connected to the fourth doped region 112 to form a contact of the body well region.
  • ion implantation is performed via a photoresist mask to form a fifth doping region 113 in the fourth doping region 112.
  • the fifth doping region 113 serves as a source region of the power device.
  • the dose of the ion implantation is, for example, a dose of 1E15 to 5E15 cm -2 using arsenic impurities as a dopant.
  • the sixth doping region 114 extends into the fourth doping region 112 and is adjacent to the fifth doping region 113.
  • an interlayer dielectric layer 105 is formed on the surface of the device structure.
  • the interlayer dielectric layer 105 is, for example, an insulating layer formed by deposition or a silica glass containing boric acid.
  • the interlayer dielectric layer 105 is etched using a photoresist mask to form a through hole. Further, the deposited metal layer fills the through hole, and the thickness of the metal layer is, for example, 3 to 4.5 um.
  • the metal layer is patterned to form a first electrode 118 and a second electrode 128.
  • the first electrode 118 contacts the fifth doping region 113 via the through hole, thereby providing an electrical connection to the source region. At the same time, the first electrode 118 also shorts the fifth doping region 113 and the sixth doping region 114 to each other.
  • the second electrode 128 contacts the eighth doping region 122 via the through hole, thereby providing an electrical connection to the cutoff ring.
  • the semiconductor substrate 101 is thinned so that the thickness of the semiconductor substrate 101 reaches 200 to 300 um.
  • a third electrode 108 is formed on a surface of the semiconductor substrate 101 opposite the first doped region 102 to provide an electrical connection to the drain region.
  • the first electrode 118 and the third electrode 108 serve as source and drain electrodes, respectively, of the MOSFET.
  • the structure of the power device 100 formed by the manufacturing method is as shown in Fig. 6h.
  • Figure 7 shows a cross-sectional view of a power device in accordance with a third embodiment of the present invention.
  • power device 200 is a metal oxide semiconductor field effect transistor (MOSFET).
  • MOSFET metal oxide semiconductor field effect transistor
  • N-type MOSFET will be described as an example, however, the present invention is not limited thereto.
  • cell region 110 and the ring region 120 are shown.
  • the cell region 110 in the figure only contains a schematic diagram of the longitudinal structure of two cells, and in the actual product, the number of cells is more than two, and the ring region 110 only contains five third doping regions 221 In actual products, there may be less than or more than this amount.
  • cell region 110 and ring region 120 include a common semiconductor substrate 101 and a first doped region 102 on semiconductor substrate 101.
  • the semiconductor substrate 101 is, for example, a silicon substrate, and the doping type is N++ type, and the first doping region 102 is, for example, an in-situ doped epitaxial semiconductor layer, and the doping type is N-type.
  • the semiconductor substrate 101 serves as a drain region of the MOSFET.
  • a plurality of second doping regions 211 of a doping type P-type are formed in the first doping region 102.
  • the first doping region 102 is opposite to the doping type of the plurality of second doping regions 211, and the plurality of second doping regions 211 are alternately distributed in the first doping region 102 to form a first charge compensation structure.
  • a plurality of third doping regions 221 of a doping type P-type are formed in the first doping region 102.
  • the first doping region 102 is opposite to the doping type of the plurality of third doping regions 221, and the plurality of third doping regions 221 are alternately distributed in the first doping region 102 to form a second charge compensation structure.
  • the plurality of second doping regions 211 and the plurality of third doping regions 221 respectively have a doping concentration distribution decreasing from the top end to the bottom end, and each doping region may be composed of a plurality of stacked epitaxial layers .
  • a plurality of fourth doping regions 112 are formed over the plurality of second doping regions 211, and a fifth doping region 113 is formed in the fourth doping region 112.
  • the fourth doping region 112 and the fifth doping region 113 are, for example, doped regions formed by ion implantation, and the doping types are P-type and N+-type, respectively.
  • the fourth doping region 112 serves as a body well region of the MOSFET, and the fifth doping region 113 serves as a source region of the MOSFET.
  • the bottom of the fourth doping region 112 is in contact with a corresponding one of the second doping regions 211.
  • a sixth doping region 114 may also be formed in the fourth doping region 112.
  • the sixth doping region 114 is, for example, a doping region formed by ion implantation, and the doping type is respectively P+ type.
  • the sixth doping region 114 extends into the fourth doping region 112 and is adjacent to the fifth doping region 113.
  • the sixth doped region 114 serves as the terminal for the body well region.
  • a gate dielectric 115 and a gate conductor 116 are formed on the surfaces of the first doping region 102 and the fourth doping region 112. Gate stack. The gate conductor 116 extends laterally from the first doped region 102 to the fifth doped region 113. At least a portion of the gate conductor 116 is located above the fourth doped region 112 such that a portion of the fourth doped region 112 between the first doped region 102 and the fifth doped region 113 forms a channel region of the MOSFET.
  • a seventh doping region 104 is formed in the first doping region 102.
  • the seventh doping region 104 is, for example, a doping region formed by ion implantation, and the doping type is P-type.
  • the seventh doped region 104 extends laterally to the fourth doped region 112 to form a main junction.
  • the seventh doping region 104 extends longitudinally from the surface to a predetermined depth, and is in contact with a portion of the third doping region 221 such that a portion of the fourth doping region 112 is connected to a portion of the third doping region 221 via the main junction.
  • an eighth doping region 122 is formed in the first doping region 102.
  • the eighth doped region 122 defines the perimeter of the MOSFET and acts as a turn-off ring.
  • the eighth doping region 122 is, for example, a doping region formed by ion implantation, and the doping type is a P+ type.
  • the eighth doping region 122 may be formed together with the fourth doping region 112, the doping type and the extension depth of the two being the same.
  • the interlayer dielectric layer 105 covers the device structure described above.
  • a through hole is formed in the interlayer dielectric layer 105.
  • the first electrode 118 contacts the fifth doping region 113 via the through hole, thereby providing an electrical connection to the source region.
  • the first electrode 118 also shorts the fifth doping region 113 and the sixth doping region 114 to each other.
  • the second electrode 128 contacts the eighth doping region 122 via the through hole, thereby providing an electrical connection to the cutoff ring.
  • a third electrode 108 is formed on a surface of the semiconductor substrate 101 opposite the first doped region 102 to provide an electrical connection to the drain region.
  • the first electrode 118 and the third electrode 108 serve as source and drain electrodes, respectively, of the MOSFET.
  • the second doping region 211 and the third doping region 221 are simultaneously formed. Different from the first embodiment, the second doping region 211 and the third doping region 221 are formed by deep trench etching and epitaxial backfilling, and the resistivities of the two are completely the same. However, the shapes of the bottom ends of the second doping region 211 and the third doping region 221 are different due to the difference in the shape of the deep trenches.
  • the horizontal X direction is a direction extending laterally along the ring region 120 to the cell region 110.
  • the vertical Y direction is a direction extending longitudinally along the semiconductor substrate 101 to the fifth doping region 113.
  • W1 is the width of the second doping region 211
  • S1 is the spacing between the second doping regions 211 adjacent to each other
  • W2 is the width of the third doping region 221, and S2 is adjacent to each other
  • the spacing between the third doping regions 221, S3 is the spacing between the third doping regions 221 and the second doping regions 211 adjacent to each other.
  • the doping concentrations of the second doping region 211 and the third doping region 221 are non-linear.
  • the top ends of the second doping region 211 and the third doping region 221 are close to the source region of the power device, that is, the fifth doping region 113, and the bottom end is close to the drain region of the power device, that is, the semiconductor substrate 101.
  • the second doping region 211 and the third doping region 221 respectively have a doping concentration distribution that decreases from the top end to the bottom end.
  • the region of the first charge compensation structure near the drain is an I region; the region of the first charge compensation structure near the source is a region II.
  • the morphology of the P-type epitaxial filling in the second doping region 111 in the I region and the II region is different.
  • the Y-direction interface of the second doped region 211 and the first doped region 102 in the I region has a small slope with respect to the horizontal X-axis; in the II region, the Y-direction boundary of the second doped region 211 and the first doped region 102 The slope is larger with respect to the horizontal X axis.
  • the reason for the difference in slope is that the etching angles in the I region and the II region are different when the deep trench is etched. Generally, an etching angle of 85° to 87° is used in the I region, and an etching angle of 88° to 89° is used in the II region.
  • the doping concentration of the first doping region 102 in the I region is higher than the doping concentration of the second doping region 111 due to the slope angle; II
  • the doping concentration of the first doping region 102 in the region is approximately equal to the doping concentration of the second doping region 111.
  • the doping concentration change of the second doping region 111 exhibits a nonlinear change, and the average doping concentration thereof is lower than the average doping concentration of the first doping region 102.
  • Figure 8 shows a cross-sectional view of a power device in accordance with a fourth embodiment of the present invention.
  • power device 300 is a diode.
  • cell region 110 and the ring region 120 are shown.
  • the cell region 110 in the figure only contains a schematic diagram of the longitudinal structure of two cells, and in the actual product, the number of cells is more than two, and the ring region 110 contains only five third doping regions 121. In actual products, there may be less than or more than this amount.
  • cell region 110 and ring region 120 include a common semiconductor substrate 101 and a first doped region 102 on semiconductor substrate 101.
  • the semiconductor substrate 101 is, for example, a silicon substrate, and the doping type is N++ type, and the first doping region 102 is, for example, an in-situ doped epitaxial semiconductor layer, and the doping type is N-type.
  • the semiconductor substrate 101 serves as a cathode of the diode.
  • a plurality of second doping regions 111 of a doping type P-type are formed in the first doping region 102.
  • the first doping region 102 is opposite to the doping type of the plurality of second doping regions 111, and the plurality of second doping regions 111 are alternately distributed in the first doping region 102 to form a first charge compensation structure.
  • a plurality of third doping regions 121 of a doping type P-type are formed in the first doping region 102.
  • the first doping region 102 is opposite to the doping type of the plurality of third doping regions 121, and the plurality of third doping regions 121 are alternately distributed in the first doping region 102 to form a second charge compensation structure.
  • the plurality of second doping regions 111 and the plurality of third doping regions 121 respectively have a doping concentration distribution reduced from a top end to a bottom end, and each doped region may be composed of a plurality of stacked epitaxial layers .
  • a plurality of fourth doping regions 112 are formed over the plurality of second doping regions 111, and a fifth doping region 313 is formed in the fourth doping region 112.
  • the fourth doping region 112 and the fifth doping region 313 are, for example, doped regions formed by ion implantation, and the doping types are P-type and P+-type, respectively.
  • the fourth doped region 112 serves as the anode of the diode.
  • Fourth doping The bottom of the region 112 is in contact with a corresponding one of the second doped regions 111.
  • a fifth doping region 313 may also be formed in the fourth doping region 112.
  • the fifth doping region 313 is, for example, a doping region formed by ion implantation, and the doping type is respectively P+ type.
  • the fifth doping region 313 extends to the fourth doping region 112.
  • the fifth doped region 313 serves as the terminal for the anode.
  • a seventh doping region 104 is formed in the first doping region 102.
  • the seventh doping region 104 is, for example, a doping region formed by ion implantation, and the doping type is P-type.
  • the seventh doped region 104 extends laterally to the fourth doped region 112 to form a main junction.
  • the seventh doping region 104 extends longitudinally from the surface to a predetermined depth, and is in contact with a portion of the third doping region 121 such that a portion of the fourth doping region 112 is connected to a portion of the third doping region 121 via the main junction.
  • an eighth doping region 122 is formed in the first doping region 102.
  • the eighth doped region 122 defines the perimeter of the diode and acts as a turn-off ring.
  • the eighth doping region 122 is, for example, a doping region formed by ion implantation, and the doping type is a P+ type.
  • the eighth doping region 122 may be formed together with the fourth doping region 112, the doping type and the extension depth of the two being the same.
  • the interlayer dielectric layer 105 covers the device structure described above.
  • a through hole is formed in the interlayer dielectric layer 105.
  • the first electrode 118 contacts the fifth doping region 313 via the through hole to provide an electrical connection to the anode.
  • the first electrode 118 also shorts the fifth doping region 313 and the sixth doping region 114 to each other.
  • the second electrode 128 contacts the eighth doping region 122 via the through hole, thereby providing an electrical connection to the cutoff ring.
  • a third electrode 108 is formed on a surface of the semiconductor substrate 101 opposite the first doped region 102 to provide an electrical connection to the cathode.
  • the first electrode 118 and the third electrode 108 function as an anode electrode and a cathode electrode of the diode, respectively.
  • the horizontal X direction is a direction extending laterally along the ring region 120 to the cell region 110.
  • the vertical Y direction is a direction extending longitudinally along the semiconductor substrate 101 to the fifth doping region 313.
  • W1 is the width of the second doping region 111
  • S1 is the spacing between the second doping regions 111 adjacent to each other
  • W2 is the width of the third doping region 121
  • S2 is adjacent to each other
  • the spacing between the third doping regions 121, S3 is the spacing between the third doping region 121 and the second doping region 111 adjacent to each other.
  • the doping concentrations of the second doping region 111 and the third doping region 121 are non-linear.
  • the top ends of the second doping region 111 and the third doping region 121 are close to the anode of the diode, that is, the fifth doping region 313, and the bottom end is close to the cathode of the diode, that is, the semiconductor substrate 101.
  • the second doping region 111 and the third doping region 121 respectively have a doping concentration distribution that decreases from the top end to the bottom end.
  • the power device may be a high voltage power device, an IGBT power device, or a diode.
  • the power device structure includes a first doped region and a second doped region, and the two doped regions are alternately distributed.
  • the positions of the first doped region and the second doped region may be interchanged.

Abstract

一种功率器件（100）及其制造方法。所述功率器件（100）包括：半导体衬底（101）；位于所述半导体衬底（101）上的第一掺杂区（102）；位于所述第一掺杂区（102）的第一区域中的多个第二掺杂区（111）；以及位于所述第一掺杂区（102）的第二区域中的多个第三掺杂区（121），其中，所述多个第二掺杂区（111）彼此隔开第一预定间距（S1），与所述第一掺杂区（102）形成第一电荷补偿结构，所述第一电荷补偿结构和所述半导体衬底（101）位于电流通道上，所述多个第三掺杂区（121）彼此隔开第二预定间距（S2），与所述第一掺杂区（102）形成第二电荷补偿结构，所述第二电荷补偿结构用于分散所述功率器件（100）连续的表面电场。该功率器件（100）不仅可以稳定器件的耐压，提高可靠性，而且可以降低导通电阻。

Description

功率器件及其制造方法 技术领域
本发明涉及一种功率器件，尤其涉及包括电荷补偿结构的功率器件。
背景技术
功率器件主要用于大功率的电源电路和控制电路中，例如作为开关元件或整流元件。在功率器件中，不同掺杂类型的掺杂区形成PN结，从而实现二极管或晶体管的功能。功率器件在应用中通常需要在高电压下承载大电流。一方面，为了满足高电压应用的需求以及提高器件可靠性和寿命，功率器件需要具有高击穿电压。另一方面，为了降低功率器件自身的功耗和产生的热量，功率器件需要具有低导通电阻。
在美国专利US5216275和US4754310公开了电荷补偿类型的功率器件，其中多个P型掺杂区和多个N型掺杂区交替横向排列或垂直堆叠。在功率器件的导通状态，P型掺杂区和N型掺杂区之一提供低阻抗的导电路径。在功率器件的断开状态，彼此相邻的P型掺杂区和N型掺杂区的电荷可以相互耗尽。因而，电荷补偿类型的功率器件可以显著减小导通电阻，从而降低功耗。
另一种改进的功率器件包括环区和由环区围绕的元胞区。在元胞区中形成功率器件的P型掺杂区和N型掺杂区，在环区中形成附加的P型掺杂区和N型掺杂区。环区对于功率器件的高压特性和可靠性特性至关重要。当器件关断的时候，环区起到缓解器件边缘表面电场作用，尤其在高温和高压情况下，减小电场对于器件表面氧化层的冲击，降低高温下器件漏电流。通常而言，希望环区的耐压要比元胞区的耐压高一些，由此器件发生击穿的时候，大部分电流能从元胞区流出。元胞区的面积相对环区面积要大很多，有利于提高器件的雪崩能力。
期望在功率器件中包含上述两种结构，以同时减小导通电阻和提高耐压特性。然而，在实际应用中，电荷补偿型器件的导通电阻和耐压特性之间是一对矛盾参数。虽然可以通过增加N型掺杂区的杂质浓度，提高电流通道的电流能力，获得较小导通电阻。但是，由于N型掺杂区杂质浓度增加，对补偿匹配度的要求很高，很难重复做到N型掺杂区和P型掺杂区杂质浓度完全相同，两者杂区杂质浓度稍有偏差，耐压就会大幅度的降低，出现耐压不稳定的情况。尤其在环区，更加难做到提高耐压，改善可靠性的目的。
在包括电荷补偿和环区的功率器件中，仍然需要进一步改进环区结构，以兼顾导通电阻和击穿电压的要求。
发明内容
鉴于上述问题，本发明的目的是提供一种功率器件及其制造方法，其中，在功率器件的环区中采用附加的电荷补偿结构以以兼顾导通电阻和击穿电压的要求。
根据本发明的一方面，提供一种功率器件，包括：半导体衬底；位于所述半导体衬底上的第一掺杂区；位于所述第一掺杂区的第一区域中的多个第二掺杂区；以及位于所述第一掺杂区的第二区域中的多个第三掺杂区，其中，所述半导体衬底和所述第一掺杂区分别为第一掺杂类型，所述多个第二掺杂区和所述多个第三掺杂区分别为第二掺杂类型，第二掺杂类型与第一掺杂类型相反，所述多个第二掺杂区彼此隔开第一预定间距，与所述第一掺杂区形成第一电荷补偿结构，所述第一电荷补偿结构和所述半导体衬底位于电流通道上，所述多个第三掺杂区彼此隔开第二预定间距，与所述第一掺杂区形成第二电荷补偿结构，所述第二电荷补偿结构用于分散所述功率器件连续的表面电场。
优选地，所述第一电荷补偿结构位于所述功率器件的元胞区中，所述第二电荷补偿结构位于所述功率器件的环区中，所述环区围绕所述元胞区。
优选地，所述多个第二掺杂区和所述多个第三掺杂区分别在所述第一掺杂区中沿纵向方向朝着所述半导体衬底延伸，并且掺杂浓度非线性减小。
优选地，所述多个第二掺杂区和所述多个第三掺杂区的平均掺杂浓度分别小于所述第一掺杂区的平均掺杂浓度。
优选地，所述多个第二掺杂区的平均掺杂浓度大于所述多个第三掺杂区的平均掺杂浓度，从而利用所述平均掺杂浓度的差异减小所述元胞区的导通电阻和提高所述元胞区的击穿电压。
优选地，所述多个第二掺杂区的平均掺杂浓度比所述多个第三掺杂区的平均掺杂浓度大10％或更多。
优选地，所述多个第二掺杂区分别包括第一子区域和第二子区域，所述第一子区域的平均掺杂浓度小于所述第一掺杂区的掺杂浓度，所述第二子区域的平均掺杂浓度等于所述第一掺杂区的掺杂浓度。
优选地，所述第一子区域的平均掺杂浓度比所述第一掺杂区的平均掺杂浓度小20％或更多。
优选地，所述多个第二掺杂区具有第一横向尺寸，所述多个第三掺杂区具有第二横向尺寸，并且所述第一横向尺寸大于所述第二横向尺寸。
优选地，所述第一横向尺寸与所述第一预定间距的比值等于所述第二横向尺寸与所述第二预定间距的比值。
优选地，所述第一横向尺寸与所述第一预定间距之和等于所述第二横向尺寸与所述第二预定间距之和的整数倍。
优选地，所述多个第二掺杂区在离子注入时采用第一离子注入剂量，所述多个第三掺杂区在离子注入时采用第二离子注入剂量，所述第一离子注入剂量和所述第二离子注入剂量的范围为2E12～2E13cm-2。
优选地，所述第一离子注入剂量与所述第二离子注入剂量相同。
优选地，所述第一离子注入剂量比所述第二离子注入剂量高20％或更多。
优选地，所述多个第二掺杂区和所述多个第三掺杂区分别形成在深槽中，所述深槽在所述第一掺杂区中沿纵向方向朝着所述半导体衬底延伸，并且横向尺寸减小。
优选地，所述深槽采用蚀刻形成，并且采用不同的蚀刻角度获得横向尺寸减小的形状。
优选地，所述深槽的下部在蚀刻时采用的蚀刻角度为85°～87°，上部在蚀刻时采用的蚀刻角度为88°～89°。
优选地，所述元胞区还包括：多个第四掺杂区，分别位于所述多个第二掺杂区上方；以及多个第五掺杂区，分别位于所述多个第四掺杂区中。
优选地，所述元胞区还包括：多个第六掺杂区，分别位于所述多个第四掺杂区中，并且作为所述多个第四掺杂区的引出端。
优选地，所述元胞区还包括：多个栅叠层，分别包括栅极介质和栅极导体，至少一部分位于所述多个第五掺杂区和所述第一掺杂区之间，其中，所述多个第四掺杂区和所述多个第五掺杂区分别为第二掺杂类型和第一掺杂类型，所述功率器件为MOSFET，所述半导体衬底、所述多个第四掺杂区、所述多个第五掺杂区分别作为所述MOSFET的漏区、阱区和源区，所述多个第四掺杂区位于所述多个第五掺杂区和所述第一掺杂区之间形成沟道。
优选地，所述多个第四掺杂区和所述多个第五掺杂区分别为第二掺杂类型，其中，所述功率器件为二极管，所述多个第四掺杂区、所述半导体衬底分别作为所述二极管的阳极和阴极。
优选地，所述环区还包括：第七掺杂区，所述第七掺杂区为第二掺杂类型，所述第七掺杂区位于所述第一掺杂区中；以及第八掺杂区，所述第八掺杂区为第二掺杂类型，所述第八掺杂区位于所述第一掺杂区中，并且与所述多个第三掺杂区和所述第七掺杂区隔开，其中，所述第七掺杂区横向延伸至所述元胞区中的所述多个第四掺杂区中的至少一个掺杂区，形成主结，并且从所述第一掺杂区的表面从表面纵向延伸至预定深度，与所述多个第三掺杂区中的至少一些掺杂区接触，使得所述多个第三掺杂区中的至少一些掺杂区与所述多个第二掺杂区中的至少一些掺杂区经由所述主结相连接，所述第八掺杂区限定所述功率器件的周边且作为截止环。
优选地，还包括：层间介质层；第一电极，所述第一电极穿过所述层间介质层与所述多个第五掺杂区电连接；第二电极，所述第二电极穿过所述层间介质层与所述第八掺杂区电连接；以及第三电极，所述第三电极与所述半导体衬底电连接。
优选地，所述第一掺杂类型为N型和P型之一，所述第二掺杂类型为N型和P型中的另一个。
优选地，所述功率器件为选自金属氧化物半导体场效应晶体管、绝缘栅双极晶体管和二极管中的一种。
根据本发明的另一方面，提供一种功率器件的制造方法，包括：在半导体衬底上形成第一掺杂区；在所述第一掺杂区的第一区域中形成多个第二掺杂区；以及在所述第一掺杂区的第二区域中形成多个第三掺杂区，其中，所述半导体衬底和所述第一掺杂区分别为第一掺杂类型，所述多个第二掺杂区和所述多个第三掺杂区分别为第二掺杂类型，第二掺杂类型与第一掺杂类型相反，所述多个第二掺杂区彼此隔开第一预定间距，与所述第一掺杂区形成第一电荷补偿结构，所述第一电荷补偿结构和所述半导体衬底位于电流通道上，所述多个第三掺杂区彼此隔开第二预定间距，与所述第一掺杂区形成第二电荷补偿结构，所述第二电荷补偿结构用于分散所述功率器件连续的表面电场。
优选地，所述多个第二掺杂区的平均掺杂浓度大于所述多个第三掺杂区的平均掺杂浓度，从而利用所述平均掺杂浓度的差异减小所述元胞区的导通电阻和提高所述元胞区的击穿电压。
优选地，在所述第一掺杂区的第一区域中形成多个第二掺杂区包括经由第一掩模进行第一离子注入，在所述第一掺杂区的第二区域中形成多个第三掺杂区包括经由第二掩模进行第二离子注入。
优选地，第一掩模的开口具有第一横向尺寸，第二掩模的开口具有第二横向尺寸，并且所述第一横向尺寸大于所述第二横向尺寸。
优选地，在所述第一离子注入时采用第一离子注入剂量，在所述第二离子注入时采用第二离子注入剂量，所述第一离子注入剂量和所述第二离子注入剂量的范围为2E12～2E13cm-2。
优选地，所述第一离子注入剂量与所述第二离子注入剂量相同。
优选地，所述第一离子注入剂量比所述第二离子注入剂量高20％或更多。
优选地，在所述第一掺杂区的第一区域中形成多个第二掺杂区包括在第一深槽中填充多个第一外延层，在所述第一掺杂区的第二区域中形成多个第三掺杂区包括在第一深槽中填充多个第二外延层。
优选地，所述第一深槽和所述第二深槽在所述第一掺杂区中沿纵向方向朝着所述半导体衬底延伸，并且横向尺寸减小。
优选地，所述深槽采用蚀刻形成，并且采用不同的蚀刻角度获得横向尺寸减小的形状。
优选地，所述深槽的下部在蚀刻时采用的蚀刻角度为85°～87°，上部在蚀刻时采用的蚀刻角度为88°～89°。
根据本发明实施例的功率器件及其制作方法，在功率器件的元胞区和环区分别形成第一电荷补偿结构和第二电荷补偿结构。由于可以采用相同的工艺同时形成第一电荷补偿结构和第二电荷补偿结构，因此，该实施例的功率器件没有增加工艺复杂度和成本。在元胞区中，由于第一电荷补偿结构包括彼此相邻的P型掺杂区和N型掺杂区，二者的电荷可以相互耗尽，因此可以显著减小功率器件的导通电阻和降低功耗。在环区中，由于第二电荷补偿结构的存在，在元胞边缘区域的的耗尽层得以扩展，有利于缓解元胞区的边缘区域形成的反向电场，从而提高功率器件的击穿电压。
在优选的实施例中，通过在第一电荷补偿结构和第二电荷补偿结构中的P型掺杂区的平均掺杂浓度的差异，同时实现减小所述元胞区的导通电阻和提高所述元胞区的击穿电压。
在优选的实施例中，可以在形成第一电荷补偿结构和第二电荷补偿结构时采用不同的离子注入步骤，获得第一电荷补偿结构和第二电荷补偿结构中P型掺杂区的掺杂浓度差异。或者，采用不同尺寸的窗口，在同一个离子注入步骤中，获得第一电荷补偿结构和第二电荷补偿结构中P型掺杂区的掺杂浓度差异。或者，采用不同的蚀刻角度形成深槽，然后填充外延层，获得第一电荷补偿结构和第二电荷补偿结构中P型掺杂区的掺杂浓度差异。
与现有技术相比，本发明在不增加任何工艺复杂度和成本的基础上，通过调整第一电荷补偿结构和第二电荷补偿结构中的P型掺杂区的掺杂浓度，兼顾提高功率器件的导通电阻和击穿电压的要求。
附图说明
通过以下参照附图对本发明实施例的描述，本发明的上述以及其他目的、特征和优点将更为清楚。
图1和2分别示出根据本发明第一实施例的功率器件的截面图和俯视图。
图3示出根据本发明第一实施例的功率器件中的各个掺杂区的掺杂浓度分布。
图4和5分别示出根据本发明第一实施例的功率器件的导通电阻分布图和击穿电压分布图。
图6a至6h示出根据本发明第二实施例的功率器件制造方法不同阶段的截面图。
图7示出根据本发明第三实施例的功率器件的截面图。
图8示出根据本发明第四实施例的功率器件的截面图。
具体实施方式
以下将参照附图更详细地描述本发明的各种实施例。在各个附图中，相同的元件采用相同或类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。
本发明可以各种形式呈现，以下将描述其中一些示例。
<第一实施例>
图1和2分别示出根据本发明第一实施例的功率器件的截面图和俯视图，其中，图1是图2所示俯视图中沿AA’线获取的截面图。在该实施例中，功率器件100为金属氧化物半导体场效应晶体管(MOSFET)。在下文中，以N型MOSFET为例进行说明，然而，本发明不限于此。
在图1中仅示出环区120的一部分结构。如图1所示，功率器件100包括元胞区110以及围绕元胞区110的环区120。环区120是围绕元胞区110的封闭形状。元胞区110和环区120均包括多个第一掺杂区102和多个P型掺杂区。元胞区110中的第一掺杂区102和P型掺杂区提供源区、漏区、沟道和补偿区，从而形成功率器件导通时的电流通道。环区120中的第一掺杂区102和第三掺杂区121用于分散功率器件边缘的表面电场。
进一步地，参见图1，其中示出元胞区110和环区120的纵向结构。为了简明清楚，图中元胞区110只包含了两个元胞的纵向结构示意图，而实际产品当中，元胞的数量不止于两个，环区110只包含了五个第三掺杂区121，而在实际产品当中，可以少于或者多于这个数量。在功率器件100中，元胞区110和环区120包括公共的半导体衬底101以及位于半导体衬底101上的第一掺杂区102。在该实施例中，半导体衬底101的例如为硅衬底，并且掺杂类型为N++型，第一掺杂区102例如是原位掺杂的外延半导体层，并且掺杂类型为N型。半导体衬底101作为MOSFET的漏区。
在元胞区110中，在第一掺杂区102中形成掺杂类型为P型的多个第二掺杂区111。第一掺杂区102与多个第二掺杂区111的掺杂类型相反，多个第二掺杂区111交替分布于第一掺杂区102中，形成第一电荷补偿结构110a。在环区120中，在第一掺杂区102中形成掺杂类型为P型的多个第三掺杂区121。第一掺杂区102与多个第三掺杂区121的掺杂类型相反，多个第三掺杂区121交替分布于第一掺杂区102中，形成第二电荷补偿结构120a。所述多个第二掺杂区111和多个第三掺杂区121分别具有从顶端至底端减小的掺杂浓度分布，并且每个掺杂区都可以由堆叠的多个外延层组成。
进一步地，在元胞区110中，在多个第二掺杂区111上方形成多个第四掺杂区112，以及在 第四掺杂区112中形成第五掺杂区113。第四掺杂区112和第五掺杂区113例如是通过离子注入形成的掺杂区，并且掺杂类型分别为P型和N+型。第四掺杂区112作为MOSFET的本体阱区，第五掺杂区113作为MOSFET的源区。第四掺杂区112的底部与相应的一个第二掺杂区111接触。优选地，在第四掺杂区112中还可以形成第六掺杂区114。第六掺杂区114例如是通过离子注入形成的掺杂区，并且掺杂类型分别为P+型。第六掺杂区114延伸至第四掺杂区112中，并且与第五掺杂区113邻接。在该优选的实施例中，第六掺杂区114用作本体阱区的引出端。
在第一掺杂区102和第四掺杂区112的表面上，形成包括栅极介质115和栅极导体116的栅极叠层。栅极导体116至少一部分从第一掺杂区102上方横向延伸至第五掺杂区113上方。第四掺杂区112在第一掺杂区102和第五掺杂区113之间、位于栅极导体116下方的部分形成MOSFET的沟道区。
进一步地，在环区120中，在第一掺杂区102中形成第七掺杂区104。所述第七掺杂区104例如是通过离子注入形成的掺杂区，并且掺杂类型为P型。第七掺杂区104横向延伸至第四掺杂区112，形成主结。第七掺杂区104从表面纵向延伸至预定深度，与一部分第三掺杂区121接触，使得一部分第四掺杂区112与一部分第三掺杂区121经由主结相连。进一步地，在第一掺杂区102中形成第八掺杂区122。第八掺杂区122限定MOSFET的周边，并且作为截止环。所述第八掺杂区122例如是通过离子注入形成的掺杂区，并且掺杂类型为P+型。第八掺杂区122可以与第四掺杂区112一起形成，二者的掺杂类型和延伸深度相同。
进一步地，层间介质层105覆盖上述的器件结构。在层间介质层105中形成穿透孔。第一电极118经由穿透孔接触第五掺杂区113，从而提供至源区的电连接。同时，第一电极118还将第五掺杂区113和第六掺杂区114彼此短接。第二电极128经由穿透孔接触第八掺杂区122，从而提供至截止环的电连接。在半导体衬底101的与第一掺杂区102相对的表面上形成第三电极108，从而提供至漏区的电连接。在该实施例中，第一电极118和第三电极108分别作为MOSFET的源极电极和漏极电极。
为了清楚地说明问题，在图1中定义了水平X方向和垂直Y方向。所谓水平X方向是沿着环区120到元胞区110横向延伸的方向。所谓垂直Y方向是沿着半导体衬底101至第五掺杂区113纵向延伸的方向。
在水平X方向上，W1为第二掺杂区111的宽度，S1为彼此相邻的第二掺杂区111之间的间距；W2为第三掺杂区121的宽度，S2为彼此相邻的第三掺杂区121之间的间距，S3为彼此相邻的第三掺杂区121和第二掺杂区111之间的间距。在实际制作过程中，要求满足X方向注入窗口满足以下规则：W1+S1＝n*(W2+S2)，且W1/(W1+S1)＝W2/(W2+S2)，其中n为整数。
在垂直Y方向上，第二掺杂区111和第三掺杂区121的掺杂浓度是非线性的。第二掺杂区111和第三掺杂区121的顶端靠近功率器件的源区，即第五掺杂区113，底端靠近功率器件的漏区，即半导体衬底101。第二掺杂区111和第三掺杂区121分别具有从顶端至底端减小的掺杂浓度分布。
在功率器件100的工作期间，在栅极导体116上施加栅极电压。当栅极电压低于阈值电压时，功率器件处于断开状态，在漏极会施加高电压。随着漏极电压的升高，电荷补偿结构形成耗尽层，从而承载电压。第一电荷补偿结构在第二掺杂区111和第一掺杂区102相互补偿作用下，能够承受比较高的电压。虽然第二掺杂区111和第三掺杂区121的尺寸比例相同，但由于第二电荷补偿结构的第三掺杂区121的尺寸比第二掺杂区111的尺寸小，在后续制造的高温过程中，第二掺杂区111的杂质扩散和第三掺杂区121的扩散情况有差别，造成在相同漏极电极电压的作用下，第三掺杂区121的杂质更加容易被第一掺杂区102的杂质补偿而耗尽，也即在第二电荷补偿结构补偿匹配度的绝对值更加小。一般而言，对于600V的高压功率器件，采用本实施例环区110的耐压比元胞区110的耐压要高60V左右，完全可以满足功率器件可靠性的要求。
虽然在第二电荷补偿结构的上述改进容易实现高耐压，但是这种处理方法同时也减小第一掺杂区102的尺寸。也就是说，如果在元胞区110采用同样的处理方法，电流通道会变窄，导通电阻会明显增加，这不是希望看到的结果。为了进一步在元胞区110中第一电荷补偿结构保持高耐压的情况下，减小导通电阻，第二掺杂区111分成II区域和I区域，其中I区域是靠近漏极附近的区域，II区域是靠近源极附近的区域。在I区域，第二掺杂区111的掺杂浓度低于第一掺杂区102的掺杂浓度；在II区域，第二掺杂区111的掺杂浓度等于第一掺杂区102的掺杂浓度。
具体而言，将第二掺杂区111划分成不同的子区域，在垂直Y方向上，从靠近漏极附近的区域开始，子区域的补偿匹配度从-20％变化到0％；在靠近源极附近的区域，子区域的补偿匹配度保持0％不变。电荷匹配浓度0％，即第二掺杂区111掺杂浓度和第一掺杂区102掺杂浓度相等，在靠近漏极附近的子区域需要故意做成两种掺杂浓度失配。
在功率器件的工作期间，当功率器件的栅极电压高于阈值电压时，功率器件导通，电流从漏极电极经过第一掺杂区102，流向源极电极。当功率器件的栅极电压低于阈值电压时，功率器件关断，漏极电极将会施加高电压。环区120的作用是缓解元胞区110与功率器件的边缘区域的第一掺杂区102之间形成的反向电场，从而承受漏极电压。
在半导体器件中，理想的平面PN结击穿电压仅由外延的浓度和厚度决定。但是实际器件元胞区的边缘区域会出现结终端的效应，即元胞区110和功率器件的边缘附近的第一掺杂区102之间的PN结的耗尽层轮廓是弯曲的，存在PN结的曲率效应。当反向施加电压的时候，PN结曲率 最大的位置出现最强的电场，而提前击穿或者导致PN结的反向泄漏电流增加，降低了耐压和可靠性。
根据本发明实施例的功率器件，采用环区120围绕元胞区110，在环区120中形成第二电荷补偿结构120a。由于第二电荷补偿结构120a中的第三掺杂区121掺杂浓度分布的设计，在施加反向电压的时候，第三掺杂区121和第一掺杂区102的耗尽更加充分，与元胞边缘区域的耗尽层连接，从而有效地延展了元胞区边缘的耗尽层，降低了终端曲率，提高耐压。同时，环区120中的耗尽层内的可动载流子大大减少，形成一个高阻区域，有效的降低了反向漏电流，改善可靠性。
图3示出根据本发明第一实施例的功率器件中的各个掺杂区的掺杂浓度分布。曲线P1是第二掺杂区111从顶端至底端的掺杂浓度分布曲线，曲线P2是第三掺杂区121从顶端至底端的掺杂浓度分布曲线，曲线N是第一掺杂区102从顶端至底端的掺杂浓度分布曲线。与现有技术的功率器件相比，根据本发明实施例的功率器件中，第二掺杂区111和第三掺杂区121的掺杂浓度是非线性的，从顶端至底端减小。第二掺杂区111和第三掺杂区121的平均掺杂浓度低于第一掺杂区102的平均掺杂浓度。进一步地，第三掺杂区121的平均掺杂浓度低于第二掺杂区111的平均掺杂浓度。
图4和5分别示出根据本发明第一实施例的功率器件的导通电阻分布图和击穿电压分布图。
在功率器件的导通状态，图4对比采用现有技术方法和本实施例方法制造的600V功率器件导通电阻分布对比图，其中，采用标记A表示现有技术的功率器件，采用标记B表示根据本发明实施例的功率器件。本实施例制造的功率器件导通电阻低于现有技术，这得益于减小了第二掺杂区111在靠近源极附近的掺杂浓度，降低了结电阻。
在功率器件的关断状态，虽然第一电荷补偿结构的掺杂浓度不能完全匹配，当漏极施加电压时，仍然能够进行电荷补偿，产生耗尽层而获得高耐压。图5对比采用现有技术方法和本实施例方法制造的600V功率器件600V功率器件击穿电压分布图，其中，采用标记A表示现有技术的功率器件，采用标记B表示根据本发明实施例的功率器件。从图中可以看到，本实施例的功率器件击穿电压分布会比现有技术击穿电压分布大一些，主要由于第一电荷补偿结构的电荷补偿匹配度略有差异造成的。即使是耐压相对低的功率器件，由于环区110的第二电荷补偿结构补偿匹配度绝对值小，环区110的耐压仍然高于元胞区110的耐压，确保了功率器件的可靠性。
<第二实施例>
图6a至6h示出根据本发明第二实施例的功率器件制造方法不同阶段的截面图。
在半导体衬底101上外延生长第一外延层1021，如图6a所示。
该实施例中，半导体衬底101的例如为硅衬底，并且掺杂类型为N++型。例如，半导体衬底101的电阻率为0.01～0.03ohms*cm，厚度是600um左右的<100>晶向的单晶硅衬底。第一外延层1021例如是采用减压外延的方法，在温度1050～1150℃下，原位掺杂的外延半导体层，并且掺杂类型为N型。半导体衬底101将作为MOSFET的漏区。
第一外延层1021的厚度和电阻率根据功率器件的不同耐压规格差异很大。第一外延层1021的厚度例如14～24um，电阻率为0.8～3ohms*cm。另外，根据需要，为了提高第一外延层1021的浓度，在第一外延层1021表面进行一次N型杂质的整体注入，通常采用磷作为注入杂质，注入的剂量一般选择在7E11～7E12cm-2。
随后，在第一外延层1021的表面，涂布光刻胶，经过曝光、显影等光刻步骤，形成光刻胶掩模PR1。该光刻胶掩模PR1包括注入窗口的图案，其中在第二掺杂区和第三掺杂区对应的位置上，暴露第一外延层1021的表面。采用光刻胶掩模PR1进行杂质注入，如图6b所示。
为了形成P型的第二掺杂区和第三掺杂区，可以采用硼作为掺杂剂进行离子注入，注入的能量一般选择60～180Kev，剂量一般选择2E12～2E13cm-2。在离子注入之后，通过溶剂溶解或灰化去除光刻胶掩模PR1。
如上文所述，注入窗口满足以下规则：W1+S1＝n*(W2+S2)，且W1/(W1+S1)＝W2/(W2+S2)，其中，W1为第二掺杂区的宽度，S1为彼此相邻的第二掺杂区之间的间距；W2为第三掺杂区的宽度，S2为彼此相邻的第三掺杂区之间的间距，S3为彼此相邻的第三掺杂区和第二掺杂区之间的间距，n为整数。
该离子注入在第二掺杂区的注入窗口位置形成掺杂区1111，在第三掺杂区域的注入窗口位置形成掺杂区1211。掺杂区1111和1211从第一外延层1021向下延伸预定的深度。由于注入窗口的尺寸差异，即使采用相同的注入条件，掺杂区1211的掺杂浓度也会比掺杂区1111的掺杂浓度小10％。
然后，重复图6a和6b所示的步骤，在第一外延层1021上形成第二外延层1022，以及在第二外延层1022中形成掺杂区1112和1212。第二外延层1022的厚度通常是5～8um，电阻率为0.8～3ohms*cm。掺杂区1112和1212从第二外延层1022向下延伸预定的深度。在离子注入步骤中，掺杂区1112的注入窗口与先前形成的掺杂区1111对准且杂质注入剂量相同，掺杂区1212的注入窗口与先前形成的掺杂区1211对准且杂质注入剂量相同。如上所述，由于注入窗口的尺寸差异，即使采用相同的注入条件，掺杂区1212的掺杂浓度也会比掺杂区1112的掺杂浓度小10％。
进一步地，重复图6a和6b所示的步骤，在第二外延层1022上形成第三外延层1023，以及 在第三外延层1023中形成掺杂区1113和1213，如图6c所示。
在上述的多次外延生长和离子注入步骤中，形成多个外延层的堆叠结构，并且所述外延层中的掺杂区对准。根据功率器件不同耐压的要求，一般上述步骤会重复进行4～10次,在本实施例中举例为4次。每一层生长外延的厚度和电阻率均与第二外延层1022相同。
在垂直Y方向上，掺杂区1111至1113的杂质注入剂量是非线性变化的，靠近漏极附近的杂质注入剂量会比靠近源极附近的杂质注入剂量小20％，掺杂区1211至1213的杂质注入剂量是非线性变化的，靠近漏极附近的杂质注入剂量会比靠近源极附近的杂质注入剂量小20％。在每个层面上，环区中的掺杂区的杂质注入剂量比元胞区中的掺杂区的杂质注入剂量小10％。
随后，在第三外延层1023上外延生长第四外延层1024，如图6d所示。第四外延层1024的厚度和电阻率，根据功率器件的参数特性，可以和之前的外延略有不同。例如，第四外延层1024厚度是4～7um，电阻率为1～4ohms*cm。在外延生长之后进行热退火，经过1000～1150℃高温过程，生长一层3000～6000A厚度的氧化硅层1025。
随后，在氧化硅层1025的表面，涂布光刻胶，经过曝光、显影等光刻步骤，形成光刻胶掩模PR2。该光刻胶掩模PR2包括注入窗口的图案，其中在第七掺杂区对应的位置上，暴露氧化硅层1025的表面。采用光刻胶掩模PR2进行杂质注入，从而形成第七掺杂区104，如图6e所示。
在该步骤中，在离子注入之前，可以刻蚀去除表面二氧化硅。然后注入杂质硼。离子注入的能量是40～100KeV，剂量是3E12～3E13cm-2。在离子注入之后，通过溶剂溶解或灰化去除光刻胶掩模PR1。
随后，进行长时间的高温驱入过程。该步骤包括在1100～1200℃温度进行时间约60～300分钟的热处理。
在高温驱入的过程中，外延层1021至1023中的掺杂区1111至1113和1211至1213中的杂质会向四周扩散。在垂直Y方向上，掺杂区1111至1113相互连接形成第二掺杂区111，掺杂区1211至1213相互连接形成第二掺杂区121。进一步地，在高温驱入的过程中，第四外延层1024的表面会生长一层厚度达到1.6～0.8um的氧化硅层105，如图6f所示。
随后，在氧化硅层105的表面，涂布光刻胶，经过曝光、显影等光刻步骤，形成光刻胶掩模。该光刻胶掩模包括蚀刻窗口的图案，其中在元胞区的整个区域以及环区与截止环相对应的位置上，蚀刻窗口暴露第一掺杂区102的表面。采用湿法腐蚀，去除元胞区的整个区域以及环区与截止环上的氧化硅层105。在蚀刻之后，通过溶剂溶解或灰化去除光刻胶掩模。
优选地，热生长一层厚度是200～600A的薄氧化层，作为离子注入的阻挡层。进行一次N型杂质的整体注入，提高元胞区110表面的N型掺杂浓度。通常采用磷作为注入杂质，注入的剂 量一般选择在7E11～7E12cm-2。注入后再经过一次高温过程，通常会选择1100～1150℃的温度，把杂质扩散到表面1～3um的深度。
进一步地，经过表面清洗，选择900～1000℃温度条件下，热生长氧化硅，从而形成栅极介质115。栅极介质115的厚度一般为800～1200A。采用LPCVD的方法进行多晶硅的淀积，淀积多晶硅的厚度是3000～5000A。对多晶硅进行杂质掺杂，杂质掺杂可以采用扩散或者注入的方式，掺杂后的多晶硅，一般方块电阻分布在5～30ohm/cm。
进一步地，涂布光刻胶，经过曝光、显影等光刻步骤，形成光刻胶掩模。该光刻胶掩模包括蚀刻窗口的图案，其中在元胞区的除栅极导体之外的位置上，蚀刻窗口暴露多晶硅的表面。采用湿法腐蚀，去除多晶硅的暴露部分，从而形成栅极导体116，如图6g所示。在蚀刻之后，通过溶剂溶解或灰化去除光刻胶掩模。
随后，经由光刻胶掩模进行离子注入，从而在元胞区110中形成第四掺杂区112，以及在环区120中形成第八掺杂区122。第四掺杂区112作为功率器件100的本体阱区。
根据功率器件阈值的需求，选择本体阱区注入的剂量。一般3V阈值，采用2E13～5E13cm-2的剂量。经过1100℃～1150℃高温驱入，第四掺杂区112达到2～4um的结深，与第二掺杂区111相接触。
随后，经由光刻胶掩模进行离子注入，从而在第四掺杂区112中形成第六掺杂区114。第六掺杂区114用作本体阱区的引出端。该离子注入的剂量例如为1E15～5E15cm-2剂量，采用硼杂质作为掺杂剂。
在形成第六掺杂区114之后，经过900～1000℃温度，30～90分钟的热过程，形成0.5～1.5um结深。第六掺杂区114与第四掺杂区112相连，形成本体阱区的接触。
进一步地，经由光刻胶掩模进行离子注入，从而在第四掺杂区112中形成第五掺杂区113。第五掺杂区113用作功率器件的源区。该离子注入的剂量例如为1E15～5E15cm-2剂量，采用砷杂质作为掺杂剂。第六掺杂区114延伸至第四掺杂区112中，并且与第五掺杂区113邻接。
进一步地，在器件结构的表面形成层间介质层105。该层间介质层105例如是淀积形成的绝缘层或者含有硼酸的硅玻璃。采用光刻胶掩模对层间介质层105进行蚀刻，形成穿透孔。进一步地，沉积金属层填充穿透孔，金属层的厚度例如为3～4.5um。对金属层进行图案化，形成第一电极118和第二电极128。
第一电极118经由穿透孔接触第五掺杂区113，从而提供至源区的电连接。同时，第一电极118还将第五掺杂区113和第六掺杂区114彼此短接。第二电极128经由穿透孔接触第八掺杂区122，从而提供至截止环的电连接。
对半导体衬底101进行减薄，使得半导体衬底101的厚度达到200～300um。类似地，在半导体衬底101的与第一掺杂区102相对的表面上形成第三电极108，从而提供至漏区的电连接。在该实施例中，第一电极118和第三电极108分别作为MOSFET的源极电极和漏极电极。
最终，该制造方法形成的功率器件100的结构如图6h所示。
<第三实施例>
图7示出根据本发明第三实施例的功率器件的截面图。
在该实施例中，功率器件200为金属氧化物半导体场效应晶体管(MOSFET)。在下文中，以N型MOSFET为例进行说明，然而，本发明不限于此。
参见图7，其中示出元胞区110和环区120的纵向结构。为了简明清楚，图中元胞区110只包含了两个元胞的纵向结构示意图，而实际产品当中，元胞的数量不止于两个，环区110只包含了五个第三掺杂区221，而在实际产品当中，可以少于或者多于这个数量。在功率器件200中，元胞区110和环区120包括公共的半导体衬底101以及位于半导体衬底101上的第一掺杂区102。在该实施例中，半导体衬底101的例如为硅衬底，并且掺杂类型为N++型，第一掺杂区102例如是原位掺杂的外延半导体层，并且掺杂类型为N型。半导体衬底101作为MOSFET的漏区。
在元胞区110中，在第一掺杂区102中形成掺杂类型为P型的多个第二掺杂区211。第一掺杂区102与多个第二掺杂区211的掺杂类型相反，多个第二掺杂区211交替分布于第一掺杂区102中，形成第一电荷补偿结构。在环区120中，在第一掺杂区102中形成掺杂类型为P型的多个第三掺杂区221。第一掺杂区102与多个第三掺杂区221的掺杂类型相反，多个第三掺杂区221交替分布于第一掺杂区102中，形成第二电荷补偿结构。所述多个第二掺杂区211和多个第三掺杂区221分别具有从顶端至底端减小的掺杂浓度分布，并且每个掺杂区都可以由堆叠的多个外延层组成。
进一步地，在元胞区110中，在多个第二掺杂区211上方形成多个第四掺杂区112，以及在第四掺杂区112中形成第五掺杂区113。第四掺杂区112和第五掺杂区113例如是通过离子注入形成的掺杂区，并且掺杂类型分别为P型和N+型。第四掺杂区112作为MOSFET的本体阱区，第五掺杂区113作为MOSFET的源区。第四掺杂区112的底部与相应的一个第二掺杂区211接触。优选地，在第四掺杂区112中还可以形成第六掺杂区114。第六掺杂区114例如是通过离子注入形成的掺杂区，并且掺杂类型分别为P+型。第六掺杂区114延伸至第四掺杂区112中，并且与第五掺杂区113邻接。在该优选的实施例中，第六掺杂区114用作本体阱区的引出端。
在第一掺杂区102和第四掺杂区112的表面上，形成包括栅极介质115和栅极导体116的 栅极叠层。栅极导体116从第一掺杂区102横向延伸至第五掺杂区113。栅极导体116的至少一部分位于第四掺杂区112的上方，使得第四掺杂区112在第一掺杂区102和第五掺杂区113之间的部分形成MOSFET的沟道区。
进一步地，在环区120中，在第一掺杂区102中形成第七掺杂区104。所述第七掺杂区104例如是通过离子注入形成的掺杂区，并且掺杂类型为P型。第七掺杂区104横向延伸至第四掺杂区112，形成主结。第七掺杂区104从表面纵向延伸至预定深度，与一部分第三掺杂区221接触，使得一部分第四掺杂区112与一部分第三掺杂区221经由主结相连。进一步地，在第一掺杂区102中形成第八掺杂区122。第八掺杂区122限定MOSFET的周边，并且作为截止环。所述第八掺杂区122例如是通过离子注入形成的掺杂区，并且掺杂类型为P+型。第八掺杂区122可以与第四掺杂区112一起形成，二者的掺杂类型和延伸深度相同。
进一步地，层间介质层105覆盖上述的器件结构。在层间介质层105中形成穿透孔。第一电极118经由穿透孔接触第五掺杂区113，从而提供至源区的电连接。同时，第一电极118还将第五掺杂区113和第六掺杂区114彼此短接。第二电极128经由穿透孔接触第八掺杂区122，从而提供至截止环的电连接。在半导体衬底101的与第一掺杂区102相对的表面上形成第三电极108，从而提供至漏区的电连接。在该实施例中，第一电极118和第三电极108分别作为MOSFET的源极电极和漏极电极。
在该实施例中，第二掺杂区211和第三掺杂区221是同时形成的。与第一实施例不同，采用深槽刻蚀和外延回填技术形成第二掺杂区211和第三掺杂区221，二者的电阻率完全相同。然而，由于深槽形状不同，使得第二掺杂区211和第三掺杂区221的底端的形状不同。
为了清楚地说明问题，在图7中定义了水平X方向和垂直Y方向。所谓水平X方向是沿着环区120到元胞区110横向延伸的方向。所谓垂直Y方向是沿着半导体衬底101至第五掺杂区113纵向延伸的方向。
在水平X方向上，W1为第二掺杂区211的宽度，S1为彼此相邻的第二掺杂区211之间的间距；W2为第三掺杂区221的宽度，S2为彼此相邻的第三掺杂区221之间的间距，S3为彼此相邻的第三掺杂区221和第二掺杂区211之间的间距。在实际制作过程中，要求满足X方向深槽刻蚀窗口满足以下规则：W1+S1＝n*(W2+S2)，且W1/(W1+S1)＝W2/(W2+S2)，其中n为整数。
在垂直Y方向上，第二掺杂区211和第三掺杂区221的掺杂浓度是非线性的。第二掺杂区211和第三掺杂区221的顶端靠近功率器件的源区，即第五掺杂区113，底端靠近功率器件的漏区，即半导体衬底101。第二掺杂区211和第三掺杂区221分别具有从顶端至底端减小的掺杂浓度分布。
第一电荷补偿结构在靠近漏极附近的区域为I区域；第一电荷补偿结构在靠近源极附近的区域为II区域。I区域和II区域中第二掺杂区111内P型外延填充的形貌有差别。在I区域中第二掺杂区211和第一掺杂区102的Y方向交界面相对于水平X轴斜率小；在II区域中第二掺杂区211和第一掺杂区102的Y方向交界面相对于水平X轴斜率大。斜率有差异的原因是，深槽刻蚀的时候，在I区域和II区域的刻蚀角度不同。一般而言，在I区域会采用85°～87°的刻蚀角度，在II区域会采用88°～89°的刻蚀角度。
具体而言，在回填的外延层掺杂浓度一定的情况下，由于斜率角度的原因，在I区域中第一掺杂区102的掺杂浓度高于第二掺杂区111掺杂浓度；II区域中第一掺杂区102掺杂浓度近似等于第二掺杂区111掺杂浓度。在垂直Y方向上，第二掺杂区111掺杂浓度变化呈现非线性的变化，而且其平均掺杂浓度低于第一掺杂区102平均掺杂浓度。
<第四实施例>
图8示出根据本发明第四实施例的功率器件的截面图。在该实施例中，功率器件300为二极管。
参见图8，其中示出元胞区110和环区120的纵向结构。为了简明清楚，图中元胞区110只包含了两个元胞的纵向结构示意图，而实际产品当中，元胞的数量不止于两个，环区110只包含了五个第三掺杂区121，而在实际产品当中，可以少于或者多于这个数量。在功率器件300中，元胞区110和环区120包括公共的半导体衬底101以及位于半导体衬底101上的第一掺杂区102。在该实施例中，半导体衬底101的例如为硅衬底，并且掺杂类型为N++型，第一掺杂区102例如是原位掺杂的外延半导体层，并且掺杂类型为N型。半导体衬底101作为二极管的阴极。
在元胞区110中，在第一掺杂区102中形成掺杂类型为P型的多个第二掺杂区111。第一掺杂区102与多个第二掺杂区111的掺杂类型相反，多个第二掺杂区111交替分布于第一掺杂区102中，形成第一电荷补偿结构。在环区120中，在第一掺杂区102中形成掺杂类型为P型的多个第三掺杂区121。第一掺杂区102与多个第三掺杂区121的掺杂类型相反，多个第三掺杂区121交替分布于第一掺杂区102中，形成第二电荷补偿结构。所述多个第二掺杂区111和多个第三掺杂区121分别具有从顶端至底端减小的掺杂浓度分布，并且每个掺杂区都可以由堆叠的多个外延层组成。
进一步地，在元胞区110中，在多个第二掺杂区111上方形成多个第四掺杂区112，以及在第四掺杂区112中形成第五掺杂区313。第四掺杂区112和第五掺杂区313例如是通过离子注入形成的掺杂区，并且掺杂类型分别为P型和P+型。第四掺杂区112作为二极管的阳极。第四掺杂 区112的底部与相应的一个第二掺杂区111接触。优选地，在第四掺杂区112中还可以形成第五掺杂区313。第五掺杂区313例如是通过离子注入形成的掺杂区，并且掺杂类型分别为P+型。第五掺杂区313延伸至第四掺杂区112。在该优选的实施例中，第五掺杂区313用作阳极的引出端。
进一步地，在环区120中，在第一掺杂区102中形成第七掺杂区104。所述第七掺杂区104例如是通过离子注入形成的掺杂区，并且掺杂类型为P型。第七掺杂区104横向延伸至第四掺杂区112，形成主结。第七掺杂区104从表面纵向延伸至预定深度，与一部分第三掺杂区121接触，使得一部分第四掺杂区112与一部分第三掺杂区121经由主结相连。进一步地，在第一掺杂区102中形成第八掺杂区122。第八掺杂区122限定二极管的周边，并且作为截止环。所述第八掺杂区122例如是通过离子注入形成的掺杂区，并且掺杂类型为P+型。第八掺杂区122可以与第四掺杂区112一起形成，二者的掺杂类型和延伸深度相同。
进一步地，层间介质层105覆盖上述的器件结构。在层间介质层105中形成穿透孔。第一电极118经由穿透孔接触第五掺杂区313，从而提供至阳极的电连接。同时，第一电极118还将第五掺杂区313和第六掺杂区114彼此短接。第二电极128经由穿透孔接触第八掺杂区122，从而提供至截止环的电连接。在半导体衬底101的与第一掺杂区102相对的表面上形成第三电极108，从而提供至阴极的电连接。在该实施例中，第一电极118和第三电极108分别作为二极管的阳极电极和阴极电极。
为了清楚地说明问题，在图8中定义了水平X方向和垂直Y方向。所谓水平X方向是沿着环区120到元胞区110横向延伸的方向。所谓垂直Y方向是沿着半导体衬底101至第五掺杂区313纵向延伸的方向。
在水平X方向上，W1为第二掺杂区111的宽度，S1为彼此相邻的第二掺杂区111之间的间距；W2为第三掺杂区121的宽度，S2为彼此相邻的第三掺杂区121之间的间距，S3为彼此相邻的第三掺杂区121和第二掺杂区111之间的间距。在实际制作过程中，要求满足X方向注入窗口满足以下规则：W1+S1＝n*(W2+S2)，且W1/(W1+S1)＝W2/(W2+S2)，其中n为整数。
在垂直Y方向上，第二掺杂区111和第三掺杂区121的掺杂浓度是非线性的。第二掺杂区111和第三掺杂区121的顶端靠近二极管的阳极，即第五掺杂区313，底端靠近二极管的阴极，即半导体衬底101。第二掺杂区111和第三掺杂区121分别具有从顶端至底端减小的掺杂浓度分布。
根据本发明的上述实施例，功率器件可以是高压功率器件、IGBT功率器件或者二极管。其功率器件结构中包含第一掺杂区和第二掺杂区，且两种掺杂区交替分布。在具体的实施例中，第一掺杂区和第二掺杂区的位置可以相互变换。
依照本发明的实施例如上文所述，这些实施例并没有详尽叙述所有的细节，也不限制该发明 仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本发明的原理和实际应用，从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明的保护范围应当以本发明权利要求所界定的范围为准。

Claims (36)

  1. 一种功率器件，包括：
    半导体衬底；
    位于所述半导体衬底上的第一掺杂区；
    位于所述第一掺杂区的第一区域中的多个第二掺杂区；以及
    位于所述第一掺杂区的第二区域中的多个第三掺杂区，
    其中，所述半导体衬底和所述第一掺杂区分别为第一掺杂类型，
    所述多个第二掺杂区和所述多个第三掺杂区分别为第二掺杂类型，第二掺杂类型与第一掺杂类型相反，
    所述多个第二掺杂区彼此隔开第一预定间距，与所述第一掺杂区形成第一电荷补偿结构，所述第一电荷补偿结构和所述半导体衬底位于电流通道上，
    所述多个第三掺杂区彼此隔开第二预定间距，与所述第一掺杂区形成第二电荷补偿结构，所述第二电荷补偿结构用于分散所述功率器件连续的表面电场。
  2. 根据权利要求1所述的功率器件，其中，所述第一电荷补偿结构位于所述功率器件的元胞区中，所述第二电荷补偿结构位于所述功率器件的环区中，所述环区围绕所述元胞区。
  3. 根据权利要求1所述的功率器件，其中，所述多个第二掺杂区和所述多个第三掺杂区分别在所述第一掺杂区中沿纵向方向朝着所述半导体衬底延伸，并且掺杂浓度非线性减小。
  4. 根据权利要求3所述的功率器件，其中，所述多个第二掺杂区和所述多个第三掺杂区的平均掺杂浓度分别小于所述第一掺杂区的平均掺杂浓度。
  5. 根据权利要求4所述的功率器件，其中，所述多个第二掺杂区的平均掺杂浓度大于所述多个第三掺杂区的平均掺杂浓度，从而利用所述平均掺杂浓度的差异减小所述元胞区的导通电阻和提高所述元胞区的击穿电压。
  6. 根据权利要求5所述的功率器件，其中，所述多个第二掺杂区的平均掺杂浓度比所述多个第三掺杂区的平均掺杂浓度大10％或更多。
  7. 根据权利要求5所述的功率器件，其中，所述多个第二掺杂区分别包括第一子区域和第二子区域，所述第一子区域的平均掺杂浓度小于所述第一掺杂区的掺杂浓度，所述第二子区域的平均掺杂浓度等于所述第一掺杂区的掺杂浓度。
  8. 根据权利要求7所述的功率器件，其中，所述第一子区域的平均掺杂浓度比所述第一掺杂区的平均掺杂浓度小20％或更多。
  9. 根据权利要求5所述的功率器件，其中，所述多个第二掺杂区具有第一横向尺寸，所述多 个第三掺杂区具有第二横向尺寸，并且所述第一横向尺寸大于所述第二横向尺寸。
  10. 根据权利要求9所述的功率器件，其中，所述第一横向尺寸与所述第一预定间距的比值等于所述第二横向尺寸与所述第二预定间距的比值。
  11. 根据权利要求9所述的功率器件，其中，所述第一横向尺寸与所述第一预定间距之和等于所述第二横向尺寸与所述第二预定间距之和的整数倍。
  12. 根据权利要求5所述的功率器件，其中，所述多个第二掺杂区在离子注入时采用第一离子注入剂量，所述多个第三掺杂区在离子注入时采用第二离子注入剂量，所述第一离子注入剂量和所述第二离子注入剂量的范围为2E12～2E13cm-2。
  13. 根据权利要求5所述的功率器件，其中，所述第一离子注入剂量与所述第二离子注入剂量相同。
  14. 根据权利要求5所述的功率器件，其中，所述第一离子注入剂量比所述第二离子注入剂量高20％或更多。
  15. 根据权利要求5所述的功率器件，其中，所述多个第二掺杂区和所述多个第三掺杂区分别形成在深槽中，所述深槽在所述第一掺杂区中沿纵向方向朝着所述半导体衬底延伸，并且横向尺寸减小。
  16. 根据权利要求15所述的功率器件，其中，所述深槽采用蚀刻形成，并且采用不同的蚀刻角度获得横向尺寸减小的形状。
  17. 根据权利要求16所述的功率器件，其中，所述深槽的下部在蚀刻时采用的蚀刻角度为85°～87°，上部在蚀刻时采用的蚀刻角度为88°～89°。
  18. 根据权利要求2所述的功率器件，其中，所述元胞区还包括：
    多个第四掺杂区，分别位于所述多个第二掺杂区上方；以及
    多个第五掺杂区，分别位于所述多个第四掺杂区中。
  19. 根据权利要求18所述的功率器件，其中，所述元胞区还包括：
    多个第六掺杂区，分别位于所述多个第四掺杂区中，并且作为所述多个第四掺杂区的引出端。
  20. 根据权利要求18所述的功率器件，其中，所述元胞区还包括：
    多个栅叠层，分别包括栅极介质和栅极导体，至少一部分位于所述多个第五掺杂区和所述第一掺杂区之间，
    其中，所述多个第四掺杂区和所述多个第五掺杂区分别为第二掺杂类型和第一掺杂类型，
    所述功率器件为MOSFET，所述半导体衬底、所述多个第四掺杂区、所述多个第五掺杂区分别作为所述MOSFET的漏区、阱区和源区，所述多个第四掺杂区位于所述多个第五掺杂区和所述 第一掺杂区之间形成沟道。
  21. 根据权利要求18所述的功率器件，其中，所述多个第四掺杂区和所述多个第五掺杂区分别为第二掺杂类型，
    其中，所述功率器件为二极管，所述多个第四掺杂区、所述半导体衬底分别作为所述二极管的阳极和阴极。
  22. 根据权利要求18所述的功率器件，其中，所述环区还包括：
    第七掺杂区，所述第七掺杂区为第二掺杂类型，所述第七掺杂区位于所述第一掺杂区中；以及
    第八掺杂区，所述第八掺杂区为第二掺杂类型，所述第八掺杂区位于所述第一掺杂区中，并且与所述多个第三掺杂区和所述第七掺杂区隔开，
    其中，所述第七掺杂区横向延伸至所述元胞区中的所述多个第四掺杂区中的至少一个掺杂区，形成主结，并且从所述第一掺杂区的表面从表面纵向延伸至预定深度，与所述多个第三掺杂区中的至少一些掺杂区接触，使得所述多个第三掺杂区中的至少一些掺杂区与所述多个第二掺杂区中的至少一些掺杂区经由所述主结相连接，
    所述第八掺杂区限定所述功率器件的周边且作为截止环。
  23. 根据权利要求22所述的功率器件，还包括：
    层间介质层；
    第一电极，所述第一电极穿过所述层间介质层与所述多个第五掺杂区电连接；
    第二电极，所述第二电极穿过所述层间介质层与所述第八掺杂区电连接；以及
    第三电极，所述第三电极与所述半导体衬底电连接。
  24. 根据权利要求1所述的功率器件，其中，所述第一掺杂类型为N型和P型之一，所述第二掺杂类型为N型和P型中的另一个。
  25. 根据权利要求1所述的功率器件，其中，所述功率器件为选自金属氧化物半导体场效应晶体管、绝缘栅双极晶体管和二极管中的一种。
  26. 一种功率器件的制造方法，包括：
    在半导体衬底上形成第一掺杂区；
    在所述第一掺杂区的第一区域中形成多个第二掺杂区；以及
    在所述第一掺杂区的第二区域中形成多个第三掺杂区，
    其中，所述半导体衬底和所述第一掺杂区分别为第一掺杂类型，
    所述多个第二掺杂区和所述多个第三掺杂区分别为第二掺杂类型，第二掺杂类型与第一掺杂 类型相反，
    所述多个第二掺杂区彼此隔开第一预定间距，与所述第一掺杂区形成第一电荷补偿结构，所述第一电荷补偿结构和所述半导体衬底位于电流通道上，
    所述多个第三掺杂区彼此隔开第二预定间距，与所述第一掺杂区形成第二电荷补偿结构，所述第二电荷补偿结构用于分散所述功率器件连续的表面电场。
  27. 根据权利要求26所述的方法，其中，所述多个第二掺杂区的平均掺杂浓度大于所述多个第三掺杂区的平均掺杂浓度，从而利用所述平均掺杂浓度的差异减小所述元胞区的导通电阻和提高所述元胞区的击穿电压。
  28. 根据权利要求27所述的方法，其中，在所述第一掺杂区的第一区域中形成多个第二掺杂区包括经由第一掩模进行第一离子注入，
    在所述第一掺杂区的第二区域中形成多个第三掺杂区包括经由第二掩模进行第二离子注入。
  29. 根据权利要求28所述的方法，其中，第一掩模的开口具有第一横向尺寸，第二掩模的开口具有第二横向尺寸，并且所述第一横向尺寸大于所述第二横向尺寸。
  30. 根据权利要求28所述的方法，其中，在所述第一离子注入时采用第一离子注入剂量，在所述第二离子注入时采用第二离子注入剂量，所述第一离子注入剂量和所述第二离子注入剂量的范围为2E12～2E13cm-2。
  31. 根据权利要求30所述的方法，其中，所述第一离子注入剂量与所述第二离子注入剂量相同。
  32. 根据权利要求30所述的方法，其中，所述第一离子注入剂量比所述第二离子注入剂量高20％或更多。
  33. 根据权利要求27所述的方法，其中，在所述第一掺杂区的第一区域中形成多个第二掺杂区包括在第一深槽中填充多个第一外延层，
    在所述第一掺杂区的第二区域中形成多个第三掺杂区包括在第一深槽中填充多个第二外延层。
  34. 根据权利要求33所述的方法，其中，所述第一深槽和所述第二深槽在所述第一掺杂区中沿纵向方向朝着所述半导体衬底延伸，并且横向尺寸减小。
  35. 根据权利要求34所述的方法，其中，所述深槽采用蚀刻形成，并且采用不同的蚀刻角度获得横向尺寸减小的形状。
  36. 根据权利要求35所述的方法，其中，所述深槽的下部在蚀刻时采用的蚀刻角度为85°～87°，上部在蚀刻时采用的蚀刻角度为88°～89°。
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