WO2018076677A1

WO2018076677A1 - Method and apparatus for testing integrated circuit, and storage medium

Info

Publication number: WO2018076677A1
Application number: PCT/CN2017/085666
Authority: WO
Inventors: 孙建伟; 杨丽宁; 胡安稳
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2016-10-28
Filing date: 2017-05-24
Publication date: 2018-05-03
Also published as: CN108020769A

Abstract

A method and an apparatus for testing an integrated circuit, and a storage medium. The method for testing an integrated circuit comprises: selecting N nodes from M nodes to be detected in an integrated circuit, M and N being both integers greater than 0 (100); acquiring data of the selected N nodes in real time, and analyzing the data to obtain a test result of the integrated circuit; or detecting data of each selected node by means of a preset detection method to obtain a detection result of the corresponding node, and when the detection result of any one of the nodes is abnormal, controlling to acquire the data of the corresponding node, analyzing the detection result and data of the abnormal node, and determining a fault state of the integrated circuit (102).

Description

Method, device and storage medium for integrated circuit testing

Cross-reference to related applications

The present application is based on a Chinese patent application filed on Jan. 28, 2016, the entire disclosure of which is hereby incorporated by reference.

Technical field

The present invention relates to the field of integrated circuit technology, and in particular, to a method, an apparatus, and a storage medium for testing an integrated circuit.

Background technique

At present, most of the traditional integrated circuit tests are board-level tests. There are two commonly used board-level tests. The first one is to use the Field Programmable Gate Array (FPGA) to perform excitation input from the integrated circuit pins, and then collect The integrated circuit pins are output, and the output results are compared on the host computer to determine whether the use case is passed; the second type: the integrated circuit test instrument is used to test the integrated circuit.

The disadvantage of the first traditional test method is that the integrated circuit has a limited pin and the internal visibility is not high. Once the integrated circuit to be tested does not pass the use case, the use case simulation is performed to determine the cause of the fault of the integrated circuit to be tested, so the fault is located. The cycle is long.

The disadvantage of the second traditional test method is that when testing with integrated circuit instruments, the hardware environment must be built for each test, and the dependency on the test personnel and equipment is high. The staff is not in the station or the equipment is incomplete, which will waste time.

Summary of the invention

In view of this, embodiments of the present invention are expected to provide a method and apparatus for testing an integrated circuit. The storage medium can reduce the simulation coordination and dependence on a large number of test instruments, quickly locate the fault location of the integrated circuit, thereby solving the fault in time and speeding up the commercial progress.

The technical solution of the embodiment of the present invention is implemented as follows:

Embodiments of the present invention provide a method for testing an integrated circuit, including:

Selecting N nodes from the M nodes to be detected; M and N are integers greater than 0;

Collecting data of the selected N nodes in real time, and analyzing the data of the N nodes to obtain test results of the integrated circuit;

Or, the data of each selected node is detected by a preset detection manner, and the detection result of the corresponding node is obtained. When the detection result of any node is abnormal, the corresponding node is determined to be an abnormal node, and a trigger signal is generated to trigger the start. Collecting data of the corresponding node; determining a fault state of the integrated circuit by analyzing the detection result and data of the abnormal node;

Alternatively, the data of the selected N nodes are collected in real time, and the data of each selected node is detected by a preset detection manner, and the detection result of the corresponding node is obtained. When the detection result of any node is abnormal, the corresponding node is determined to be An abnormal node generates a trigger signal to trigger the stop of collecting data of the corresponding node; and determining a fault state of the integrated circuit by analyzing the detection result and the data of the abnormal node.

In the foregoing solution, the preset detection manner includes: power detection, delay detection, task quantity detection, or traffic detection.

In the above solution, when the detection result of any node is abnormal, a trigger signal is generated, including:

When determining the data power abnormality of any one node by power detection, determining that the detection result of the corresponding node is abnormal, generating a power abnormality indication signal;

Or determining, by using the delay detection, that the data delay of any one node is abnormal, determining that the detection result of the corresponding node is abnormal, and generating a delay abnormality indication signal;

Or, when the task quantity detection is determined by the task quantity detection, determining that the detection result of the corresponding node is abnormal, and generating a task quantity abnormality indication signal;

Alternatively, when the traffic detection is abnormal, the detection result of the corresponding node is abnormal, and the traffic abnormality indication signal is generated;

The power abnormality indicating signal, the delay abnormality indicating signal, the task amount abnormality indicating signal, or the flow abnormality indicating signal is determined as a trigger signal.

In the foregoing solution, the starting to collect data of the corresponding node includes: immediately starting to collect data of the corresponding node, or starting to collect data of the corresponding node after a preset delay time;

The stopping the data collection of the corresponding node includes: immediately stopping collecting data of the corresponding node, or stopping collecting data of the corresponding node after a preset delay time.

In the above solution, the method further includes: configuring a data collection mode;

The data collection mode is: collecting valid data of the node, or collecting data of the node according to the working clock of the node; the valid data of the node is: data of the valid flag of the node in the data of the node is 1.

In the above solution, selecting the N nodes from the M nodes to be detected by the integrated circuit includes: selecting N nodes among the M to-be-detected nodes by software configuration.

In the above solution, before the test result of the integrated circuit is obtained by analyzing the data of the N nodes, the method further includes: saving the data of each selected node to the first storage unit;

After triggering to start collecting data of the corresponding node, or triggering to stop collecting data of the corresponding node, the method further includes: saving the data of the abnormal node to the first storage unit.

In the above solution, the method further includes: when the data amount of the selected one of the nodes is greater than the storage limit of the first storage unit, transmitting the data of the corresponding node to the second storage unit in real time through the ping-pong storage;

Or, when the data volume of any abnormal node is greater than the upper storage limit of the first storage unit, The data corresponding to the abnormal node is transferred to the second storage unit in real time through the ping-pong storage; the storage capacity of the second storage unit is greater than the storage capacity of the first storage unit.

An apparatus for testing an integrated circuit according to an embodiment of the present invention includes: a selection module and a processing module; wherein

The selection module is configured to select N nodes from the M nodes to be detected in the integrated circuit; M and N are integers greater than 0;

The processing module is configured to collect data of the selected N nodes in real time, and analyze the data of the N nodes to obtain test results of the integrated circuit;

In the above solution, the processing module is further configured to: when determining, by using power detection, that the data power of any one node is abnormal, determining that the detection result of the corresponding node is abnormal, generating a power abnormality indication signal; or determining that the delay is detected by the delay detection When the data delay of one node is abnormal, it is determined that the detection result of the corresponding node is abnormal, and a delay abnormality indication signal is generated; or, when the task quantity abnormality of any one node is determined by the task quantity detection, it is determined that the detection result of the corresponding node is abnormal. , generating a task amount abnormality indication signal; or, determining any one by flow detection When the data flow of the node is abnormal, determining that the detection result of the corresponding node is abnormal, generating a traffic abnormality indication signal; determining the power abnormality indication signal, the delay abnormality indication signal, the task quantity abnormality indication signal, or the traffic abnormality indication signal as a trigger signal.

In the above solution, the processing module is further configured to start collecting data of the corresponding node immediately, or start collecting data of the corresponding node after a preset delay time;

Alternatively, it is configured to stop collecting data of the corresponding node immediately, or stop collecting data of the corresponding node after a preset delay time.

In the above solution, the device further includes: a first configuration module;

The first configuration module is configured to configure a data collection mode;

In the above solution, the device further includes: a second configuration module, wherein the second configuration module is configured to select N nodes among the M to-be-detected nodes by software configuration.

In the above solution, the device further includes: a first storage unit;

a first storage unit configured to save data of each selected node before analyzing the test result of the integrated circuit by analyzing data of the N nodes;

The first storage unit is further configured to save the data of the abnormal node after triggering to start collecting data of the corresponding node or triggering to stop collecting data of the corresponding node.

In the above solution, the device further includes: a second storage unit;

The second storage unit is configured to save the data of the corresponding node in real time through the ping-pong storage when the data amount of the selected one of the nodes is greater than the storage limit of the first storage unit;

Alternatively, the second storage unit is further configured to: when the data amount of any one of the abnormal nodes is greater than the storage limit of the first storage unit, save the data corresponding to the abnormal node in real time through the ping-pong storage; the second storage unit The storage capacity is greater than the storage capacity of the first storage unit.

The embodiment of the invention further provides a computer storage medium storing a computer program for performing the above method of testing the integrated circuit of the embodiment of the invention.

An apparatus for testing an integrated circuit according to an embodiment of the present invention includes: a processor and a memory configured to store a computer program capable of running on the processor,

The processor is configured to perform the method of testing the integrated circuit of the embodiment of the present invention when the computer program is executed.

In the embodiment of the present invention, N nodes are selected from the M nodes to be detected; M and N are integers greater than 0; the data of the selected N nodes are collected in real time, and the data of the N nodes is analyzed. The test result of the integrated circuit is detected; or, the data of each selected node is detected by a preset detection manner, and the detection result of the corresponding node is obtained, and when the detection result of any one node is abnormal, the corresponding node is determined to be an abnormal node, and Generating a trigger signal to trigger the start of collecting data of the corresponding node; determining the fault state of the integrated circuit by analyzing the detection result and data of the abnormal node; or collecting the data of the selected N nodes in real time, and detecting by using a preset detection manner The data of each selected node obtains the detection result of the corresponding node. When the detection result of any node is abnormal, it is determined that the corresponding node is an abnormal node, and a trigger signal is generated to trigger the stop of collecting data of the corresponding node; The detection result and data of the node determine the fault state of the integrated circuit. In this way, the simulation fit and dependence on a large number of test instruments can be reduced, and the fault location of the integrated circuit can be quickly located.

DRAWINGS

1 is a flow chart of a first embodiment of a method for testing an integrated circuit of the present invention;

2 is a schematic diagram of a delay detection according to an embodiment of the present invention;

3 is a schematic diagram of a task quantity detection according to an embodiment of the present invention;

4 is a schematic diagram of traffic detection in an embodiment of the present invention;

5 is a flow chart of a second embodiment of a method for testing an integrated circuit of the present invention;

6 is a schematic diagram of a first component structure of an apparatus for testing an integrated circuit according to an embodiment of the present invention;

FIG. 7 is a schematic diagram showing a second composition structure of an apparatus for testing an integrated circuit according to an embodiment of the present invention.

detailed description

The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It is to be understood that the specific embodiments described herein are merely illustrative and not restrictive.

First embodiment

1 is a flow chart of a first embodiment of a method for testing an integrated circuit according to the present invention. As shown in FIG. 1, the method includes:

Step 100: Select N nodes from the integrated circuit M nodes to be detected; M and N are integers greater than 0.

In an embodiment, N nodes are selected among the M to-be-detected nodes by software configuration.

Here, the selected N nodes may be that the user selects N nodes that need to be observed according to the current link state. When N is 1, one of the M nodes is selected for single point detection; when N is 2, the data of the two nodes can be simultaneously collected and analyzed, and is usually used to collect input and output data of a certain node. And comparing with the data of the reference node to determine whether the node works normally; when N takes an integer greater than 2, the selected N node data can be simultaneously collected and analyzed.

Step 102: Collect data of the selected N nodes in real time, and analyze the test result of the integrated circuit; or, detect the data of each selected node by using a preset detection manner, and obtain the detection result of the corresponding node, where When the detection result of one node is abnormal, it controls the data of the corresponding node, analyzes the detection result and data of the abnormal node, and determines the fault state of the integrated circuit.

This step can include the following three different implementations:

Method 1: Collect data of selected N nodes in real time, and analyze the number of N nodes According to the test results of the integrated circuit.

Manner 2: detecting the data of each selected node by using a preset detection manner, and obtaining the detection result of the corresponding node. When the detection result of any node is abnormal, determining that the corresponding node is an abnormal node, and generating a trigger signal to trigger Start collecting data of the corresponding node; determine the fault status of the integrated circuit by analyzing the detection result and data of the abnormal node.

Method 3: collecting data of the selected N nodes in real time, detecting the data of each selected node by using a preset detection manner, and obtaining the detection result of the corresponding node, and determining the corresponding node when the detection result of any one node is abnormal It is an abnormal node, and generates a trigger signal to trigger the stop of collecting data of the corresponding node; by analyzing the detection result and data of the abnormal node, determining the fault state of the integrated circuit.

In the above manners 1, 2, and 3, the identification information of the data of the selected N nodes may be configured before the data of the selected N nodes is collected. Correspondingly, the data of the selected N nodes is collected in real time according to the configured identification information.

It should be noted that the identifier information may include at least one of the following: a radio frame number, a frame header signal, and a delay. Here, the radio frame number is used to determine which radio frame period the data of the node is collected. For example, when the radio frame number is 7 and the radio frame period is 10 ms, the 7th period of the radio frame (ie, 60 ms) is determined. The data is collected during the 70 ms period, where the frame header signal is used to indicate the data start position of the selected N nodes. When the radio frame number of the service data is equal to the pre-configured radio frame number, the frame header corresponding to the N nodes arrives, and the delay time of the configuration is reached after the arrival of the frame header, data collection corresponding to the N nodes is performed. When the wireless frame number is configured by the software for data collection, multiple devices can also collect the same piece of data.

In an embodiment, the preset detection manner may include: power detection, delay detection, task quantity detection, or traffic detection.

In this step, when the detection result of any node is abnormal, a trigger signal is generated, including:

When determining the data power abnormality of any one node by power detection, it is determined that the detection result of the corresponding node is abnormal, and a power abnormality indication signal is generated.

Alternatively, when the data delay of any one node is abnormal by the delay detection, it is determined that the detection result of the corresponding node is abnormal, and a delay abnormality indication signal is generated.

Alternatively, when the task quantity detection is determined by the task quantity detection, the detection result of the corresponding node is determined to be abnormal, and the task quantity abnormality indication signal is generated.

Alternatively, when the traffic detection is determined to be abnormal by the traffic detection, the detection result of the corresponding node is determined to be abnormal, and a traffic abnormality indication signal is generated.

In an embodiment, the process of power detection may be: first, calculating the average power and peak power of the data of the node; secondly, if the average power of the data of the node is greater than the average power upper limit value or less than the average power lower limit value, or When the peak power of the node data is greater than the peak power upper limit value or less than the peak power lower limit value, the power abnormality indication signal is pulled high to a high level, and the rising edge of the power abnormality indication signal triggers the node data acquisition. Here, when the power abnormality indication signal becomes a high level signal, a trigger signal is generated.

In actual implementation, when performing power detection on the data of the node, it is necessary to calculate the power of the fixed length node data and obtain at least two sets of power data. Therefore, the power detection mode can be configured by software, including: a power calculation starting point of the node data, a fixed length of the node data, and a power group number of the node data.

In an embodiment, the process of the delay detection may be: performing delay monitoring on the input data of all nodes, and recording the system time corresponding to the task input time of each node, and the system time difference between any two nodes is the two nodes. Delay between two nodes; when the delay between two nodes is greater than the preset delay upper limit or less than the preset delay lower limit, it is considered that there is a delay anomaly between the two nodes. The delay anomaly indication signal is pulled high to a high level, and the delay anomaly indication The rising edge of the signal triggers the data acquisition of the node. Here, the trigger signal is generated when the delay abnormality indication signal becomes a high level signal.

2 is a schematic diagram of delay detection in an embodiment of the present invention. As shown in FIG. 2, time delay monitoring is performed on input data of nodes 1, 2, and 3, and system time A, B, and C corresponding to each node task input time are recorded. . The order of data flowing through the nodes is from node 1 to node 2 to node 3. The delay between node 1 and node 2 is BA. If the delay BA of nodes 1 and 2 is greater than the preset upper limit of the delay, or less than the pre- When the lower limit of the delay is set, a delay abnormality indication signal is generated, and the data collection of the node 1 and the node 2 is triggered and saved.

In an embodiment, the process of the task quantity detection may be: setting a task statistic to each node to perform statistics on the number of tasks completed by each node, if the number of tasks completed by a node in a unit time is greater than the preset number of tasks. If the upper limit value is lower than the preset lower limit of the number of tasks, the node is considered to have task statistics, and the task abnormality indication signal is pulled high to a high level. At this time, the rising edge of the task abnormality indication signal triggers the node. Data acquisition, here, the trigger signal is generated when the task abnormality indication signal becomes a high level signal.

FIG. 3 is a schematic diagram of the task quantity detection according to the embodiment of the present invention. As shown in FIG. 3, after determining the task statistics abnormality of the node 3, it is necessary to further confirm which task causes the data error of the node 3. When the integrated circuit service is processed, the stream processing is generally performed, and the task is continuously sent to the integrated circuit. If the output result is wrong, it is difficult to know which task is caused when the task is issued, and the problem analysis will be difficult. If the task count is set, it can accurately know which task caused the error when the task is processed incorrectly, and then more accurately analyze the cause of the integrated circuit failure. Exemplarily, a task statistic is inserted into each node. When the data of the node 3 is abnormal, the task statistic recorded by the task statistic of the node 3 is 510, then the data abnormality of the task 510 at the node 3 can be obtained. When the specific fault location is located, the data collected by the node 3 when the task 510 is processed may be collected and analyzed. If the node 3 has no fault, the data of the node 2 or the node 1 when processing the task 510 may be collected separately, and the task statistics are collected. And ASIC The Application Specific Integrated Circuit (ASIC) probe is combined to conveniently obtain the internal information of the A/B node at the task value of 510, and analyze whether the fault point is at node 2 or node 1.

In an embodiment, the process of traffic detection may be: monitoring data traffic of all nodes, when the amount of data completed by a node in a unit time is greater than a preset upper limit of the data amount, or less than a preset lower limit of the data amount. When the value is concerned, it is considered that there is a traffic abnormality at this node, and the traffic abnormality indication signal is pulled high to a high level. At this time, the rising edge of the traffic abnormality indication signal triggers the data acquisition of the node, where the traffic abnormality indication signal becomes high. The trigger signal is generated when the signal is flat.

4 is a schematic diagram of traffic detection according to an embodiment of the present invention. As shown in FIG. 4, data traffic detection is performed on a node, that is, data throughput rate per unit time is detected, and traffic is added to each node during integrated circuit testing. Statistics. Exemplarily, when the data throughput rate of the node 1 is greater than the throughput upper limit value or less than the throughput lower limit value, a traffic abnormality indication signal is generated to trigger data collection for the node 1.

It should be noted that, in the foregoing embodiment, when the node performs power detection, delay detection, task quantity detection, or traffic detection, when the node is normal, the corresponding abnormality indication signal is a low level signal.

In actual implementation, the specific detection mode of each node can be configured by software, so that one of the detection modes is selected to detect the selected N nodes. When selecting the detection mode of each node, you can configure the corresponding detection mode by observing the characteristics of the link or according to the information that the user needs to observe.

In actual implementation, the detection method is not limited to the four types disclosed above, and may include other anomaly detection methods of the integrated circuit, and the limitation of the space is not redundant herein.

The collecting of the data of the corresponding node in the foregoing manner 2 may include: immediately starting to collect data of the corresponding node, or starting to collect data of the corresponding node after a preset delay time.

The stopping the data collection of the corresponding node in the foregoing manner 3 may include: immediately stopping collecting data of the corresponding node, or stopping collecting data of the corresponding node after a preset delay time.

The triggering of the triggering signal to stop the data of the collecting node may further include: collecting data of the selected N nodes in real time, and storing the fixed length data of the N nodes. Here, the fixed length data may be data of a length required by the user, and dynamic real-time storage of the fixed length data, that is, when the newly collected node data is saved, the oldest node data is deleted.

In the above mode 2 or 3, when the trigger signal arrives, the user can start or immediately stop collecting the data of the current abnormal node through the flexible configuration of the software configuration, or start collecting or stopping the acquisition after the preset delay time, to avoid External disturbances cause instantaneous anomalies caused by instantaneous fluctuations in the data of the nodes.

In this step, the method further includes: configuring a data collection mode. In an embodiment, the data collection manner configured by the software may be: collecting valid data of the node, or collecting data of the node according to the working clock of the node. Here, when the valid flag bit of the data of the current node is 1, the data of the current node is determined as valid data. The data collected by the node working clock may be: collecting node data when the rising edge of the working clock of the node arrives, including valid data and invalid data of the node.

Before analyzing the data of the N nodes to obtain the test result of the integrated circuit, the method 1 may further include: saving the data of each selected node to the first storage unit.

After the triggering starts to collect the data of the corresponding node, or after the triggering stops the data collection of the corresponding node, the method may further include: saving the data of the abnormal node to the first storage unit; and saving the detection result of the abnormal node to the Second storage unit.

In actual implementation, when the data volume of any one of the selected nodes is greater than the storage limit of the first storage unit, the data of the corresponding node is transmitted to the second storage unit in real time through the ping-pong storage; or the data volume of any abnormal node When the upper limit value is greater than the first storage unit, the data corresponding to the abnormal node is transferred to the second storage unit in real time through the ping-pong storage; the storage capacity of the second storage unit is greater than the storage capacity of the first storage unit.

In an embodiment, the user reads the data of the node in the second storage unit, analyzes the data of the node through software, and passes the analysis result through a system on a chip (SOC). The bus is reported to the software for analyzing the fault status of the integrated circuit and serves as a reference for the user to select N nodes. In actual implementation, the data analysis of the node may include at least one of the following: data comparison, spectrum analysis, timing detection, and the like.

Exemplarily, the process of data comparison may be: comparing the data of the node with a preset data model, if the data of the node matches the data model, indicating that all nodes before the node in the integrated circuit are normal; if not, if not , indicating that the node or at least one node before the node has failed.

The process of spectrum presentation can be: using MATLAB tool to perform fast Fourier transform (FFT) on the node data to obtain the spectrum of the node data, and analyze the node fault state by observing the spectral characteristics of the node data.

The process of timing detection may be: when timing detection of data of a node, the input data of the node may be detected, that is, by detecting whether the timing of the data of the previous node of the node is correct, the node may be first used by the method. Is the input data correct?

In actual implementation, the detection of timing may include: timing relationship detection and frame format detection. Exemplarily, when the timing relationship of the node 2 is detected, when the timing relationship of the data of the node 1 of the node 2, that is, the node 1 does not match the preset timing relationship, corresponding alarm information is generated and reported through the SOC bus for reporting. Determine the fault condition of the integrated circuit. When the frame format of the node 2 is detected, when the frame format of the data of the node 1 does not match the preset frame format, corresponding alarm information is generated and reported through the SOC bus, so as to determine the fault state of the integrated circuit.

Through the above data analysis of the node, combined with the detection result of the node, it can be used to determine the fault state of the integrated circuit, or as the basis for selecting N nodes in the next integrated circuit detection.

In the embodiment of the present invention, N nodes are selected from the M nodes to be detected; M and N are integers greater than 0; the data of the selected N nodes are collected in real time, and the data of the N nodes is analyzed. The test result of the integrated circuit is obtained; or, the data of each selected node is detected by a preset detection manner, and the detection result of the corresponding node is obtained, and the detection is performed at any node. When the measurement result is abnormal, it is determined that the corresponding node is an abnormal node, and a trigger signal is generated to trigger the acquisition of the data of the corresponding node; the fault state of the integrated circuit is determined by analyzing the detection result and the data of the abnormal node; or, the real-time acquisition is selected. The data of the N nodes detects the data of each selected node by a preset detection manner, and obtains the detection result of the corresponding node. When the detection result of any node is abnormal, it is determined that the corresponding node is an abnormal node, and a trigger is generated. The signal is used to trigger the acquisition of the data of the corresponding node; the fault state of the integrated circuit is determined by analyzing the detection result and the data of the abnormal node. In this way, the simulation fit and dependence on a large number of test instruments can be reduced, and the fault location of the integrated circuit can be quickly located.

Compared with the prior art, the method for testing an integrated circuit provided by the embodiment of the present invention has the following advantages: first, strong versatility, and can be used for testing all ASICs, not limited to chip scale, service function, etc. Second, flexible, flexible configuration of different detection methods and different data collection methods; third, simple operation, only need simple software configuration to achieve different detection work, no need to build integrated circuit external test The hardware platform saves the working time of each test environment; fourth, supports online testing, that is, it can be tested under the normal working condition of the integrated circuit, and does not need to switch the integrated circuit to the test mode; fifth, the internal circuit of the integrated circuit is improved. Visibility reduces the dependence on external expensive test instruments during testing.

Second embodiment

In order to further embodies the purpose of the present invention, based on the first embodiment of the present invention, one node is selected from the M nodes to be detected as an example for further exemplification.

5 is a flow chart of a second embodiment of a method for testing an integrated circuit of the present invention, the method comprising:

Step 500: Suspend the first storage unit and record the working state of the current first storage unit.

In actual implementation, the system needs to configure the first memory unit integrated circuit test. Since the first storage unit may perform other business operations before being occupied, it is necessary to record the first storage unit before the occupation of the service data node and the working clock before using the first storage unit, so as to be in the set After the circuit test is completed, the working state of the first storage unit is restored.

It should be noted that if the integrated circuit is tested with a storage unit dedicated to integrated circuit detection, this step may be omitted and step 501 is directly executed.

Step 501: Configure the first storage unit to be an integrated circuit test mode.

In actual implementation, the counting logic of the first storage unit may be reset, and the working clock frequency of the first storage unit is switched to the operating clock frequency of the integrated circuit, and after the configuration is completed, the logic reset signal is released.

Step 502: Select one node from the integrated circuit M nodes to be detected.

In one embodiment, the method of selecting one node from the integrated circuit M nodes to be detected is to configure the selected one node by software. The user can select the node concerned to detect based on the current link status, alarm information, and other information.

Step 503: Configure a corresponding detection mode for the selected one node.

In this step, the detection mode of the node can be configured as: power detection, delay detection, task quantity detection, or traffic detection.

In an embodiment, the detection mode of each node may be configured by software, so that one of the detection modes is selected to detect the selected N nodes. Select the detection mode of each node, and you can configure the corresponding detection mode by observing the characteristics of the link or according to the information that the user needs to observe.

Step 504: Detect the data of the node by using the configured detection mode.

In this step, the detection of the node is started according to the configured detection mode, and the detection result is saved to the second storage unit through the SOC bus for analyzing the state of the integrated circuit. The second storage unit may be a storage area specially requested by the user for the integrated circuit test, and configured to store the data of the node and the detection result when the collected node data amount is large.

Exemplarily, the detection mode of the node 1 is configured as power detection, and the data of the node 1 is subjected to power calculation, and the power calculation may include average power calculation and peak power detection.

Step 505: Determine whether the detection result is abnormal. If yes, generate a trigger signal and perform step 506; if no, return to step 504.

Exemplarily, when the node 1 is working normally, the power abnormality indication signal is low level, and when abnormal, the signal is pulled high. Determining whether the average power of the node 1 is greater than the average power upper limit value or less than the average power lower limit value, or whether the peak power of the node 1 is greater than the peak power upper limit value or less than the peak power lower limit value, and if so, determining the detection of the node 1 The result is abnormal. The power abnormality indication signal of node 1 is pulled high to a high level to generate a power abnormality indication signal. At this time, the rising edge of the power abnormality indication signal triggers the data of the collecting node 1; if not, the power abnormality indicating signal Low level, ie no trigger signal is generated.

Step 506: Trigger data of the collection node.

In the actual implementation, when the data of the abnormal node is collected, the collected node data is first saved to the first storage unit of the system configuration. When the capacity of the first storage unit configured by the system cannot satisfy the storage of the node data, the data in the storage space may be saved to the second storage unit through the SOC bus for analyzing the fault state of the integrated circuit. .

It should be noted that, in the data collection of a single node, if the data volume of the node to be collected is greater than the storage limit of the first storage unit, the system may perform the collected node data by using two preset storage subunits. The ping pong is stored and transferred to the second storage unit in real time through the SOC bus.

In another implementation manner, data collection may also be performed through software configuration, that is, step 503 to step 505 are skipped, and the data of the selected one node is directly collected and saved in real time, and the data of the node is analyzed to obtain integration. Test results of the circuit. Data acquisition for any node can be achieved.

In another embodiment, the data of the selected one node is collected in real time, and the data of the corresponding node is stopped by the trigger signal. It can realize the data before the abnormality of the acquisition node.

Step 507: The user reads the node data in the storage unit for data analysis.

In this step, the user can read the node data from the first storage unit or the second storage unit, and then perform node data comparison, spectrum presentation, timing detection, etc., and the analysis result is used to determine the fault state of the integrated circuit, or as a lower The basis for selecting N nodes when detecting an integrated circuit.

Step 508: Restore the working state of the occupied first storage unit.

In actual implementation, after completing the test of the integrated circuit, the first storage unit configured by the system needs to perform a logical reset of the data, so that the state of the first storage unit is restored to the pre-occupied service data node and the working clock. After the recovery is completed, the acquisition logic reset signal is released.

It should be noted that if the integrated circuit is tested with a memory unit dedicated to integrated circuit detection, this step is omitted.

Third embodiment

FIG. 6 is a schematic diagram of a first component structure of an apparatus for testing an integrated circuit according to an embodiment of the present invention, where the apparatus includes: a selection module 600, and a processing module 601;

The selection module 600 is configured to select N nodes from the integrated circuit M nodes to be detected; M and N are integers greater than 0.

The processing module 601 is configured to collect data of the selected N nodes in real time, and analyze the data of the N nodes to obtain the test result of the integrated circuit.

Or, the data of each selected node is detected by a preset detection manner, and the detection result of the corresponding node is obtained. When the detection result of any node is abnormal, the corresponding node is determined to be an abnormal node, and a trigger signal is generated to trigger the start. Collecting data of the corresponding node; determining the fault state of the integrated circuit by analyzing the detection result and the data of the abnormal node;

Alternatively, the data of the selected N nodes are collected in real time, and the data of each selected node is detected by a preset detection manner, and the detection result of the corresponding node is obtained. When the detection result of any node is abnormal, the corresponding node is determined to be An abnormal node, and generate a trigger signal to trigger the stop of collecting data of the corresponding node; determine the integration by analyzing the detection result and data of the abnormal node The fault state of the circuit.

In an embodiment, the preset detection manner includes: power detection, delay detection, task quantity detection, or traffic detection.

The processing module 601 is further configured to: when determining, by using the power detection, that the data power of any one node is abnormal, determining that the detection result of the corresponding node is abnormal, generating a power abnormality indication signal; or, when determining the data of any one node by using the delay detection When the abnormality is delayed, it is determined that the detection result of the corresponding node is abnormal, and a delay abnormality indication signal is generated; or, when the task quantity abnormality of any one node is determined by the task quantity detection, it is determined that the detection result of the corresponding node is abnormal, and the generated task quantity is abnormal. Or indicating the data flow abnormality of any one node by the flow detection, determining that the detection result of the corresponding node is abnormal, generating a traffic abnormality indication signal; and setting the power abnormality indication signal, the delay abnormality indication signal, and the task quantity abnormality indication The signal, or flow abnormality indication signal is determined to be a trigger signal.

The processing module 601 is further configured to start collecting data of the corresponding node immediately, or start collecting data of the corresponding node after a preset delay time; or configured to immediately stop collecting data of the corresponding node, or preset delay After the time, the data of the corresponding node is stopped.

In an embodiment, the apparatus of the embodiment of the present invention may further include: a first configuration module configured to configure a data collection manner.

In an embodiment, the apparatus of the embodiment of the present invention may further include: a second configuration module configured to select N nodes among the M to-be-detected nodes by software configuration.

In an embodiment, the apparatus of the embodiment of the present invention may further include: a first storage unit;

The first storage unit is further configured to start collecting data of the corresponding node at the trigger, or trigger the stop After collecting the data of the corresponding node, the data of the abnormal node is saved.

The device further includes: a second storage unit;

In a practical application, the selection module 600, the processing module 601, the first configuration module, the second configuration module, the first storage unit, and the second storage unit may all be configured by a central processing unit (CPU) located in the terminal device. Implemented by a Micro Processor Unit (MPU), a Digital Signal Processor (DSP), or a Field Programmable Gate Array.

Fourth embodiment

FIG. 7 is a schematic diagram of a second component structure of an apparatus for testing an integrated circuit according to an embodiment of the present invention. The apparatus may include: a node selection module, a power detection module, a detection module, and an acquisition module; and the acquisition module further includes: a writing unit and a storage unit.

The node selection module is configured to select N nodes from the integrated circuit M nodes to be detected; M and N are integers greater than 0.

In FIG. 7, the information that each node passes to the node selection module may be: a data signal of the node itself, and a flag signal, which is used to mark the valid data of the node.

The power detection module can be configured to perform power detection on the selected N nodes. When the power detection result is abnormal, generate a trigger signal to control the writing unit of the acquisition module, and collect data of the abnormal node. The detection result is saved to the external storage unit through the SOC bus, and the analysis for the fault state of the integrated circuit is reported.

In actual implementation, when performing power detection on the data of the node, it is necessary to calculate a fixed length. The power of the node data, and at least two sets of power data. Therefore, the power detection mode can be configured by software, including: a power calculation starting point of the node data, a fixed length of the node data, and a power group number of the node data.

The detecting module is configured to perform delay detection, task quantity detection, flow detection, or other detection on the selected N nodes. When the detection result is abnormal, the trigger signal is generated to control the acquisition module to collect the data of the abnormal node; and the detection result is saved to the external storage unit through the SOC bus, and uploaded to the software for analysis of the fault state of the integrated circuit.

In an embodiment, the specific detection mode of the detection module may be configured by software, so that one of the detection modes is selected to detect the selected N nodes.

The acquisition module may include: a writing unit and a storage unit, wherein

Write unit, configured to collect data from the node.

In actual implementation, the data of the start collecting node may be controlled by the trigger signal, or the data of the collecting node may be stopped.

A storage unit configured to save data of the collected nodes.

In the actual implementation, when the data of the abnormal node is collected, the collected node data is first saved to the storage unit inside the device. If the data volume of the node to be collected is greater than the storage unit storage upper limit value of the device, The collected node data is ping-pong stored by two storage sub-units preset in the device, and is transmitted to an external storage unit in real time through the SOC bus.

An embodiment of the present invention further provides an apparatus for testing an integrated circuit, comprising: a processor and a memory for storing a computer program executable on the processor; wherein

In the embodiment of the present invention, if the method for testing the integrated circuit described above is implemented in the form of a software function module, and is sold or used as a stand-alone product, it may also be stored in a computer readable form. Take the storage medium. Based on such understanding, the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions. A computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention. The foregoing storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disk. Thus, embodiments of the invention are not limited to any specific combination of hardware and software.

Correspondingly, an embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores a computer program, and the computer program is used to execute the method for testing the integrated circuit of the embodiment of the present invention.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the computer is readable and stored The instructions in the reservoir produce an article of manufacture comprising an instruction device that implements the functions specified in one or more blocks of the flow or in a flow or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

Industrial applicability

In the embodiment of the present invention, N nodes are selected from the M nodes to be detected; the M and the N are integers greater than 0; the data of the selected N nodes are collected in real time, and the data of the N nodes is analyzed to obtain the integration. The test result of the circuit; or, the data of each selected node is detected by a preset detection manner, and the detection result of the corresponding node is obtained. When the detection result of any node is abnormal, it is determined that the corresponding node is an abnormal node, and a trigger is generated. The signal is used to trigger the acquisition of the data of the corresponding node; the fault state of the integrated circuit is determined by analyzing the detection result and the data of the abnormal node; or the data of the selected N nodes is collected in real time, and each of the detected data is detected by a preset detection mode. The data of the selected node is obtained, and the detection result of the corresponding node is obtained. When the detection result of any node is abnormal, it is determined that the corresponding node is an abnormal node, and a trigger signal is generated to trigger the stop of collecting data of the corresponding node; Test results and data to determine the fault status of the integrated circuit. In this way, the simulation fit and dependence on a large number of test instruments can be reduced, and the fault location of the integrated circuit can be quickly located.

Claims

A method of integrated circuit testing, the method comprising:

Selecting N nodes from the M nodes to be detected; M and N are integers greater than 0;

Collecting data of the selected N nodes in real time, and analyzing the data of the N nodes to obtain test results of the integrated circuit;

Or, the data of each selected node is detected by a preset detection manner, and the detection result of the corresponding node is obtained. When the detection result of any node is abnormal, the corresponding node is determined to be an abnormal node, and a trigger signal is generated to trigger the start. Collecting data of the corresponding node; determining a fault state of the integrated circuit by analyzing the detection result and data of the abnormal node;

Alternatively, the data of the selected N nodes are collected in real time, and the data of each selected node is detected by a preset detection manner, and the detection result of the corresponding node is obtained. When the detection result of any node is abnormal, the corresponding node is determined to be An abnormal node generates a trigger signal to trigger the stop of collecting data of the corresponding node; and determining a fault state of the integrated circuit by analyzing the detection result and the data of the abnormal node.
The method according to claim 1, wherein the preset detection manner comprises: power detection, delay detection, task amount detection, or traffic detection.
The method according to claim 2, wherein when the detection result of any one of the nodes is abnormal, the trigger signal is generated, including:

When determining the data power abnormality of any one node by power detection, determining that the detection result of the corresponding node is abnormal, generating a power abnormality indication signal;

Or determining, by using the delay detection, that the data delay of any one node is abnormal, determining that the detection result of the corresponding node is abnormal, and generating a delay abnormality indication signal;

Or, when the task quantity detection is determined by the task quantity detection, determining that the detection result of the corresponding node is abnormal, and generating a task quantity abnormality indication signal;

Alternatively, when the traffic detection is abnormal, the detection result of the corresponding node is abnormal, and the traffic abnormality indication signal is generated;

The power abnormality indicating signal, the delay abnormality indicating signal, the task amount abnormality indicating signal, or the flow abnormality indicating signal is determined as a trigger signal.
The method according to claim 1, wherein the starting to collect data of the corresponding node comprises: immediately starting to collect data of the corresponding node, or starting to collect data of the corresponding node after a preset delay time;

The stopping the data collection of the corresponding node includes: immediately stopping collecting data of the corresponding node, or stopping collecting data of the corresponding node after a preset delay time.
The method of claim 1, wherein the method further comprises: configuring a data collection mode;

The data collection mode is: collecting valid data of the node, or collecting data of the node according to the working clock of the node; the valid data of the node is: data of the valid flag of the node in the data of the node is 1.
The method of claim 1, wherein the selecting N nodes from the integrated circuit M to-be-detected nodes comprises: selecting N nodes among the M to-be-detected nodes by software configuration.
The method according to claim 1, wherein, before analyzing the test results of said integrated circuit by analyzing data of said N nodes, said method further comprises: saving data of each selected node to First storage unit;

After triggering to start collecting data of the corresponding node, or triggering to stop collecting data of the corresponding node, the method further includes: saving the data of the abnormal node to the first storage unit.
The method according to claim 7, wherein the method further comprises: when the data amount of the selected one of the nodes is greater than the storage limit of the first storage unit, transmitting the data of the corresponding node to the data in real time through the ping-pong storage to Second storage unit;

Alternatively, when the data volume of any one of the abnormal nodes is greater than the storage limit of the first storage unit, the data corresponding to the abnormal node is transmitted to the second storage unit in real time through the ping-pong storage; the storage capacity of the second storage unit Greater than the storage capacity of the first storage unit.
An apparatus for testing an integrated circuit, the apparatus comprising: a selection module, a processing module; wherein

Selecting a module, configured to select N nodes from the integrated circuit M nodes to be detected; M and N are integers greater than 0;

The processing module is configured to collect data of the selected N nodes in real time, and analyze the data of the N nodes to obtain test results of the integrated circuit;

Or, the data of each selected node is detected by a preset detection manner, and the detection result of the corresponding node is obtained. When the detection result of any node is abnormal, the corresponding node is determined to be an abnormal node, and a trigger signal is generated to trigger the start. Collecting data of the corresponding node; determining a fault state of the integrated circuit by analyzing the detection result and data of the abnormal node;

Alternatively, the data of the selected N nodes are collected in real time, and the data of each selected node is detected by a preset detection manner, and the detection result of the corresponding node is obtained. When the detection result of any node is abnormal, the corresponding node is determined to be An abnormal node generates a trigger signal to trigger the stop of collecting data of the corresponding node; and determining a fault state of the integrated circuit by analyzing the detection result and the data of the abnormal node.
The apparatus according to claim 9, wherein the preset detection manner comprises: power detection, delay detection, task amount detection, or traffic detection.
The apparatus according to claim 10, wherein the processing module is further configured to: when determining a data power abnormality of any one node by power detection, determining that the detection result of the corresponding node is abnormal, generating a power abnormality indication signal; or When determining the data delay abnormality of any one node by the delay detection, determining that the detection result of the corresponding node is abnormal, generating a delay abnormality indication signal; or, when determining the task amount of any one node by the task quantity detection, Determining that the detection result of the corresponding node is abnormal, and generating a task quantity abnormality indication signal; or determining that the data flow abnormality of any one node is abnormal by the flow detection, determining that the detection result of the corresponding node is abnormal, and generating a traffic abnormality indication signal; The power abnormality indicating signal, the time delay abnormality indicating signal, the task amount abnormality indicating signal, or the flow abnormality indicating signal is determined as a trigger signal.
The device according to claim 9, wherein the processing module is further configured to start collecting data of the corresponding node immediately, or start collecting data of the corresponding node after a preset delay time;

Alternatively, it is configured to stop collecting data of the corresponding node immediately, or stop collecting data of the corresponding node after a preset delay time.
The device according to claim 9, wherein the device further comprises: a first configuration module;

The first configuration module is configured to configure a data collection mode;

The data collection mode is: collecting valid data of the node, or collecting data of the node according to the working clock of the node; the valid data of the node is: data of the valid flag of the node in the data of the node is 1.
The apparatus of claim 9, wherein the apparatus further comprises: a second configuration module; the second configuration module configured to select N nodes among the M to-be-detected nodes by software configuration.
The apparatus of claim 9, wherein the apparatus further comprises: a first storage unit;

a first storage unit configured to save data of each selected node before analyzing the test result of the integrated circuit by analyzing data of the N nodes;

The first storage unit is further configured to save the data of the abnormal node after triggering to start collecting data of the corresponding node or triggering to stop collecting data of the corresponding node.
The apparatus of claim 15 wherein said apparatus further comprises: second storage unit;

The second storage unit is configured to save the data of the corresponding node in real time through the ping-pong storage when the data amount of the selected one of the nodes is greater than the storage limit of the first storage unit;

Alternatively, the second storage unit is further configured to: when the data amount of any one of the abnormal nodes is greater than the storage limit of the first storage unit, save the data corresponding to the abnormal node in real time through the ping-pong storage; the second storage unit The storage capacity is greater than the storage capacity of the first storage unit.
A computer storage medium having stored therein computer executable instructions for performing the method of integrated circuit testing according to any one of claims 1 to 8.
An apparatus for testing integrated circuits, comprising: a processor and a memory for storing a computer program executable on the processor; wherein the processor is configured to execute any one of claims 1 to 8 when the computer program is executed The method of integrated circuit testing described in the item.