WO2018059361A1

WO2018059361A1 - Power down protection method for storage system, storage controller, and electronic device

Info

Publication number: WO2018059361A1
Application number: PCT/CN2017/103249
Authority: WO
Inventors: 许璐
Original assignee: 华为技术有限公司
Priority date: 2016-09-29
Filing date: 2017-09-25
Publication date: 2018-04-05
Also published as: CN106502928A; CN106502928B

Abstract

A power down protection method for a storage system, a storage controller and an electronic device, relating to the technical field of communications, capable of solving the problem that a storage system needs to consume a large amount of time to perform mapping relationship recovery. The method comprises: when the last power down of a CPU was an abnormal power down, a storage controller determining index information about a second-level and third-level mapping table level by level according to index information about a first-level mapping table, and reading mapping relationships of all data in a log buffer area and mapping relationships of all data in a log area; sending the acquired mapping relationships to the CPU; and when at least one piece of data has a mapping relationship in the log buffer area or a mapping relationship in the log area different from a mapping relationship in the third-level mapping table, the storage controller replacing the mapping relationship in the third-level mapping table, and updating the index information about the second-level and first-level mapping tables level by level, and saving a mapping relationship in the updated second-level mapping table that has changed before and after the update to a DRAM. The method is applicable to a storage system.

Description

Storage system power failure protection method, storage controller and electronic device

This application claims the priority of the Chinese Patent Application filed on September 29, 2016, the Chinese Patent Office, the application number is 201610872062.0, and the invention name is "a storage system power failure protection method, storage controller and electronic equipment". The content is incorporated herein by reference.

Technical field

The present invention relates to the field of communications technologies, and in particular, to a storage system power failure protection method, a storage controller, and an electronic device.

Background technique

With the popularity of flash memory technology, flash (Chinese: flash)-based storage devices (such as SSD, Solid State Drive, Chinese: SSD) may be caused by abnormal power failure during development, testing, and user use. The flash state is abnormal, causing data to be corrupted, eventually causing the device to fail to boot.

At present, in order to realize the power-down protection when the terminal generates abnormal power failure, when writing data, the metadata storage module is usually in the OOB (English: Out Of Band) area of each page of each block. Or a summary of the information of the data recorded in the OOB area of the last page, wherein the information digest includes the mapping relationship between the logical address and the physical address of all pages on the block; since the data in the SSD belonging to the non-volatile medium is rewritten When the original data is not rewritten, the rewritten content is stored in other locations in the SSD, and when the mapping relationship needs to be stored in the SSD reaches a certain number, the content can be written to the SSD. Therefore, when a power failure occurs, a new mapping relationship has been generated, but considering that the SSD is stored in units of data blocks, this may cause new mapping relationships to be written to the SSD, and new ones. The mapping relationship cannot be stored in the SSD in time; when the storage system is powered on, the storage array scanning module scans the OOB area of each page for the entire SSD, or scans the last page of the O. The OB area is used to obtain the mapping relationship of all the data pages, and then determines the latest physical address corresponding to the same logical address according to the degree of the old and new mappings of all the obtained data pages, thereby determining the latest mapping relationship to implement power-down protection. .

However, due to the large capacity of the SSD, it takes a lot of time to perform a full scan of the SSD. Therefore, the above method is used to implement power-down protection. For a large-capacity SSD, the storage system requires a large amount of time to restore the mapping relationship.

Summary of the invention

The present invention provides a storage system power failure protection method, a storage controller, and an electronic device, which can solve the problem that the storage system needs a large amount of time to restore the mapping relationship.

To achieve the above objective, the embodiment of the present invention adopts the following technical solutions:

In one aspect, the present invention provides a storage system power failure protection method, the method is used in an electronic device, and the electronic device includes: a central processing unit (English: abbreviated as: CPU), a storage controller, a flash, and a high speed non-easy Loss memory and dynamic random access memory (English: abbreviated as DRAM), high-speed non-volatile memory holds a first-level mapping table and a log buffer area, and a secondary mapping table, a three-level mapping table, and a log are stored in the flash. District, where

The log buffer is used to save the mapping relationship between the data written by the storage controller and the data in the log buffer area when the CPU writes the data mapping relationship to the DRAM during normal operation of the electronic device.

The log area is used to save the mapping relationship between the data read by the storage controller from the log buffer area after the storage space in the log buffer area reaches the first threshold.

The index information of the three-level mapping table is a data mapping relationship. When the data in the log area reaches the second threshold, the three-level mapping table is refreshed and the mapping relationship of the data in the log area is saved.

The index information of the primary mapping table is a mapping relationship of the secondary mapping table;

The index information of the secondary mapping table is a mapping relationship of the three-level mapping table;

The mapping relationship is a correspondence between a logical address and a physical address;

The method includes:

After the power-off of the CPU is abnormally powered off, the storage controller determines the physical address of the secondary mapping table according to the index information of the primary mapping table, and finds the secondary mapping table according to the physical address of the secondary mapping table, and accesses the second mapping table. The index information of the level mapping table is used to determine the physical address of the three-level mapping table, and then the three-level mapping table is found according to the physical address of the three-level mapping table, and the index information of the three-level mapping table is determined;

The storage controller reads the mapping relationship of all the data in the log buffer area, and the mapping relationship of all the data in the log area;

The storage controller sends the index information of the three-level mapping table, the mapping relationship of all the data in the log buffer area, and the mapping relationship of all the data in the log area to the CPU;

When the storage controller determines, according to the index information of the three-level mapping table and the mapping relationship of all the data in the log buffer area, the mapping relationship between the at least one data in the log buffer area or the mapping relationship in the log area and the third-level mapping table are determined by the CPU. When the mapping relationship in the log is inconsistent, the mapping relationship in the log buffer area or the mapping relationship in the log area is used to replace the mapping relationship in the third-level mapping table, wherein, in the replacement, at least one data is preferentially used. Replace the mapping relationship of the log buffer area;

The storage controller updates the index information of the secondary mapping table according to the updated three-level mapping table, and then updates the index information of the primary mapping table according to the updated secondary mapping table, and updates the updated secondary mapping table. The mapping relationship that changes before and after is saved to the DRAM.

In the embodiment of the present invention, the high-speed non-volatile memory means that the read/write speed is faster than the flash, and at the same time, the granularity of the data that can be directly manipulated is smaller each time (for example, operating in bytes instead of pressing the flash) The memory in which the block operates is, for example, MRAM (English: Magnetic Random Access Memory, Chinese: Magnetic Random Access Memory) or PCM (English: Phase-change memory, Chinese: Phase Change Memory). However, high-speed non-volatile memory is usually more expensive than flash, and its capacity is smaller than that of flash, which is not suitable for large-scale use.

In this embodiment, a plurality of locations, such as a mapping table, a log buffer, and a log area, are set to save data mapping relationships, so that after the CPU is powered off, the storage controller can recover according to the saved mapping relationships. In the process, since the search is performed one level at a time through the mapping tables of each level, instead of using the prior art full scan method, the speed is improved in the process of finding the mapping relationship of the data.

On the other hand, when saving each mapping relationship, the characteristics of the high-speed nonvolatile memory and the flash are fully utilized. Specifically, taking the high-speed non-volatile memory as an example of the MRAM, the log buffer area can be placed in the MRAM due to the high speed of the MRAM. Since the CPU writes the data mapping relationship to the DRAM, it also writes to the MRAM. This is a very frequently used operation. If the speed is slow, it will affect the whole system. Therefore, MRAM is used here to save the data in the log buffer area to maximize the performance of the system.

In the meantime, the first mapping table is also placed in the MRAM. Since the primary mapping table is used to search the second and third mapping tables, the address of the primary mapping table must be known first, and the address needs to be fixed. . If the first-level mapping table is placed in a fixed address of the flash, due to the characteristics of the flash itself, when the area is continuously read and written, excessive wear and tear will occur, eventually causing the flash to malfunction. MRAM does not have this problem, so an area can be created in MRAM to place the first level mapping table. At the same time, since the capacity of the primary mapping table is not large (only the index information of the secondary table is saved), it is also suitable to use the MRAM to save the mapping table. Other tables (for example, the secondary mapping table and the tertiary mapping table) occupy a relatively large space, and can be placed in the flash by utilizing the large-capacity feature of the flash to achieve an optimal configuration.

In a possible design, after the CPU is powered on, the storage controller needs to report to the CPU a flag for responding to abnormal power-off, and the flag is located in the register of the storage controller, so that the CPU judges the previous time according to the flag bit. Whether the power is abnormally powered off.

It can be seen that the above-mentioned reporting flag can enable the CPU to quickly and effectively distinguish whether the previous power-off is abnormally powered off. If the power-off is normal, the normal power-on process is triggered. Otherwise, the abnormal power-on is triggered. Process.

In one possible design, the log buffer is divided into n queues, n queues are represented by Q1 to Qn, where n is a positive integer greater than or equal to 1, and the log area includes at least two blocks, and each The block corresponds to a queue in the log buffer; after the storage space in the log buffer reaches the first threshold, the storage controller reads the mapping relationship of the data in the log buffer from the log buffer and saves it to the log. The area includes: after the storage space of the target column reaches the first threshold in the log buffer area, the storage controller stores the mapping relationship of the data in the target column to the position corresponding to the target block in the log area, and the target block is the target column. Corresponding block.

Considering that the storage space in the log buffer is limited, it is not only possible to ensure that there are enough free storage resources in the log buffer area, but also to ensure that the data mapping relationship is written to the flash log area in batches, that is, the content is satisfied. The storage requirement of the log area for the mapping relationship of data.

In a possible design, when the electronic device is working normally, if the number of modified entries of the three-level mapping table after the refresh reaches the third threshold, the storage controller refreshes the secondary mapping table according to the refreshed three-level mapping table. Index information; if the number of modified entries of the secondary mapping table after refreshing reaches a fourth threshold, the storage controller updates the index information of the primary mapping table according to the refreshed secondary mapping table.

In the present invention, the index information is refreshed step by step, and the process of refreshing the secondary mapping table according to the three-level mapping table and refreshing the primary mapping table according to the secondary mapping table is the number of modified entries in the mapping table. Refresh is reached when a certain threshold is reached. It can be seen that the above-mentioned batch refreshing manner can reduce the refreshing frequency of the mapping table under the premise of ensuring that the mapping table is in a new state as much as possible, and at the same time, satisfy the requirement of the mapping table for the refresh operation.

In another aspect, the present invention provides a memory controller that can implement the functions performed by the memory controller in the above method examples, and the functions can be implemented by hardware or by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the above functions.

In another aspect, the present invention provides an electronic device including: a CPU, the above memory controller, a flash, a high speed nonvolatile memory, and a dynamic random access memory (English: Dynamic Random Access Memory, DRAM for short) The memory controller is configured to perform the corresponding function of the memory controller in the above method. The electronic device can also include a communication interface for communicating with other devices.

In still another aspect, the present invention provides a computer storage medium for storing computer software instructions for use in the storage controller described above, including a program designed to perform the above aspects.

The storage system power-down protection method, the storage controller and the electronic device provided by the invention, the high-speed non-volatile memory refers to a memory with a faster read/write speed than the flash, and at the same time, a smaller granularity of data can be directly manipulated each time, for example , MRAM or PCM. However, high-speed non-volatile memory is usually more expensive than flash, and its capacity is smaller than that of flash, which is not suitable for large-scale use. In the present invention, a plurality of locations such as a mapping table and a log buffer area and a log area are set to save data mapping relationships, so that after the CPU is powered off, the storage controller can recover according to the saved mapping relationships. In the process, since it is searched step by step through various levels of mapping tables, instead of using the prior art full-disk scanning method, the speed is improved in the process of finding the mapping relationship of data. Moreover, the characteristics of the high-speed nonvolatile memory and the flash are fully utilized when the respective mapping relationships are saved. Specifically, taking the high-speed non-volatile memory as an example of the MRAM, the log buffer area can be placed in the MRAM due to the high speed of the MRAM. Since the CPU writes the data mapping relationship to the DRAM, it also writes to the MRAM. This is a very frequently used operation. If the speed is slow, it will affect the whole system. Therefore, MRAM is used here to save the data in the log buffer area to ensure the performance of the system to the greatest extent. At the same time, the present invention also places the primary mapping table in the MRAM. Since the primary mapping table is used to search the secondary and tertiary mapping tables, the address of the primary mapping table must be known first, and this address needs to be fixed. If the first-level mapping table is placed in a fixed address of the flash, due to the characteristics of the flash itself, when the area is continuously read and written, excessive wear and tear will occur, eventually causing the flash to malfunction. MRAM does not have this problem, so an area can be created in MRAM to place the first level mapping table. At the same time, since the capacity of the primary mapping table is not large, it is also suitable to use MRAM to save the mapping table. Other tables occupy a relatively large space, and can be placed in the flash by utilizing the feature of flash large capacity, thereby achieving optimal configuration.

DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings to be used in the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without any creative work.

1 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;

2 is a flowchart of a method for powering down protection of a storage system according to an embodiment of the present invention;

3 to FIG. 6 are schematic structural diagrams of another MRAM according to an embodiment of the present invention;

FIG. 7 is a flowchart of another method for powering down protection of a storage system according to an embodiment of the present invention;

FIG. 8 is a schematic structural diagram of a storage controller according to an embodiment of the present disclosure;

FIG. 9 is a schematic structural diagram of another storage controller according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

Referring to FIG. 1, the present invention is applicable to an electronic device including a CPU, a storage controller, and Flash, high speed non-volatile memory and DRAM. The DRAM can be specifically a memory, the high-speed non-volatile memory can be an MRAM, and the storage controller can be implemented by using an FPGA.

In the present invention, the high-speed non-volatile memory stores a first-level mapping table and a log buffer area, and the flash stores a second-level mapping table, a three-level mapping table, and a log area, wherein the log buffer area is used to save the electronic device. During normal operation, the CPU writes the mapping relationship of the data in the log buffer area through the storage controller while writing the mapping relationship of the data to the DRAM; the log area is used after the storage space in the log buffer area reaches the first threshold. The mapping relationship between the data read by the storage controller from the log buffer area is saved; the index information of the three-level mapping table is a data mapping relationship, and the three-level mapping table is used when the data in the log area reaches a second threshold, The level mapping table is refreshed and saves the mapping relationship of the data in the log area; the index information of the primary mapping table is the mapping relationship of the secondary mapping table; the index information of the secondary mapping table is the mapping relationship of the tertiary mapping table; the mapping relationship is The correspondence between logical addresses and physical addresses.

It should be noted that the first threshold value and the second to fourth threshold values mentioned later may be preset according to an empirical value or a specific application scenario when setting. The function of the first threshold is to determine whether the mapping relationship of the data stored in the log buffer needs to be written into the log area of the flash; the role of the second threshold is to determine whether the mapping relationship of the data stored in the log area needs to be written to the flash. The third threshold is used to determine whether the modified entry in the refreshed three-level mapping table needs to be refreshed into the secondary mapping table; the fourth threshold is to determine the refreshed secondary mapping table. Whether the modified entry in the need to be refreshed into the primary mapping table. It should be noted that the first threshold and the second threshold are both used as reference values for the storage space occupation. For example, the first threshold and/or the second threshold may be set to 100%, 90%, etc., for indicating storage space. The parameter of the occupancy condition, wherein if the first threshold is set to 100%, it indicates that after the storage space in the log buffer is full, the storage controller writes the mapping relationship of the data in the log buffer to the flash log. In the zone, the third and fourth thresholds are all reference values of the number of modified entries, for example, the third threshold and/or the fourth threshold may be set to 50, 100, etc. are used to indicate the number of modified entries. The parameter, wherein if the third threshold is set to 50, it indicates that after the third table is modified to have 50 entries after the refresh, the storage controller refreshes the secondary mapping according to the refreshed three-level mapping table. Index information for the table. In addition, in the present invention, the values of the first threshold and the second threshold may be the same or different, and the values of the third threshold and the fourth threshold may be the same or different, which is not limited herein, and the threshold is set. And the parameter type is not limited. For example, the parameter type can be other types such as a percentage, an integer, and the like.

In addition, if the mapping relationship of the data in the log buffer area has been written in the log area of the flash, in order to save storage space, the storage controller can directly delete the content that has been written to the log area in the log buffer area, and the release is deleted. When the content occupies a space to ensure that the party log buffer needs to store a new data mapping relationship, the log buffer can still provide sufficient storage space for the caching process, that is, storage resources. Alternatively, the storage controller does not delete the content in the log buffer area, but marks the part of the content, and directly overwrites the part that has been marked when the mapping relationship of the new data is written to the log buffer. In the same way, the effect of full use of space can also be achieved. For the three-level mapping table, if the data stored in the log area reaches the second threshold, the storage controller also needs to write the contents of the log area into the three-level mapping table by the block, and, in order to save the flash storage. Space, you also need to delete the contents of the log area.

Embodiments of the present invention provide a storage system power failure protection method. As shown in FIG. 2, the method may be performed by the foregoing storage controller.

It should be noted that the storage controller may specifically include an MRAM controller and an SSD controller, wherein the MRAM controller may be used to monitor the status of the primary mapping table and the log buffer in the MRAM, for example, determining the storage of the log buffer. Whether the space reaches a certain threshold, in addition, the MRAM controller can also notify the SSD controller to perform corresponding operations according to the state of the MRAM; similarly, the SSD controller can be used to monitor the secondary mapping table, the tertiary mapping table and the log area in the flash. The state of the data, for example, whether the mapping relationship of the data in the current three-level mapping table needs to be refreshed step by step into the second-level mapping table and the first-level mapping table, in addition, the SSD controller can also notify the MRAM controller according to the state of the flash. Take the appropriate action.

In addition, the specific implementation process of the foregoing storage controller is proposed below, and is not described herein again, and the foregoing SSD controller and the MRAM controller are only used as a specific implementation manner of the storage controller, but are not limited to the foregoing implementation manner. .

The method flow includes:

101. After the CPU is powered off for the previous time, the storage controller determines the physical address of the secondary mapping table according to the index information of the primary mapping table, and finds the secondary mapping table according to the physical address of the secondary mapping table. The index information of the secondary mapping table is accessed to determine the physical address of the tertiary mapping table, and then the tertiary mapping table is found according to the physical address of the tertiary mapping table, and the index information of the tertiary mapping table is determined.

102. The storage controller reads the mapping relationship of all the data in the log buffer area and the mapping relationship of all the data in the log area.

103. The storage controller sends the index information of the three-level mapping table, the mapping relationship of all the data in the log buffer area, and the mapping relationship of all the data in the log area to the CPU.

104. When the storage controller determines, according to the index information of the three-level mapping table and the mapping relationship of all the data in the log buffer area, the mapping relationship between the at least one data in the log buffer area or the mapping relationship in the log area is at the third level. If the mapping relationship in the mapping table is inconsistent, the mapping relationship in the log buffer area or the mapping relationship in the log area is used to replace the mapping relationship in the third-level mapping table.

Wherein, in the replacement, the mapping relationship of at least one data in the log buffer area is preferentially replaced.

105. The storage controller updates the index information of the second mapping table according to the refreshed three-level mapping table, and then updates the index information of the primary mapping table according to the updated secondary mapping table, and the updated secondary mapping table is The mapping relationship that changes before and after the update is saved to the DRAM.

In the present invention, in order to save flash storage resources, the secondary mapping table in the flash may be cleared after the DRAM saves the updated secondary mapping table.

It should be noted that when the CPU is powered off normally, at the software level, some program modules (for example, drivers) of the storage controller may invoke the algorithm power-off interface to notify the algorithm to perform normal power-off operations; the algorithm calls the saveMap3inSSD function and passes The drive logic writes all updated three-level mapping tables in the DRAM to the flash, and returns the physical address of the newly-written three-level mapping table in the flash; according to the physical address of the newly written three-level mapping table in the returned flash Updating the contents of the secondary mapping table in the DRAM; writing all updated secondary mapping tables in the updated DRAM to the flash, and returning the physical address newly written to the secondary mapping table; the secondary mapping table to be returned The physical address is saved to the first-level mapping table of the MRAM; all the blocks in the current log area in the flash are all set as garbage blocks, and the power-off operation is completed to the drive return algorithm, and the driver can be used in the register of the storage controller. The flag flag of the abnormal power-off process in the previous power-off process is set to 1, which means that the previous power-off process is a normal power-off.

In the present invention, the high-speed non-volatile memory means that the reading and writing speed is faster than that of the flash, and at the same time, the granularity of the data can be directly manipulated each time (for example, operating in bytes without operating in blocks like flash) Memory, for example, MRAM or PCM. However, high-speed non-volatile memory is usually more expensive than flash, and its capacity is smaller than that of flash, which is not suitable for large-scale use.

On the other hand, when saving each mapping relationship, the characteristics of the high-speed nonvolatile memory and the flash are fully utilized. Specifically, taking the high-speed non-volatile memory as an example of the MRAM, the log buffer area can be placed in the MRAM due to the high speed of the MRAM. Since the CPU writes the data mapping relationship to the DRAM, it also writes to the MRAM. This is a very frequently used operation. If the speed is slow, it will affect the whole system. Therefore, MRAM is used here to save the data in the log buffer area to ensure the performance of the system to the greatest extent.

Since the CPU may be powered off or abnormally powered off before the CPU is powered on, the different power-off states may trigger different processing flows when the CPU is powered on again. Therefore, in the embodiment of the present invention, In an implementation manner, when the CPU is powered on, the flag of the storage controller can be read to determine that the previous power-off process is normal power-off or abnormal power-off operation, and then select different processing according to the power-off state. Process. Therefore, after the CPU is powered on, the storage controller reports the flag for reflecting the abnormal power-off to the CPU.

Specifically, the flag bit can be located in a register in the memory controller. When the CPU is powered off normally, the driver in the memory controller can set the flag bit, for example, setting the flag bit flag to 1; Because the memory controller is powered off, the setting of the flag bit cannot be completed. Therefore, when the CPU is powered on again, the flag value read is a value (such as 0) during normal operation, instead of 1 When the CPU is powered off, it is abnormally powered off. It should be noted that the manner of distinguishing whether the CPU is normally powered off is not limited to the implementation manner of the above-mentioned setting flag, and may be other operations that can be used to distinguish the CPU power-off state, and details are not described herein.

In this implementation, the method for reading the flag bit can be used to enable the storage controller to quickly and effectively distinguish whether the previous power-off is abnormally powered off. If the power-off is normal, the normal power-on process of the CPU is triggered. Otherwise, , triggers the above abnormal power-on process.

In this embodiment, the normal power-on process of the CPU is: the CPU receives the drive controller to read the flag bit, invokes the algorithm initialization interface, and transmits the flag bit. When the flag bit flag=1, the algorithm normally calls the power-on process. That is, the algorithm reads the contents of the primary mapping table in the high-speed non-volatile memory through the driving logic, and according to the primary mapping The physical address of the secondary mapping table recorded in the table, find the location of the secondary mapping table in the flash, access the contents of the secondary mapping table, and save the content of the read secondary mapping table in the main storage, that is, in the In DRAM, and return the determination information to the driver.

When the CPU is powered on normally, the CPU can directly find the physical address of the secondary mapping table stored in the SSD according to the mapping relationship in the primary mapping table stored in the high-speed non-volatile memory, and then access the secondary mapping table, and Synchronizing the mapping relationship in the secondary mapping table to the DRAM, so that when the data is subsequently read, the physical address stored in the flash of the three-level mapping table can be determined according to the secondary mapping table in the DRAM, and The level mapping table determines the storage address of the data.

When the CPU is powered off abnormally, that is, the previous power-down of the CPU is abnormally powered off, the storage medium has been powered off before it can perform any operation. This means that the mapping relationship stored in the DRAM is lost due to abnormal power-down, and only the high-speed non-volatile memory with non-volatile characteristics and the data stored in the flash are retained. Therefore, the storage controller may find the physical address of the secondary mapping table stored in the flash according to the mapping relationship in the primary mapping table, and then access the secondary mapping table, and find the storage in the flash according to the mapping relationship in the secondary mapping table. The physical address of the three-level mapping table, and the mapping relationship of the data stored in the three-level mapping table is read.

In another embodiment, in order to conveniently write the contents of the log buffer to the log area of the flash in batches, the log buffer may be divided into n queues, wherein n queues may be represented by Q0 to Qn. n is a positive integer greater than or equal to 1, the log area includes at least two blocks, and each block corresponds to a column in the log buffer. In the embodiment of the present invention, when a certain condition is met, the storage controller may write the content stored in the log buffer area to the log area according to the queue. Therefore, after the storage space in the log buffer reaches the first threshold, the storage controller reads the mapping relationship of the data in the log buffer from the log buffer and saves the data to the log area.

After the storage space of the target column reaches the first threshold in the log buffer, the storage controller stores the mapping relationship of the data in the target column to the location corresponding to the target block in the log area, and the target block is the block corresponding to the target column.

It should be noted that the block can be regarded as an area corresponding to the queue. The composition of the block is the same as the queue, and is an area composed of a plurality of entries.

For example, when the MRAM is in the state shown in FIG. 3, if the CPU is powered off normally, the storage controller can write the mapping relationship in the Q0 to Qn queue of the log buffer to the log area of the flash, and in the log buffer area. After the storage space reaches the first threshold, the content in the log area is flushed to the three-level mapping table, and the second-level mapping table and the first-level mapping table, that is, the mapping table index area in the MRAM is finally refreshed. The process of flushing the contents of the three-level mapping table to the second-level mapping table and the first-level mapping table step by step will be proposed later, and will not be described here. It should be noted that the status table area in the figure corresponds to each block in the log area of the flash. Therefore, when the three-level mapping table is updated, the status table area located in the MRAM is also updated.

As shown in FIG. 4, in order to write the already generated mapping relationship to the corresponding queue in the MRAM, the storage state of the log buffer area in the MRAM.

As shown in FIG. 5, after the storage space of the at least one queue in the Q0 to Qn queue reaches the first threshold, the mapping relationship of the data stored in the at least one queue is written in the log area of the flash, and then according to The mapping relationship that has been written to the log area of the flash updates the status table area.

After the CPU is powered off normally, the storage state of the high-speed non-volatile memory is as shown in FIG. 6, that is, the data in the Q0 to Qn queue of the log buffer area is written to the log area of the flash, and after the write operation is completed, Clear All the contents of the log buffer.

When the CPU is powered off abnormally at a certain time, that is, when the CPU is abnormally powered down, the storage medium has not been able to perform any operation and has been powered down. The storage state of the MRAM is any one as shown in Figures 3 to 5. status. At this time, the content in the MRAM does not perform any operation, and the flag bit is not changed, that is, the CPU is powered off abnormally.

When the CPU is powered on again, the memory controller reads the flag bit and reports it to the CPU. This determines that the CPU is powered up abnormally. At this time, the latest or newer mapping information is stored in the Q0 to Qn queue and the log area, and some parts of the mapping table in each level are non-latest mapping information. The storage controller can read the contents stored in the Q0 to Qn queue, the log area, and the three-level mapping table by the partition block, and compare them. The new and old mapping relationships are in the order of Q0 to Qn queues, log areas, and tertiary mapping tables. After comparison, the storage controller can refresh the three-level mapping table according to the latest mapping information, so that the secondary mapping table and the primary mapping table are updated step by step after satisfying certain refreshing conditions, and then the Q0 to Qn queues and the log area are cleared. Thereby completing the restoration of the mapping relationship.

In the present invention, considering that the storage space in the log buffer area is limited, it is not only ensured that there are enough free storage resources in the log buffer area, but also ensures that the data mapping relationship is written to the log area of the flash in batches. Medium, that is, the storage requirement of the log area for the mapping relationship of data is satisfied.

In an implementation manner of the embodiment of the present invention, when the electronic device is working normally, the process of refreshing the secondary mapping table and the primary mapping table step by step from the three-level mapping table may be implemented as shown in FIG. 7:

201. If the number of modified entries after the three-level mapping table reaches the third threshold, the storage controller refreshes the index information of the secondary mapping table according to the refreshed three-level mapping table.

202. If the number of the modified entries of the secondary mapping table after the refresh reaches the fourth threshold, the storage controller updates the index information of the primary mapping table according to the updated secondary mapping table.

It can be seen that, in the process of refreshing the secondary mapping table and the primary mapping table step by step from the three-level mapping table, it is determined according to the number of modified entries of the mapping table after refreshing whether it needs to be refreshed to the next-level mapping table. By adopting the above refresh process, not only the flash can be satisfied for the write operation, but also the number of write operations for refreshing can be reduced.

The solution provided by the embodiment of the present invention is mainly introduced from the perspective of a storage controller in an electronic device. It can be understood that the storage controller includes corresponding hardware structures and/or software modules for performing the respective functions in order to implement the above functions. Those skilled in the art will readily appreciate that the present invention can be implemented in a combination of hardware or hardware and computer software in combination with the elements and algorithm steps of the various examples described in the embodiments disclosed herein. Whether a function is implemented in hardware or computer software to drive hardware depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods for implementing the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present invention.

The embodiment of the present invention may divide a function module into a storage controller or the like according to the foregoing method example. For example, each function module may be divided according to each function, or two or more functions may be integrated into one processing module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of the module in the embodiment of the present invention is schematic, and is only a logical function division, and the actual implementation may have another division manner.

In the case where each functional module is divided by corresponding functions, or in the case of an integrated unit, FIG. 8 shows a possible structural diagram of the memory controller involved in the above embodiment. Storage controller 30 includes a determination module 31, an acquisition module 32, a transmission module 33, a processing module 34, and a storage module 35. For example, the determining module 31 is configured to execute the process 101 of FIG. 2; the obtaining module 32 is configured to execute the process 102 of FIG. 2; the sending module 33 is configured to execute the process 103 of FIG. 2; and the processing module 34 is configured to execute FIG. Process 104 and process 105, and process 201 and process 202 of FIG. 4; storage module 35 for storing program code and data of the storage controller. All the related content of the steps involved in the foregoing method embodiments may be referred to the functional descriptions of the corresponding functional modules, and details are not described herein again.

The determining module 31 and the processing module 34 may be integrated on the processor, and the processor may be a central processing unit (English: Central Processing Unit, CPU for short), a general-purpose processor, and a digital signal processor (English: Digital Signal Processor, Abbreviation: DSP), Application-Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA) or other programmable logic devices, transistor logic devices, Hardware components or any combination thereof. It is possible to implement or carry out the various illustrative logical blocks, modules and circuits described in connection with the present disclosure. The processor may also be a combination of computing functions, for example, including one or more microprocessor combinations, a combination of a DSP and a microprocessor, and the like. The obtaining module 32 and the sending module 33 may specifically be a transceiver, a transceiver circuit, a communication interface, or the like. The storage module 35 can be a memory.

When the determining module 31 and the processing module 34 are processors, the obtaining module 32 and the sending module 33 are communication interfaces, and the storage module 35 is a memory, the storage controller according to the embodiment of the present invention may be the storage controller shown in FIG. 40.

Referring to FIG. 9, the memory controller 40 includes a processor 41, a communication interface 42, a memory 43, and a bus 44. The processor 41, the communication interface 42 and the memory 43 are mutually connected by a bus 44; the bus 44 may be a Peripheral Component Interconnect (PCI) bus or an extended industry standard structure (English: Extended Industry) Standard Architecture, referred to as EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in Figure 9, but it does not mean that there is only one bus or one type of bus.

The steps of a method or algorithm described in connection with the present disclosure may be implemented in a hardware, or may be implemented by a processor executing software instructions. The software instructions may be composed of corresponding software modules, and the software modules may be stored in a random access memory (English: Random Access Memory, RAM for short), flash memory, read only memory (English: Read Only Memory, referred to as: ROM), Erase programmable read-only memory (English: Erasable Programmable ROM, referred to as: EPROM), electrically erasable programmable read-only memory (English: Electrically EPROM, referred to as: EEPROM), registers, hard disk, mobile hard disk, read-only optical disk (referred to as : CD-ROM) or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor to enable the processor to read information from, and write information to, the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and the storage medium can be located in an ASIC.

Those skilled in the art will appreciate that in one or more examples described above, the functions described herein can be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored in a computer readable medium or transmitted as one or more instructions or code on a computer readable medium. Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another. The storage medium can be a general purpose or special meter Any available media that the computer can access.

The specific embodiments of the present invention have been described in detail with reference to the preferred embodiments of the present invention. The scope of the protection, any modifications, equivalent substitutions, improvements, etc., which are made on the basis of the technical solutions of the present invention, are included in the scope of the present invention.

Claims

A storage system power failure protection method is characterized in that the method is used in an electronic device, and the electronic device includes: a central processing unit CPU, a storage controller, a flash memory, a high speed nonvolatile memory, and a dynamic a random access memory DRAM, wherein the high-speed non-volatile memory stores a first-level mapping table and a log buffer area, wherein the flash stores a second-level mapping table, a three-level mapping table, and a log area, wherein

The log buffer area is configured to save, when the electronic device is working normally, the CPU writes the data in the log buffer area by using the storage controller while writing a mapping relationship of data to the DRAM. Mapping relations;

The log area is configured to save a mapping relationship between data read by the storage controller from the log buffer area after the storage space in the log buffer area reaches a first threshold;

The index information of the three-level mapping table is a mapping relationship of data, and the three-level mapping table is configured to refresh and save the log when the data in the log area reaches a second threshold. The mapping relationship of data in the area;

The index information of the primary mapping table is a mapping relationship of the secondary mapping table;

The index information of the secondary mapping table is a mapping relationship of the tertiary mapping table;

The mapping relationship is a correspondence between a logical address and a physical address;

The method includes:

After the power-off of the CPU is abnormally powered off, the storage controller determines the physical address of the secondary mapping table according to the index information of the primary mapping table, and finds the secondary mapping table according to the physical address of the secondary mapping table. The physical address of the tertiary mapping table is determined by accessing the index information of the secondary mapping table, and then the tertiary mapping table is found according to the physical address of the tertiary mapping table, and the index information of the tertiary mapping table is determined;

The storage controller reads a mapping relationship of all data in the log buffer area, and a mapping relationship of all data in the log area;

The storage controller sends, to the CPU, index information of the three-level mapping table, a mapping relationship of all data in the log buffer area, and a mapping relationship of all data in the log area;

When the storage controller determines, according to the index information of the three-level mapping table, the mapping relationship of all the data in the log buffer area, that the mapping relationship between the at least one data in the log buffer area is When the mapping relationship in the log area is inconsistent with the mapping relationship in the three-level mapping table, the mapping relationship of the at least one data in the log buffer area or the mapping relationship in the log area is replaced with the mapping relationship in the log area. a mapping relationship in the three-level mapping table, wherein, when replacing, preferentially replacing the mapping relationship of the at least one data in the log buffer area;

The storage controller updates the index information of the secondary mapping table according to the updated three-level mapping table, and then updates the index information of the primary mapping table according to the updated secondary mapping table, and the updated secondary mapping table is A mapping relationship that changes before and after the update is saved to the DRAM.
The method according to claim 1, wherein after the CPU is powered on, the method further comprises:

The storage controller reports, to the CPU, a flag bit for reflecting an abnormal power-off, and the flag bit is located in a register of the storage controller, so that the CPU determines, according to the flag bit, whether the previous power-off is abnormal. Under Electricity.
The method according to claim 1 or 2, wherein the log buffer is divided into n queues, and the n queues are represented by Q1 to Qn, where n is a positive integer greater than or equal to 1. The log area includes at least two blocks, and each block corresponds to one queue in the log buffer area;

After the storage space in the log buffer reaches the first threshold, the storage controller reads the mapping relationship between the data in the log buffer from the log buffer, and saves the data to the log area. Specifically include:

After the storage space of the target column in the log buffer reaches the first threshold, the storage controller stores the mapping relationship of the data in the target column to a location corresponding to the target block in the log area. The target block is a block corresponding to the target column.
The method of claim 1, wherein when the electronic device is in normal operation, the method further comprises:

If the number of the modified entries of the three-level mapping table reaches a third threshold after the refresh, the storage controller refreshes the index information of the secondary mapping table according to the updated three-level mapping table;

If the number of the modified entries of the secondary mapping table after the refresh reaches the fourth threshold, the storage controller updates the index information of the primary mapping table according to the refreshed secondary mapping table.
A storage controller, wherein the storage controller is used in an electronic device, and the electronic device further includes: a central processing unit CPU, a flash memory, a high speed nonvolatile memory, and a dynamic random access memory (DRAM) The high-speed non-volatile memory stores a first-level mapping table and a log buffer area, where the flash stores a second-level mapping table, a three-level mapping table, and a log area, where

The log buffer area is configured to save, when the electronic device is working normally, the CPU writes the data in the log buffer area by using the storage controller while writing a mapping relationship of data to the DRAM. Mapping relations;

The log area is configured to save a mapping relationship between data read by the storage controller from the log buffer area after the storage space in the log buffer area reaches a first threshold;

The index information of the three-level mapping table is a mapping relationship of data, and the three-level mapping table is configured to refresh and save the third-level mapping table when the data in the log area reaches a second threshold. Mapping of data in the log area;

The index information of the primary mapping table is a mapping relationship of the secondary mapping table;

The index information of the secondary mapping table is a mapping relationship of the tertiary mapping table;

The mapping relationship is a correspondence between a logical address and a physical address;

The storage controller includes:

a determining module, configured to determine a physical address of the secondary mapping table according to the index information of the primary mapping table, and find the secondary mapping table according to the physical address of the secondary mapping table, after the CPU is powered off for the previous time. The physical address of the tertiary mapping table is determined by accessing the index information of the secondary mapping table, and then the tertiary mapping table is found according to the physical address of the tertiary mapping table, and the index information of the tertiary mapping table is determined;

An obtaining module, configured to read a mapping relationship of all data in the log buffer, and in the log area Mapping of all data;

a sending module, configured to send, to the CPU, index information of the three-level mapping table, a mapping relationship of all data in the log buffer area, and a mapping relationship of all data in the log area;

a processing module, configured to: when the storage controller determines, according to the index information of the three-level mapping table, the mapping relationship of all data in the log buffer area, that the mapping of the at least one data in the log buffer area When the relationship or the mapping relationship in the log area is inconsistent with the mapping relationship in the three-level mapping table, the mapping relationship of the at least one data in the log buffer or the mapping in the log area is used. The relationship replaces the mapping relationship in the three-level mapping table, wherein, in the replacement, the mapping relationship of the at least one data in the log buffer area is preferentially replaced;

The processing module is further configured to update the index information of the second mapping table according to the updated three-level mapping table, and then update the index information of the primary mapping table according to the updated secondary mapping table, and the updated secondary level A mapping relationship in the mapping table that changes before and after the update is saved to the DRAM.
The memory controller according to claim 5, wherein after the CPU is powered on, the sending module is further configured to report, to the CPU, a flag bit for reflecting abnormal power-off, the flag bit And a register located in the storage controller, so that the CPU determines, according to the flag bit, whether the previous power-off is abnormally powered off.
The memory controller according to claim 5 or 6, wherein the log buffer area is divided into n queues, and the n queues are represented by Q0 to Qn, wherein n is greater than or equal to 1 An integer, the log area includes at least two blocks, and each block corresponds to a column in the log buffer area;

The storage controller further includes:

a storage module, configured to: if a storage space of the target column in the log buffer reaches the first threshold, store a mapping relationship of data in the target column to a location corresponding to the target block in the log area, where The target block is a block corresponding to the target column.
The method according to claim 5, wherein when the electronic device is in normal operation, the processing module is further configured to:

If the number of modified entries after the refreshing of the three-level mapping table reaches a third threshold, refreshing the index information of the secondary mapping table according to the updated tertiary mapping table;

If the number of the modified entries after the refreshing of the secondary mapping table reaches the fourth threshold, the index information of the primary mapping table is updated according to the refreshed secondary mapping table.
An electronic device, comprising: a central processing unit CPU, the storage controller according to any one of claims 5 to 8, a flash memory, a high speed nonvolatile memory, and a dynamic random Accessing a memory DRAM, wherein the high-speed non-volatile memory stores a first-level mapping table and a log buffer area, where the flash stores a second-level mapping table, a three-level mapping table, and a log area, where

The log buffer area is configured to save, when the electronic device is working normally, the CPU writes the data in the log buffer area by using the storage controller while writing a mapping relationship of data to the DRAM. Mapping relationship;

The log area is configured to save a mapping relationship between data read by the storage controller from the log buffer area after the storage space in the log buffer area reaches a first threshold;

The index information of the three-level mapping table is a mapping relationship of data, and the three-level mapping table is configured to refresh and save the log when the data in the log area reaches a second threshold. The mapping relationship of data in the area;

The index information of the primary mapping table is a mapping relationship of the secondary mapping table;

The index information of the secondary mapping table is a mapping relationship of the tertiary mapping table;

The mapping relationship is a correspondence between a logical address and a physical address.