CN106502928B - A kind of storage system power-off protection method, storage control and electronic equipment - Google Patents
A kind of storage system power-off protection method, storage control and electronic equipment Download PDFInfo
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- CN106502928B CN106502928B CN201610872062.0A CN201610872062A CN106502928B CN 106502928 B CN106502928 B CN 106502928B CN 201610872062 A CN201610872062 A CN 201610872062A CN 106502928 B CN106502928 B CN 106502928B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/16—Protection against loss of memory contents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7201—Logical to physical mapping or translation of blocks or pages
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Abstract
The invention discloses a kind of storage system power-off protection method, storage control and electronic equipments, are related to field of communication technology, are able to solve storage system needs and take considerable time the problem of carrying out mapping relations recovery.This method comprises: after the previous lower electricity of CPU belongs to abnormal lower electricity, storage control determines the index information of two, three-level mapping table according to the index information of level-one mapping table step by step, and read the mapping relations of the mapping relations of all data and all data in log area in log buffer area；And acquired mapping relations are sent to CPU；When having at least one data when the mapping relations in log buffer area or the mapping relations in log area are with mapping relations difference in three-level mapping table, storage control replaces the mapping relations in three-level mapping table, and the index information of two, level-one mapping table is updated step by step, and the mapping relations to change afterwards before the update in updated second level mapping table are saved to DRAM.The present invention is suitable for storage system.
Description
Technical field
The present invention relates to field of communication technology more particularly to a kind of storage system power-off protection method, storage control and
Electronic equipment.
Background technique
With universal, storage equipment (such as SSD, the Solid State based on flash (Chinese: flash memory) of flash memory technology
Drive, Chinese: solid state hard disk) exploitation, test and user's use process in, may due to terminal generate powered-off fault and
It causes flash state abnormal, is destroyed so as to cause data, ultimately cause device power-up failure.
Currently, power down protection when in order to realize that terminal generates powered-off fault, when writing data, metadata storage module,
Usually in the OOB of each piece of every page (English: Out Of Band, Chinese: the band external space) region, or in last page
OOB regional record data informative abstract, wherein informative abstract includes all pages of logical address and physical address on block
Mapping relations；It is not to be stored in legacy data when being rewritten due to the data in the SSD for belonging to non-volatile media
Position rewritten, but the content of rewriting is stored in the other positions in SSD, and when needing to store reflecting into SSD
It when the relationship of penetrating reaches certain amount, can be written in SSD down, therefore, when power down occurs, although new mapping relations are
It generates, but in view of SSD is stored as unit of data block, may result in new mapping relations in this way and do not write down also
Into SSD and new mapping relations cannot be stored in SSD in time；When storage system powers on, storage array scan module
By scanning the region OOB of every page, or the region OOB of scanning last page to entire SSD, to obtain all data pages
Mapping relations determine that same logical address is corresponding later according to the newness degree of the mapping relations of acquired all data pages
Newest physical address, so that it is determined that newest mapping relations, to realize power down protection.
But since the capacity of SSD is very big, carrying out scan full hard disk to SSD can be taken a substantial amount of time.Therefore, in use
Method is stated to realize power down protection, for the SSD of large capacity, storage system, which needs to take considerable time, carries out the extensive of mapping relations
It is multiple.
Summary of the invention
The present invention provides a kind of storage system power-off protection method, storage control and electronic equipment, is able to solve storage
System needs take considerable time the problem of carrying out mapping relations recovery.
In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that
On the one hand, the present invention provides a kind of storage system power-off protection method, and this method is used for a kind of electronic equipment, electronics
It include: central processing unit (English:, referred to as: CPU), storage control, flash, high speed nonvolatile memory and dynamic in equipment
State random access memory (English:, referred to as: DRAM), level-one mapping table and log are preserved in high speed nonvolatile memory
Buffer area preserves second level mapping table, three-level mapping table and log area in flash, wherein
When log buffer area is worked normally for being stored in electronic equipment, the mapping relations of data are being write DRAM by CPU
While, the mapping relations of data in log buffer area are write by storage control；
If log area is used for after the memory space in log buffer area reaches first threshold, storage control is saved from day
The mapping relations of the data read in will buffer area；
The index information of three-level mapping table is the mapping relations of data, and data of the three-level mapping table in log area reach
When to second threshold, three-level mapping table is refreshed and saves the mapping relations of data in log area；
The index information of level-one mapping table is the mapping relations of second level mapping table；
The index information of second level mapping table is the mapping relations of three-level mapping table；
Mapping relations are the corresponding relationship of logical address and physical address；
This method comprises:
After the previous lower electricity of CPU belongs to abnormal lower electricity, storage control determines two according to the index information of level-one mapping table
The physical address of grade mapping table, and second level mapping table is found according to the physical address of second level mapping table, pass through access second level mapping
The index information of table determines the physical address of three-level mapping table, finds three-level according to the physical address of three-level mapping table later and reflects
Firing table determines the index information of three-level mapping table；
Storage control reads reflecting for mapping relations of all data in log buffer area and all data in log area
Penetrate relationship；
Storage control mapping of all data into the index information of CPU transmission three-level mapping table, log buffer area is closed
The mapping relations of all data in system and log area；
When storage control in CPU according to the mapping of all data in the index information of three-level mapping table, log buffer area
Relationship judgement have at least one data the mapping relations in log buffer area or mapping relations in log area in three-level
When mapping relations in mapping table are inconsistent, using at least one data in the mapping relations in log buffer area or in log area
In mapping relations replace the mapping relations in three-level mapping table, wherein replacement when, preferentially use at least one data
Mapping relations in log buffer area are replaced；
Storage control updates the index information of second level mapping table according to the three-level mapping table after refreshing, later according to update
Second level mapping table afterwards updates the index information of level-one mapping table, and will occur afterwards before the update in updated second level mapping table
The mapping relations of change are saved to DRAM.
Wherein, in the embodiment of the present invention, high speed nonvolatile memory refers to read or write speed ratio flash faster, meanwhile, often
It is secondary can immediate operand evidence granularity it is smaller (for example, by byte operated rather than flash operated by block)
Memory, for example, MRAM (English: Magnetic Random Access Memory, Chinese: magnetic RAM)
Or PCM (English: Phase-change memory, Chinese: phase transition storage).But high speed nonvolatile memory usually at
, than flash high, capacity is also smaller than flash for this, can not be suitble to large-scale use.
In the present embodiment, data are saved provided with multiple positions such as mapping tables at different levels and log buffer area, log area
Mapping relations so that CPU power-off after, storage control can be restored according to each mapping relations of preservation, in this mistake
Cheng Zhong is searched one by one by then passing through mapping tables at different levels, rather than uses the mode of prior art scan full hard disk, because
This, improves speed during searching the mapping relations of data.
On the other hand, when saving each mapping relations, high speed nonvolatile memory and flash are also fully utilized by
The characteristics of.Specifically, by taking high speed nonvolatile memory is MRAM as an example, it, can be by log due to the fireballing characteristic of MRAM
Buffer area is put in a mram, since CPU is when writing DRAM for data mapping relations, can also write MRAM, this is a using frequency
The very high operation of rate can impact whole system if speed is slow, therefore, save log buffer used here as MRAM
The data in area can utmostly guarantee the performance of system.
Meanwhile level-one mapping table is also also disposed in MRAM by the present embodiment, due to level-one mapping table be for search two,
Three-level mapping table, so must first know the address of level-one mapping table, and this address needs to fix.If level-one mapped
Table is placed in a piece of fixing address of flash, due to the characteristic of flash itself, when constantly reading and writing this part region, can be generated
More abrasions, eventually lead to flash and break down.And it MRAM and therefore can specially open up in a mram there is no this problem
One piece of region carries out the placement of level-one mapping table.Simultaneously as the capacity of level-one mapping table (only will not save second level greatly very much
The index information of table), therefore, MRAM is suitable for use of to save mapping table.And other tables are (for example, second level mapping table, three-level are reflected
Firing table) occupied space is relatively large, and the characteristic that can use flash large capacity is placed in flash, is matched to be optimal
It sets.
In a kind of possible design, after CPU is powered on, storage control needs to report to CPU for abnormal reaction
The flag bit of lower electricity, the flag bit are located at the register of storage control, so that whether CPU judges previous lower electricity according to flag bit
Belong to abnormal lower electricity.
It can be seen that using it is above-mentioned report flag bit by the way of, can make CPU quickly and efficiently distinguish it is previous it is lower electricity whether
Belong to abnormal lower electricity, if belonging to normal lower electricity, triggering normally powers on process, otherwise, then triggers above-mentioned exception and power on process.
In a kind of possible design, log buffer area is divided into n queue, and n queue is indicated with Q1 to Qn,
In, n is the positive integer more than or equal to 1, and log area includes at least two blocks, and each block corresponds in log buffer area
One queue；After the memory space in log buffer area reaches first threshold, storage control is read from log buffer area
The mapping relations of data in log buffer area, and it is saved in log area, specifically include: target column deposits in log buffer area
After storage space reaches first threshold, the mapping relations of data in target column are stored into log area target block by storage control
Corresponding position, target block are the corresponding block of target column.
In view of the limited storage space in log buffer area, it so can not only guarantee exist in log buffer area
Enough free time storage resources, while can also guarantee, the mapping relations of data are write in the log area of flash in batches, i.e.,
Log area is met for the memory requirement of the mapping relations of data.
In a kind of possible design, when electronic equipment works normally, if three-level mapping table is after refreshing by modification item
Purpose quantity reaches third threshold value, then storage control is believed according to the index that the three-level mapping table after refreshing refreshes second level mapping table
Breath；If second level mapping table reaches the 4th threshold value by the quantity of modification entry after refreshing, after storage control is according to refreshing
The index information of second level mapping table update level-one mapping table.
In the present invention, index information refreshes step by step, and refreshes second level mapping table, Yi Jigen according to three-level mapping table
The process for refreshing level-one mapping table according to second level mapping table is to be modified the quantity of entry in the mapping table to reach certain threshold value
When, just refreshed.It can be seen that by the way of above-mentioned batch refresh, can ensure as far as possible mapping table be in compared with
Under the precondition of new state, the refreshing frequency of mapping table is reduced, meanwhile, meet the needs of mapping table is for refresh operation.
On the other hand, the present invention provides a kind of storage control, which may be implemented in above method example
Function performed by storage control, the function can also execute corresponding software by hardware realization by hardware
It realizes.The hardware or software include one or more above-mentioned corresponding modules of function.
Another aspect, the present invention provide a kind of electronic equipment, include: in the electronic equipment CPU, above-mentioned storage control,
Flash, high speed nonvolatile memory and dynamic random access memory (English: Dynamic Random Access
Memory, referred to as: DRAM), which is used to execute the corresponding function of storage control in the above method.The electronics is set
It can also include communication interface in standby, for being communicated between other equipment.
Another aspect, the present invention provides a kind of computer storage mediums, for being stored as used in above-mentioned storage control
Computer software instructions, it includes for executing program designed by above-mentioned aspect.
Storage system power-off protection method, storage control and electronic equipment provided by the invention, high speed nonvolatile are deposited
Reservoir refers to read or write speed ratio flash faster, meanwhile, every time can immediate operand evidence the smaller memory of granularity, for example,
MRAM or PCM.But high speed nonvolatile memory typically cost ratio flash high, capacity is also smaller than flash, can not be suitble to big
Scale uses.In the present invention, data are saved provided with multiple positions such as mapping tables at different levels and log buffer area, log area
Mapping relations so that CPU power-off after, storage control can be restored according to each mapping relations of preservation, in this mistake
Cheng Zhong is searched step by step by then passing through mapping tables at different levels, rather than uses the mode of prior art scan full hard disk, therefore,
Speed is improved during the mapping relations for searching data.Also, when saving each mapping relations, it is also fully utilized by height
Fast nonvolatile memory and the characteristics of flash.Specifically, by taking high speed nonvolatile memory is MRAM as an example, due to
The fireballing characteristic of MRAM can put log buffer area in a mram, since data mapping relations are being write DRAM by CPU
When, MRAM can be also write, this is that the very high operation of frequency of use can impact whole system if speed is slow, because
This, the data in log buffer area are saved used here as MRAM, can utmostly guarantee the performance of system.Meanwhile the present invention
Also level-one mapping table is also disposed in MRAM, since level-one mapping table is for searching two, three-level mapping table, so necessary
First know the address of level-one mapping table, and this address needs to fix.If level-one mapping table is placed on a piece of fixation of flash
In address, due to the characteristic of flash itself, when constantly reading and writing this part region, excessive abrasion can be generated, flash is eventually led to
It breaks down.And MRAM and therefore one piece of region can be specially opened up in a mram and is reflected to carry out level-one there is no this problem
The placement of firing table.Simultaneously as the capacity of level-one mapping table will not be very big, therefore, MRAM is suitable for use of to save mapping
Table.And other table occupied spaces are relatively large, the characteristic that can use flash large capacity is placed in flash, to reach
Allocation optimum.
Detailed description of the invention
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to needed in the embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is the structural schematic diagram of a kind of electronic equipment provided in an embodiment of the present invention；
Fig. 2 is a kind of storage system power-off protection method flow chart provided in an embodiment of the present invention；
Fig. 3 to Fig. 6 is the structural schematic diagram of another kind MRAM provided in an embodiment of the present invention；
Fig. 7 is another storage system power-off protection method flow chart provided in an embodiment of the present invention；
Fig. 8 is a kind of structural schematic diagram of storage control provided in an embodiment of the present invention；
Fig. 9 is the structural schematic diagram of another storage control provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts all other
Embodiment shall fall within the protection scope of the present invention.
Referring to Fig. 1, the present invention is suitable for a kind of electronic equipment, include in the electronic equipment CPU, storage control,
Flash, high speed nonvolatile memory and DRAM.Wherein, DRAM is specifically as follows memory, and high speed nonvolatile memory is specific
It can be MRAM, storage control can be realized with FPGA.
In the present invention, level-one mapping table and log buffer area are preserved in high speed nonvolatile memory, are protected in flash
There are second level mapping table, three-level mapping table and log area, wherein log buffer area is for being stored in electronic equipment normal work
When, CPU writes reflecting for data in log buffer area while the mapping relations of data are write DRAM, through storage control
Penetrate relationship；If log area is used for after the memory space in log buffer area reaches first threshold, storage control is saved from day
The mapping relations of the data read in will buffer area；The index information of three-level mapping table is the mapping relations of data, three-level mapping
When data of the table in log area reach second threshold, three-level mapping table is refreshed and saves the mapping of data in log area
Relationship；The index information of level-one mapping table is the mapping relations of second level mapping table；The index information of second level mapping table reflects for three-level
The mapping relations of firing table；Mapping relations are the corresponding relationship of logical address and physical address.
It should be noted that above-mentioned first threshold, and the second to the 4th mentioned hereinafter threshold value, in setting,
It can empirically be worth or specific application scenarios are preset.Wherein, the effect of first threshold is to differentiate that log is slow
Whether the mapping relations for depositing the data stored in area need to write in the log area of flash；The effect of second threshold is to differentiate
Whether the mapping relations of the data stored in log area need to write in the three-level mapping table of flash；Third threshold value acts on
Whether the entry modified in the three-level mapping table after differentiation refreshes needs to flush in second level mapping table；The work of 4th threshold value
With being to differentiate whether the entry modified needs to flush in level-one mapping table in the second level mapping table after refreshing.Also need
Bright, the first, second threshold value is used as the reference value of memory space occupancy situation, for example, the first threshold and/or this second
Threshold value can be set to 100%, and 90% waits the parameter for indicating memory space occupancy situation, wherein if by first threshold
Value is set as 100%, then shows after the memory space in log buffer area has been expired, and storage control will be in log buffer area
The mapping relations of data are write in the log area of flash；Third, the 4th threshold value are used as by the reference of the quantity of modification entry
Value, for example, the third threshold value and/or the 4th threshold value can be set to 50 articles, 100 numbers waited for indicating modification entry
The parameter of amount, wherein if setting 50 for the third threshold value, the entry for showing that three-level table is modified after refreshing reaches 50
After item, then storage control can refresh the index information of second level mapping table according to the three-level mapping table after refreshing.In addition, in this hair
In bright, the value of first threshold and second threshold can be identical or different, and the value of third threshold value and the 4th threshold value can also phase
With or it is different, it is not limited here, and the set-up mode of above-mentioned threshold value and parameter type are also with no restrictions, for example, parameter class
Type can be the other types such as percentage, integer.
In addition, if the mapping relations of the data in log buffer area have been written in the log area of flash, then in order to save
Memory space is saved, the content that log area is had been written in log buffer area can be deleted directly, be discharged simultaneously by storage control
The occupied space of content has been deleted, when ensuring that Party day will buffer area needs to store the mapping relations of new data, the log
Buffer area still is able to provide enough memory spaces, i.e. storage resource for process of caching.Alternatively, storage control is not to log
Content in buffer area is deleted, but the contents of the section is marked, and when the mapping relations of new data write day
When will buffer area, the part content that directly covering has been labeled so equally can achieve the effect that space makes full use of
Fruit.For three-level mapping table, if after the data that log area is stored reach second threshold, storage control also need by
Content in log area is write in three-level mapping table by block, also, in order to save the memory space of flash, it is also desirable to by day
The content in will area is deleted.
The embodiment of the present invention provides a kind of storage system power-off protection method, as shown in Fig. 2, this method can be by above-mentioned
Storage control executes.
It should be noted that the storage control can specifically include MRAM controller and SSD controller, wherein MRAM
Controller can be used for monitoring the state of level-one mapping table and log buffer area in MRAM, for example, judging depositing for log buffer area
Whether storage space reaches certain threshold value, in addition, MRAM controller can also notify SSD controller to execute according to the state of MRAM
Corresponding operating；Similarly, SSD controller can be used for monitoring the shape of second level mapping table in flash, three-level mapping table and log area
State, for example, judging whether the mapping relations of the data in current three-level mapping table need to flush to second level mapping table and one step by step
In grade mapping table, in addition, SSD controller can also notify MRAM controller to execute corresponding operating according to the state of flash.
In addition, the specific implementation process of above-mentioned storage control can propose that this will not be repeated here below, and above-mentioned SSD
Controller and MRAM controller are only used as a kind of concrete implementation mode of storage control, it is not limited to above-mentioned realization side
Formula.
This method process includes:
101, after the previous lower electricity of CPU belongs to abnormal lower electricity, storage control is true according to the index information of level-one mapping table
Determine the physical address of second level mapping table, and second level mapping table is found according to the physical address of second level mapping table, by accessing second level
The index information of mapping table determines the physical address of three-level mapping table, finds three according to the physical address of three-level mapping table later
Grade mapping table, determines the index information of three-level mapping table.
102, storage control read log buffer area in all data mapping relations and log area in all data
Mapping relations.
103, storage control to CPU sends the index information of three-level mapping table, all data reflects in log buffer area
Penetrate the mapping relations of all data in relationship and log area.
104, when storage control in CPU according to all data in the index information of three-level mapping table, log buffer area
Mapping relations judgement have at least one data the mapping relations in log buffer area or mapping relations in log area with
When mapping relations in three-level mapping table are inconsistent, using at least one data in the mapping relations in log buffer area or in day
Mapping relations in will area replace the mapping relations in three-level mapping table.
Wherein, in replacement, preferentially the mapping relations using at least one data in log buffer area are replaced.
105, storage control updates the index information of second level mapping table according to the three-level mapping table after refreshing, later basis
Updated second level mapping table updates the index information of level-one mapping table, and by updated second level mapping table before the update after
The mapping relations to change are saved to DRAM.
In the present invention, in order to save the storage resource of flash, updated second level mapping table can be saved in DRAM
Later, the second level mapping table in flash is emptied.
It should be noted that when CPU normally lower electricity, in software view, some program module (examples of storage control
Such as, drive) electrical interface under algorithm can be called, it is electrically operated under notice algorithm progress is normal；Algorithm calls saveMap3inSSD letter
Number, and by driving logic that will write in flash under the three-level mapping table of updates all in DRAM, and return to new write-in flash
The physical address of middle three-level mapping table；It is updated according to the physical address for the three-level mapping table being newly written in the flash of return
The content of second level mapping table in DRAM；The second level mapping table for having update all in updated DRAM is write in flash, and
Return to the physical address of new write-in second level mapping table；The level-one that the physical address of the second level mapping table of return is saved in MRAM is reflected
In firing table；It is all set to executing garbage by all pieces in log area current in flash, and electrically operated under return algorithm to driving
It completes, while driving and can will be used to react whether previous lower electric process belongs to abnormal lower electricity in the register of storage control
Flag bit flag is set as 1, that is, indicates that previous lower electric process belongs to normal lower electricity.
In the present invention, high speed nonvolatile memory refers to read or write speed ratio flash faster, meanwhile, it every time can be direct
The granularity of operation data it is smaller (for example, by byte operated rather than flash operated by block) memory, example
Such as, MRAM or PCM.But high speed nonvolatile memory typically cost ratio flash high, capacity is also smaller than flash, can not be suitble to
Large-scale use.
In the present embodiment, data are saved provided with multiple positions such as mapping tables at different levels and log buffer area, log area
Mapping relations so that CPU power-off after, storage control can be restored according to each mapping relations of preservation, in this mistake
Cheng Zhong is searched one by one by then passing through mapping tables at different levels, rather than uses the mode of prior art scan full hard disk, because
This, improves speed during searching the mapping relations of data.
On the other hand, when saving each mapping relations, high speed nonvolatile memory and flash are also fully utilized by
The characteristics of.Specifically, by taking high speed nonvolatile memory is MRAM as an example, it, can be by log due to the fireballing characteristic of MRAM
Buffer area is put in a mram, since CPU is when writing DRAM for data mapping relations, can also write MRAM, this is a using frequency
The very high operation of rate can impact whole system if speed is slow, therefore, save log buffer used here as MRAM
The data in area can utmostly guarantee the performance of system.
Meanwhile level-one mapping table is also also disposed in MRAM by the present embodiment, due to level-one mapping table be for search two,
Three-level mapping table, so must first know the address of level-one mapping table, and this address needs to fix.If level-one mapped
Table is placed in a piece of fixing address of flash, due to the characteristic of flash itself, when constantly reading and writing this part region, can be generated
More abrasions, eventually lead to flash and break down.And it MRAM and therefore can specially open up in a mram there is no this problem
One piece of region carries out the placement of level-one mapping table.Simultaneously as the capacity of level-one mapping table (only will not save second level greatly very much
The index information of table), therefore, MRAM is suitable for use of to save mapping table.And other tables are (for example, second level mapping table, three-level are reflected
Firing table) occupied space is relatively large, and the characteristic that can use flash large capacity is placed in flash, is matched to be optimal
It sets.
Due to before CPU is this time powered on, CPU may be normally under electric or abnormal lower electricity, and different lower electric shape
State triggers different process flows when CPU can be made to power on again, therefore, in an implementation of the embodiment of the present invention,
When CPU is powered on, the lower electric process that can determine before this by reading the flag bit that storage control is sent belong to it is normal under
It is electrically operated under electricity or exception, different process flows is selected according to power-down state later.Therefore, it after CPU is powered on, deposits
Storage controller reports the flag bit for reflecting abnormal lower electricity to CPU.
Specifically, flag bit can be located at the register in storage control, and in CPU normally lower electricity, storage control
In driving flag bit can be configured, for example set 1 for flag bit flag；And when electric under CPU exception, due to depositing
Controller power-off is stored up, therefore is unable to complete the operation being configured to flag bit, therefore, is read when CPU is powered on again
Flag value be a value (such as 0) in normal work, rather than when 1, show that electricity is extremely lower electricity under last time CPU.It needs
Illustrate, for distinguishing whether CPU is that the mode of normal lower electricity is not limited only to the implementation of above-mentioned setting flag bit, may be used also
Think that other can be used for distinguishing other operations of CPU power-down state, this will not be repeated here.
In this embodiment, by the way of above-mentioned reading flag bit, storage control can be made rapidly and effectively to distinguish
Whether previous lower electricity belongs to abnormal lower electricity, if belonging to normal lower electricity, that triggers CPU normally powers on process, otherwise, then in triggering
It states exception and powers on process.
In the present embodiment, CPU normally powers on process are as follows: the driving that CPU receives storage control reads flag bit, adjusts
With algorithm initialization interface, flag bit is transmitted.As flag bit flag=1, algorithm normal call powers on process.I.e. algorithm passes through
Logic is driven, reads the content of level-one mapping table in high speed nonvolatile memory, and according to two recorded in level-one mapping table
The physical address of grade mapping table, finds the position of second level mapping table in flash, accesses the content of second level mapping table, will read
The content of second level mapping table be stored in main memory, that is, be stored in DRAM, and returned to driving and determine information.
When CPU is normally to power on, CPU can be directly according to the level-one mapping table stored in high speed nonvolatile memory
In mapping relations find the physical address for being stored in the second level mapping table of SSD, access second level mapping table later, and second level reflected
Mapping relations in firing table are synchronized in DRAM, in order to subsequent reads access according to when, can according to the second level mapping table in DRAM,
It determines physical address that three-level mapping table stores in flash, and determines the storage of data by access three-level mapping table
Address.
When CPU is abnormal powers on, i.e. the previous lower electricity of CPU belongs to abnormal lower electricity, and storage medium, which also has little time to execute, appoints
What operation just power down.It means that the mapping relations being stored in DRAM are lost because of abnormal lower electricity, only have
The data stored in the high speed nonvolatile memory and flash of non-volatile nature still retain.Therefore, storage control can
To find the physical address for being stored in the second level mapping table of flash according to the mapping relations in level-one mapping table, two are accessed later
Grade mapping table, and the physical address for being stored in the three-level mapping table of flash is found according to the mapping relations in second level mapping table, and
Read the mapping relations of the data stored in three-level mapping table.
In another embodiment, for convenience by the log area for writing flash under the content batch in log buffer area,
Log buffer area can be divided into n queue, wherein n queue can indicate that n is more than or equal to 1 with Q0 to Qn
Positive integer, log area includes at least two blocks, and each block corresponds to the column in log buffer area.In the embodiment of the present invention
In, when meeting certain condition, the content stored in log buffer area can be write log area by queue by storage control.Cause
This, after the memory space in log buffer area reaches first threshold, it is slow that storage control reads log from log buffer area
The mapping relations of the data in area are deposited, and are saved in log area, specifically may be implemented are as follows:
After the memory space of target column reaches first threshold in log buffer area, storage control is by data in target column
Mapping relations store into log area the corresponding position of target block, target block is the corresponding block of target column.
It should be noted that block can be considered as one piece of region corresponding with queue.The composition of block is phase with queue
With, it is one piece of region being made of multiple list items.
Such as: when MRAM is in state as shown in Figure 3, if CPU is normally lower electric, storage control can be by log
Mapping relations in Q0 to the Qn queue of buffer area write the log area of flash, and the memory space in log buffer area reaches
To after first threshold, by the content refresh in log area to three-level mapping table and second level mapping table and level-one mapping table, i.e., most
Refresh the mapping table index area in MRAM eventually.Wherein, the content in three-level mapping table is flushed into second level mapping table and one step by step
The process of grade mapping table, can propose, this will not be repeated here later.It should be noted that Tu Zhong state table area corresponds to flash's
Each block in log area, therefore, when three-level mapping table updates, the state table area in MRAM also be will be updated.
As shown in figure 4, the log in MRAM is delayed after to write the mapping relations generated and correspond to queue in MRAM
Deposit the storage state in area.
As shown in figure 5, after memory space of the Q0 into Qn queue there are at least one queue reaches the first threshold,
Then the mapping relations for the data that at least one queue is stored are write in the log area of flash, basis has been write later
The mapping relations of the log area of flash update state table area.
After CPU carries out normal lower electricity, the storage state of high speed nonvolatile memory is as shown in fig. 6, i.e. log is slow
The log area that the data in Q0 to the Qn queue in area have write flash is deposited, and after completing write operation, removes log buffer area
All the elements.
When CPU is electric under sometime exception, that is, when CPU is abnormal power down, storage medium also has little time to hold
Any operation just power down of row, then the storage state of MRAM is any one state as shown in Fig. 3 to 5.At this point, MRAM
In content be not carried out any operation, flag bit is not also modified, and as CPU descends electricity extremely.
When CPU is powered on again, storage control first reads flag bit and is reported to CPU, can determine that CPU is different in this way
Often power on.At this point, Q0 stores newest or newer map information into Qn queue, log area, in mapping tables at different levels
Partial content is non-current map information.Storage control can read Q0 to Qn queue, log area and three-level with blockette
The content that mapping table is stored, and be compared.Wherein, the newness degree of mapping relations be followed successively by Q0 to Qn queue, log area,
Three-level mapping table.After, storage control can refresh three-level mapping table according to newest map information, thus full
Second level mapping table and level-one mapping table are updated step by step after the certain flush condition of foot, empty Q0 later to Qn queue and log
Area, to complete the recovery of mapping relations.
In the present invention, it is contemplated that the limited storage space in log buffer area so can not only guarantee log
There are enough idle storage resources in buffer area, while can also guarantee, the mapping relations of data are write flash's in batches
In log area, that is, log area is met for the memory requirement of the mapping relations of data.
In an implementation of the embodiment of the present invention, when electronic equipment works normally, step by step from three-level mapping table
The process for refreshing second level mapping table and level-one mapping table, can be implemented as implementation as shown in Figure 7:
If 201, three-level mapping table reaches third threshold value by the quantity of modification entry after refreshing, storage control according to
Three-level mapping table after refreshing refreshes the index information of second level mapping table.
If 202, second level mapping table reaches the 4th threshold value by the quantity of modification entry after refreshing, storage control according to
Second level mapping table after refreshing updates the index information of level-one mapping table.
It is according to reflecting it can be seen that during refreshing second level mapping table and level-one mapping table step by step from three-level mapping table
Firing table determines the need for flushing to next stage mapping table by the quantity of modification entry after refreshing.Take above-mentioned refreshed
Journey can not only meet the needs of flash is for write operation, meanwhile, it can also reduce to refresh and carry out the secondary of write operation
Number.
It is above-mentioned that mainly the angle of storage control is situated between to scheme provided in an embodiment of the present invention from electronic equipment
It continues.It is understood that storage control is in order to realize the above functions, it comprises execute each corresponding hardware configuration of function
And/or software module.Those skilled in the art should be readily appreciated that, described in conjunction with the examples disclosed in this document each
Exemplary unit and algorithm steps, the present invention can be realized with the combining form of hardware or hardware and computer software.Some
Function is executed in a manner of hardware or computer software driving hardware actually, depending on technical solution specific application and set
Count constraint condition.Professional technician can use different methods to achieve the described function each specific application,
But such implementation should not be considered as beyond the scope of the present invention.
The embodiment of the present invention can carry out the division of functional module, example according to above method example to storage control etc.
Such as, each functional module of each function division can be corresponded to, two or more functions can also be integrated at one
It manages in module.Above-mentioned integrated module both can take the form of hardware realization, can also use the form of software function module
It realizes.It should be noted that being schematical, only a kind of logic function stroke to the division of module in the embodiment of the present invention
Point, there may be another division manner in actual implementation.
In the case where functional module each using corresponding each function division, or the case where using integrated unit
Under, Fig. 8 shows a kind of possible structural schematic diagram of storage control involved in above-described embodiment.Storage control 30
It comprises determining that module 31, obtain module 32, sending module 33, processing module 34 and memory module 35.For example, determining module 31,
For executing the process 101 of Fig. 2；Module 32 is obtained, for executing the process 102 of Fig. 2；Sending module 33, for executing Fig. 2's
Process 103；Processing module 34, for executing the process 104 and process 105 and the process of Fig. 4 201 and process 202 of Fig. 2；It deposits
Module 35 is stored up, for saving the program code and data of storage control.Wherein, each step that above method embodiment is related to
All related contents can quote the function description of corresponding function module, and details are not described herein.
Above-mentioned determining module 31 and processing module 34 can integrate on a processor, which can be central processing unit
(English: Central Processing Unit, referred to as: CPU), general processor, digital signal processor (English:
Digital Signal Processor, referred to as: DSP), specific integrated circuit (English: Application-Specific
Integrated Circuit, referred to as: ASIC), field programmable gate array (English: Field Programmable Gate
Array, referred to as: FPGA) either other programmable logic device, transistor logic, hardware component or any combination thereof.
It, which may be implemented or executes, combines various illustrative logic blocks, module and circuit described in the disclosure of invention.Institute
It states processor to be also possible to realize the combination of computing function, such as is combined comprising one or more microprocessors, DSP and micro process
Combination of device etc..It obtains module 32 and sending module 33 is specifically as follows transceiver, transmission circuit or communication interface etc..Storage
Module 35 can be memory.
When determining module 31 and processing module 34 are processor, obtaining module 32 and sending module 33 is communication interface, is deposited
When storage module 35 is memory, storage control involved in the embodiment of the present invention can be storage control 40 shown in Fig. 9.
As shown in fig.9, the storage control 40 includes: processor 41, communication interface 42, memory 43 and bus
44.Wherein, processor 41, communication interface 42 and memory 43 are connected with each other by bus 44；Bus 44 can be external components
Interconnection standards (English: Peripheral Component Interconnect, abbreviation: PCI) bus or extension industrial standard knot
Structure (English: Extended Industry Standard Architecture, referred to as: EISA) bus etc..The bus can be with
It is divided into address bus, data/address bus, control bus etc..Only to be indicated with a thick line in Fig. 9 convenient for indicating, it is not intended that
Only a bus or a type of bus.
The step of method in conjunction with described in the disclosure of invention or algorithm can realize in a manner of hardware, can also
It is realized in a manner of being to execute software instruction by processor.Software instruction can be made of corresponding software module, software mould
Block can be stored on random access memory (English: Random Access Memory, referred to as: RAM), flash memory, read-only deposit
Reservoir (English: Read Only Memory, abbreviation: ROM), Erasable Programmable Read Only Memory EPROM (English: Erasable
Programmable ROM, referred to as: EPROM), Electrically Erasable Programmable Read-Only Memory (English: Electrically EPROM,
Referred to as: EEPROM), register, hard disk, mobile hard disk, CD-ROM (referred to as: CD-ROM) or it is well known in the art it is any its
In the storage medium of its form.A kind of illustrative storage medium is coupled to processor, to enable a processor to from the storage
Medium reads information, and information can be written to the storage medium.Certainly, storage medium is also possible to the component part of processor.
Pocessor and storage media can be located in ASIC.
Those skilled in the art are it will be appreciated that in said one or multiple examples, function described in the invention
It can be realized with hardware, software, firmware or their any combination.It when implemented in software, can be by these functions
Storage in computer-readable medium or as on computer-readable medium one or more instructions or code transmitted.
Computer-readable medium includes computer storage media and communication media, and wherein communication media includes convenient for from a place to another
Any medium of one place transmission computer program.Storage medium can be general or specialized computer can access it is any
Usable medium.
Above-described specific embodiment has carried out further the purpose of the present invention, technical scheme and beneficial effects
It is described in detail, it should be understood that being not intended to limit the present invention the foregoing is merely a specific embodiment of the invention
Protection scope, all any modification, equivalent substitution, improvement and etc. on the basis of technical solution of the present invention, done should all
Including within protection scope of the present invention.
Claims (9)
1. a kind of storage system power-off protection method, which is characterized in that the method is used for a kind of electronic equipment, and the electronics is set
It include: central processor CPU, storage control, flash memory flash, high speed nonvolatile memory and dynamic randon access in standby
DRAM memory is preserved level-one mapping table and log buffer area in the high speed nonvolatile memory, is protected in the flash
There are second level mapping table, three-level mapping table and log area, wherein
When the log buffer area is worked normally for being stored in the electronic equipment, the CPU is by the mapping relations of data
While writing DRAM, the mapping relations of data described in the log buffer area are write by the storage control；
If the log area is used for after the memory space in the log buffer area reaches first threshold, the storage control is saved
The mapping relations for the data that device processed is read from the log buffer area；
The index information of the three-level mapping table is the mapping relations of data, and the three-level mapping table is used in the log area
Data when reaching second threshold, the three-level mapping table is refreshed and saves the mapping relations of data in the log area；
The index information of the level-one mapping table is the mapping relations of the second level mapping table；
The index information of the second level mapping table is the mapping relations of the three-level mapping table；
The mapping relations are the corresponding relationship of logical address and physical address；
The described method includes:
After the previous lower electricity of the CPU belongs to abnormal lower electricity, the storage control is true according to the index information of level-one mapping table
Determine the physical address of second level mapping table, and second level mapping table is found according to the physical address of second level mapping table, by accessing second level
The index information of mapping table determines the physical address of three-level mapping table, finds three according to the physical address of three-level mapping table later
Grade mapping table, determines the index information of three-level mapping table；
The storage control is read in the log buffer area to be owned in the mapping relations of all data and the log area
The mapping relations of data；
The storage control sends the index information of the three-level mapping table to the CPU, owns in the log buffer area
The mapping relations of all data in the mapping relations of data and the log area；
When the storage control in the CPU according to institute in the index information of the three-level mapping table, the log buffer area
Having the mapping relations judgement of data has at least one data in the mapping relations in the log buffer area or in the log area
In mapping relations it is inconsistent with mapping relations in the three-level mapping table when, using at least one described data described
The mapping relations in log buffer area replace reflecting in the three-level mapping table in the mapping relations in the log area
Penetrate relationship, wherein preferential to be replaced using the mapping relations of at least one data in the log buffer area in replacement
It changes；
The storage control updates the index information of second level mapping table according to the three-level mapping table after refreshing, later according to update
Second level mapping table afterwards updates the index information of level-one mapping table, and will occur afterwards before the update in updated second level mapping table
The mapping relations of change are saved to the DRAM.
2. the method according to claim 1, wherein after the CPU is powered on, the method also includes:
The storage control reports the flag bit for reflecting abnormal lower electricity to the CPU, and the flag bit is located at described deposit
The register of controller is stored up, so that the CPU judges whether previous lower electricity belongs to abnormal lower electricity according to the flag bit.
3. method according to claim 1 or 2, which is characterized in that the log buffer area is divided into n queue, institute
State n queue is indicated with Q1 to Qn, wherein n is the positive integer more than or equal to 1, and the log area includes at least two blocks,
And each block corresponds to a queue in the log buffer area；
After the memory space in the log buffer area reaches first threshold, the storage control is from the log buffer area
The middle mapping relations for reading the data in the log buffer area, and it is saved in the log area, it specifically includes:
After the memory space of target column reaches the first threshold in the log buffer area, the storage control will be described
The mapping relations of data store into the log area the corresponding position of target block in target column, and the target block is described
The corresponding block of target column.
4. the method according to claim 1, wherein the method is also when the electronic equipment works normally
Include:
If the three-level mapping table reaches third threshold value by the quantity of modification entry after refreshing, the storage control according to
Three-level mapping table after refreshing refreshes the index information of second level mapping table；
If the second level mapping table reaches the 4th threshold value by the quantity of modification entry after refreshing, the storage control according to
Second level mapping table after refreshing updates the index information of level-one mapping table.
5. a kind of storage control, which is characterized in that the storage control is used for a kind of electronic equipment, in the electronic equipment
Further include: central processor CPU, flash memory flash, high speed nonvolatile memory and dynamic random access memory DRAM, institute
It states and preserves level-one mapping table and log buffer area in high speed nonvolatile memory, second level mapping is preserved in the flash
Table, three-level mapping table and log area, wherein
When the log buffer area is worked normally for being stored in the electronic equipment, the CPU is by the mapping relations of data
While writing DRAM, the mapping relations of data described in the log buffer area are write by the storage control；
If the log area is used for after the memory space in the log buffer area reaches first threshold, the storage control is saved
The mapping relations for the data that device processed is read from the log buffer area；
The index information of the three-level mapping table is the mapping relations of data, and the three-level mapping table is used in the log area
Data when reaching second threshold, the three-level mapping table is refreshed and saves the mapping relations of data in the log area；
The index information of the level-one mapping table is the mapping relations of the second level mapping table；
The index information of the second level mapping table is the mapping relations of the three-level mapping table；
The mapping relations are the corresponding relationship of logical address and physical address；
The storage control includes:
Determining module, for being determined according to the index information of level-one mapping table after the previous lower electricity of the CPU belongs to abnormal lower electricity
The physical address of second level mapping table, and second level mapping table is found according to the physical address of second level mapping table, it is reflected by accessing second level
The index information of firing table determines the physical address of three-level mapping table, finds three-level according to the physical address of three-level mapping table later
Mapping table determines the index information of three-level mapping table；
Module is obtained, is owned in the mapping relations of all data and the log area for reading in the log buffer area
The mapping relations of data；
Sending module, for sending the index information of the three-level mapping table to the CPU, all numbers in the log buffer area
According to mapping relations and the log area in all data mapping relations；
Processing module, for when the storage control is in index information of the CPU according to the three-level mapping table, the day
In will buffer area the mapping relations judgement of all data have at least one data in the mapping relations in the log buffer area or
In the mapping relations in the log area and the inconsistent mapping relations in the three-level mapping table, described at least one is used
A data are replaced in the mapping relations in the log buffer area or the mapping relations in the log area in the three-level
Mapping relations in mapping table, wherein preferential to use at least one data reflecting in the log buffer area in replacement
The relationship of penetrating is replaced；
The processing module is also used to update the index information of second level mapping table, Zhi Hougen according to the three-level mapping table after refreshing
According to updated second level mapping table update level-one mapping table index information, and by updated second level mapping table before the update
The mapping relations to change afterwards are saved to the DRAM.
6. storage control according to claim 5, which is characterized in that after the CPU is powered on, the transmission mould
Block is also used to report the flag bit for reflecting abnormal lower electricity to the CPU, and the flag bit is located at the storage control
Register, so that the CPU judges whether previous lower electricity belongs to abnormal lower electricity according to the flag bit.
7. storage control according to claim 5 or 6, which is characterized in that the log buffer area is divided into n team
Column, the n queue are indicated with Q0 to Qn, wherein n is the positive integer more than or equal to 1, and the log area includes at least two
Block, and each block corresponds to the column in the log buffer area；
The storage control further include:
Memory module will be described if the memory space for target column in the log buffer area reaches the first threshold
The mapping relations of data store into the log area the corresponding position of target block in target column, and the target block is described
The corresponding block of target column.
8. storage control according to claim 5, which is characterized in that described when the electronic equipment works normally
Processing module is also used to:
If the three-level mapping table reaches third threshold value by the quantity of modification entry after refreshing, reflected according to the three-level after refreshing
The index information of firing table refreshing second level mapping table；
If the second level mapping table reaches the 4th threshold value by the quantity of modification entry after refreshing, reflected according to the second level after refreshing
The index information of firing table update level-one mapping table.
9. a kind of electronic equipment, which is characterized in that include: central processor CPU, such as claim 5 to 8 in the electronic equipment
Any one of described in storage control, flash memory flash, high speed nonvolatile memory and dynamic random access memory
DRAM preserves level-one mapping table and log buffer area in the high speed nonvolatile memory, preserves two in the flash
Grade mapping table, three-level mapping table and log area, wherein
When the log buffer area is worked normally for being stored in the electronic equipment, the CPU is by the mapping relations of data
While writing DRAM, the mapping relations of data described in the log buffer area are write by the storage control；
If the log area is used for after the memory space in the log buffer area reaches first threshold, the storage control is saved
The mapping relations for the data that device processed is read from the log buffer area；
The index information of the three-level mapping table is the mapping relations of data, and the three-level mapping table is used in the log area
Data when reaching second threshold, the three-level mapping table is refreshed and saves the mapping relations of data in the log area；
The index information of the level-one mapping table is the mapping relations of the second level mapping table；
The index information of the second level mapping table is the mapping relations of the three-level mapping table；
The mapping relations are the corresponding relationship of logical address and physical address.
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| CN201610872062.0A CN106502928B (en) | 2016-09-29 | 2016-09-29 | A kind of storage system power-off protection method, storage control and electronic equipment |
| PCT/CN2017/103249 WO2018059361A1 (en) | 2016-09-29 | 2017-09-25 | Power down protection method for storage system, storage controller, and electronic device |
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Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106502928B (en) * | 2016-09-29 | 2019-08-20 | 华为技术有限公司 | A kind of storage system power-off protection method, storage control and electronic equipment |
| CN107168888B (en) * | 2017-05-19 | 2020-06-02 | 惠州佰维存储科技有限公司 | Mapping table management method and system of Nand flash memory |
| KR102430791B1 (en) * | 2017-07-19 | 2022-08-10 | 에스케이하이닉스 주식회사 | Controller and operation method thereof |
| CN107506311B (en) * | 2017-08-30 | 2020-10-20 | 苏州浪潮智能科技有限公司 | Method and device for flashing FTL (flash translation layer) table of solid state disk |
| CN108228376A (en) * | 2017-12-29 | 2018-06-29 | 北京联想核芯科技有限公司 | A kind of data processing method and device of SSD hard disks |
| CN108647157B (en) * | 2018-03-14 | 2021-10-01 | 深圳忆联信息系统有限公司 | Mapping management method based on phase change memory and solid state disk |
| CN108804026B (en) * | 2018-03-27 | 2022-02-18 | 深圳忆联信息系统有限公司 | Solid state disk full-disk scanning method and solid state disk |
| CN108804033B (en) * | 2018-05-18 | 2021-04-20 | 记忆科技(深圳)有限公司 | Full-disk scanning method and device based on power-off continuation, computer equipment and medium |
| CN108959589B (en) * | 2018-07-11 | 2021-08-10 | 中电海康集团有限公司 | STT-MRAM-based method for accelerating log file saving and recovery of solid-state memory device |
| CN109086222B (en) * | 2018-07-24 | 2023-08-25 | 浪潮电子信息产业股份有限公司 | Data recovery method of solid state disk and solid state disk |
| CN109059913B (en) * | 2018-08-27 | 2021-08-03 | 立得空间信息技术股份有限公司 | Zero-delay integrated navigation initialization method for vehicle-mounted navigation system |
| CN109213690A (en) * | 2018-09-21 | 2019-01-15 | 浪潮电子信息产业股份有限公司 | A kind of method for reconstructing and relevant apparatus of L2P table |
| CN109684238A (en) * | 2018-12-19 | 2019-04-26 | 湖南国科微电子股份有限公司 | A kind of storage method, read method and the solid state hard disk of solid state hard disk mapping relations |
| CN110502452B (en) * | 2019-07-12 | 2022-03-29 | 华为技术有限公司 | Method and device for accessing mixed cache in electronic equipment |
| CN112346647B (en) * | 2019-08-06 | 2024-03-29 | 浙江宇视科技有限公司 | Data storage method, device, equipment and medium |
| CN110543434B (en) * | 2019-09-05 | 2022-07-01 | 北京兆易创新科技股份有限公司 | NAND flash device, memory table management method, device and storage medium |
| CN111142792B (en) * | 2019-12-17 | 2022-11-22 | 尧云科技(西安)有限公司 | Power-down protection method of storage device |
| US11138110B1 (en) * | 2020-04-30 | 2021-10-05 | Sage Microelectronics Corporation | Data management for memory devices |
| CN111858508B (en) * | 2020-06-17 | 2023-01-31 | 远光软件股份有限公司 | Regulation and control method and device of log system, storage medium and electronic equipment |
| CN111832088B (en) * | 2020-07-13 | 2024-02-13 | 深圳忆联信息系统有限公司 | Method and device for protecting data in low-power-consumption mode of solid state disk, computer equipment and storage medium |
| CN112395215B (en) * | 2020-12-03 | 2024-02-13 | 深圳忆联信息系统有限公司 | DRAM-less solid state disk mapping table management method and device, computer equipment and storage medium |
| JP2022114726A (en) | 2021-01-27 | 2022-08-08 | キオクシア株式会社 | Memory system and control method |
| CN113568579B (en) * | 2021-07-28 | 2022-05-03 | 深圳市高川自动化技术有限公司 | Memory, data storage method and data reading method |
| CN114168076A (en) * | 2021-12-06 | 2022-03-11 | 陕西空天动力研究院有限公司 | Data storage method, device and system |
| CN116909493B (en) * | 2023-09-12 | 2023-11-17 | 合肥康芯威存储技术有限公司 | Memory and control method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102981963A (en) * | 2012-10-30 | 2013-03-20 | 华中科技大学 | Implementation method for flash translation layer of solid-state disc |
| CN103294607A (en) * | 2012-02-27 | 2013-09-11 | 北京华虹集成电路设计有限责任公司 | Memory management method |
| CN105511583A (en) * | 2015-12-02 | 2016-04-20 | 福建星网锐捷网络有限公司 | Power-fail protection circuit and method for storage device |
| CN105760313A (en) * | 2015-08-07 | 2016-07-13 | 深圳市证通金信科技有限公司 | Data processing method and device for SPI-Flash-based (Serial Peripheral Interface-Flash-based) file system |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101782875B (en) * | 2010-01-29 | 2012-01-04 | 成都市华为赛门铁克科技有限公司 | Storage unit and data storage method |
| US9164887B2 (en) * | 2011-12-05 | 2015-10-20 | Industrial Technology Research Institute | Power-failure recovery device and method for flash memory |
| CN106502928B (en) * | 2016-09-29 | 2019-08-20 | 华为技术有限公司 | A kind of storage system power-off protection method, storage control and electronic equipment |
-
2016
- 2016-09-29 CN CN201610872062.0A patent/CN106502928B/en active Active
-
2017
- 2017-09-25 WO PCT/CN2017/103249 patent/WO2018059361A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103294607A (en) * | 2012-02-27 | 2013-09-11 | 北京华虹集成电路设计有限责任公司 | Memory management method |
| CN102981963A (en) * | 2012-10-30 | 2013-03-20 | 华中科技大学 | Implementation method for flash translation layer of solid-state disc |
| CN105760313A (en) * | 2015-08-07 | 2016-07-13 | 深圳市证通金信科技有限公司 | Data processing method and device for SPI-Flash-based (Serial Peripheral Interface-Flash-based) file system |
| CN105511583A (en) * | 2015-12-02 | 2016-04-20 | 福建星网锐捷网络有限公司 | Power-fail protection circuit and method for storage device |
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| CN106502928A (en) | 2017-03-15 |
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